Unified Coverage Report :: Module :: prim_mubi8_sender

Module : prim_mubi8_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre	83.33	50.00				100.00	100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.90	96.91	100.00		95.24	100.00	82.35	gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.90	96.91	100.00		95.24	100.00	82.35	gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	94.16	95.24	97.30		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.20	94.51	100.00		85.00	95.35	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.20	94.51	100.00		85.00	95.35	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.20	94.51	100.00		85.00	95.35	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.13	100.00	100.00		95.65	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.13	100.00	100.00		95.65	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.13	100.00	100.00		95.65	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	100.00	100.00		95.24	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	100.00	100.00		95.24	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	100.00	100.00		95.24	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.18	97.64	95.24		92.00	98.15	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.18	97.64	95.24		92.00	98.15	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.18	97.64	95.24		92.00	98.15	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.68	96.00	93.75		88.89	95.31	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.68	96.00	93.75		88.89	95.31	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.68	96.00	93.75		88.89	95.31	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.68	96.00	93.75		88.89	95.31	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.50	98.00	93.75		94.44	96.88	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.50	98.00	93.75		94.44	96.88	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.50	98.00	93.75		94.44	96.88	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.50	98.00	93.75		94.44	96.88	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	98.00	93.75		97.22	96.88	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	98.00	93.75		97.22	96.88	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	98.00	93.75		97.22	96.88	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.06	98.00	93.75		97.22	96.88	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi8_sender

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Module : prim_mubi8_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_mubi8_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	291840	287394	0	0
T2	729486	718770	0	0
T3	577239	559854	0	0
T4	3147198	3086379	0	0
T5	1028736	1016595	0	0
T9	1289454	1273209	0	0
T10	3405807	3402558	0	0
T11	257298	254106	0	0
T12	686223	671460	0	0
T13	2729730	2726253	0	0

Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         0/1     ==>    assign mubi = MuBi8Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         0/1     ==>      assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         0/1     ==>    assign mubi_o = mubi8_t'(mubi_out);

---

Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T4 T35 T51 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T4 T35 T51 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T4 T35 T51 

---

Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T4 T35 T51 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T4 T35 T51 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T4 T35 T51 

---

Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T4 T35 T51 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T4 T35 T51 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T4 T35 T51 

---

Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T4 T35 T51 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T4 T35 T51 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T4 T35 T51 

---

Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T4 T51 T55 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T4 T51 T55 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T4 T51 T55 

---

Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi8Width-1:0] mubi, mubi_int, mubi_out;
34         1/1            assign mubi = MuBi8Width'(mubi_i);
           Tests:       T1 T2 T3 
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi8Width),
40                            .ResetValue(MuBi8Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48         1/1              assign mubi_int = mubi;
           Tests:       T1 T2 T3 
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi8_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
56         1/1                   unused_logic <= MuBi8False;
           Tests:       T1 T2 T3 
57                            end else begin
58         1/1                   unused_logic <= mubi_i;
           Tests:       T1 T2 T3 
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(8)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(8)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82                          assign mubi_out = mubi_int;
83                        end
84                      
85         1/1            assign mubi_o = mubi8_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

55               if (!rst_ni) begin
                 -1-  
56                  unused_logic <= MuBi8False;
                    ==>
57               end else begin
58                  unused_logic <= mubi_i;
                    ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	84443599	83613730	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0