Unified Coverage Report :: Module :: otp_ctrl

Module : otp_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.55	92.95	86.96	87.55		93.10	97.18

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	96.06	94.16	95.24	97.30		96.43	97.18

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.06	94.16	95.24	97.30		96.43	97.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	93.68	96.65	96.02	92.29	97.50	96.37

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
core_tlul_assert_device	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
gen_alert_tx[3].u_prim_alert_sender	100.00			100.00
gen_alert_tx[4].u_prim_alert_sender	100.00			100.00
gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[10].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[10].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[8].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[8].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[9].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[9].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf	95.54	96.38	100.00	100.00	85.00	94.64	97.22
gen_partitions[10].gen_lifecycle.u_part_buf	91.64	90.44	100.00	78.09	95.24	100.00	86.05
gen_partitions[1].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[2].gen_unbuffered.u_part_unbuf	98.98	100.00	100.00	100.00	95.65	98.25	100.00
gen_partitions[3].gen_unbuffered.u_part_unbuf	98.32	100.00	100.00	100.00	91.67	98.25	100.00
gen_partitions[4].gen_unbuffered.u_part_unbuf	98.90	100.00	100.00	100.00	95.24	98.18	100.00
gen_partitions[5].gen_buffered.u_part_buf	95.11	98.28	95.24	100.00	92.00	98.51	86.67
gen_partitions[6].gen_buffered.u_part_buf	93.40	96.65	92.86	100.00	91.67	92.54	86.67
gen_partitions[7].gen_buffered.u_part_buf	95.28	97.07	93.75	100.00	88.89	96.20	95.74
gen_partitions[8].gen_buffered.u_part_buf	96.66	98.54	93.75	100.00	94.44	97.47	95.74
gen_partitions[9].gen_buffered.u_part_buf	97.12	98.54	93.75	100.00	97.22	97.47	95.74
otp_ctrl_core_csr_assert	100.00						100.00
prim_tlul_assert_device	100.00						100.00
u_edn_arb	87.74	92.31	65.31			100.00	93.33
u_intr_error	100.00	100.00	100.00			100.00	100.00
u_intr_operation_done	100.00	100.00	100.00			100.00	100.00
u_keygmr_key_valid	100.00	100.00				100.00
u_otp	98.91	93.68	99.80	100.00	100.00	100.00	100.00
u_otp_arb	97.25	98.07	97.16			100.00	93.75
u_otp_ctrl_dai	89.65	84.75	91.46	100.00	85.96	88.51	87.23
u_otp_ctrl_kdi	97.21	99.63	99.64	100.00	90.91	95.70	97.37
u_otp_ctrl_lci	100.00	100.00	100.00	100.00	100.00	100.00	100.00
u_otp_ctrl_lfsr_timer	93.08	100.00	89.87	76.92	100.00	91.67	100.00
u_otp_ctrl_scrmbl	96.92	81.50	100.00	100.00	100.00	100.00	100.00
u_otp_init_sync	100.00	100.00				100.00
u_otp_rsp_fifo	100.00	100.00	100.00			100.00	100.00
u_part_sel_idx	74.55	65.65	89.83			88.89	53.85
u_prim_edn_req	92.19	100.00	93.75			100.00	75.00
u_prim_lc_sender_otp_broadcast_valid	100.00	100.00				100.00
u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
u_prim_lc_sender_secrets_valid	100.00	100.00				100.00
u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
u_prim_lc_sync_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_creator_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_owner_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_seed_hw_rd_en	100.00	100.00				100.00	100.00
u_reg_core	99.13	99.65	95.98	100.00		100.00	100.00
u_scrmbl_mtx	79.55	75.00	99.45			100.00	43.75
u_tlul_adapter_sram	97.79	92.05	99.13			100.00	100.00
u_tlul_lc_gate	93.84	99.21	100.00		85.71	96.77	87.50

Line Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
TOTAL		156	145	92.95
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
ALWAYS	284	14	13	92.86
ALWAYS	308	3	3	100.00
ALWAYS	324	11	10	90.91
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	5	5	100.00
ALWAYS	434	19	19	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	9	9	100.00
ALWAYS	521	10	10	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	766	1	1	100.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
ALWAYS	876	2	2	100.00
ALWAYS	934	2	2	100.00
ALWAYS	961	4	4	100.00
CONT_ASSIGN	988	1	1	100.00
ALWAYS	991	3	3	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1079	1	0	0.00
CONT_ASSIGN	1130	1	0	0.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1300	1	0	0.00
CONT_ASSIGN	1312	1	0	0.00
CONT_ASSIGN	1336	1	1	100.00
ALWAYS	1348	2	2	100.00
CONT_ASSIGN	1362	1	1	100.00
ALWAYS	1390	9	9	100.00
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1422	1	1	100.00
CONT_ASSIGN	1424	1	1	100.00
CONT_ASSIGN	1426	1	1	100.00
CONT_ASSIGN	1430	1	1	100.00
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1441	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1475	1	1	100.00
CONT_ASSIGN	1477	1	1	100.00
CONT_ASSIGN	1481	1	1	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00

250                         if (PartInfo[k].offset == 0) begin : gen_zero_offset
251        1/1                assign tlul_part_sel_oh[k] = ({1'b0, {tlul_addr, 2'b00}} < PartEnd);
           Tests:       T1 T2 T3 
252                         end else begin : gen_nonzero_offset
253        10/10              assign tlul_part_sel_oh[k] = ({tlul_addr, 2'b00} >= PartInfo[k].offset) &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
254                                                        ({1'b0, {tlul_addr, 2'b00}} < PartEnd);
255                         end
256                       end
257                     
258                       `ASSERT(PartSelMustBeOnehot_A, $onehot0(tlul_part_sel_oh))
259                     
260                       logic [NumPartWidth-1:0] tlul_part_idx;
261                       prim_arbiter_fixed #(
262                         .N(NumPart),
263                         .EnDataPort(0)
264                       ) u_part_sel_idx (
265                         .clk_i,
266                         .rst_ni,
267                         .req_i   ( tlul_part_sel_oh  ),
268                         .data_i  ( '{default: '0}    ),
269                         .gnt_o   (                   ), // unused
270                         .idx_o   ( tlul_part_idx     ),
271                         .valid_o (                   ), // unused
272                         .data_o  (                   ), // unused
273                         .ready_i ( 1'b0              )
274                       );
275                     
276                       logic tlul_oob_err_d, tlul_oob_err_q;
277                       logic [NumPart-1:0] part_tlul_req, part_tlul_gnt, part_tlul_rvalid;
278                       logic [SwWindowAddrWidth-1:0] part_tlul_addr;
279                       logic [NumPart-1:0][1:0]  part_tlul_rerror;
280                       logic [NumPart-1:0][31:0] part_tlul_rdata;
281                     
282                       always_comb begin : p_tlul_assign
283                         // Send request to the correct partition.
284        1/1              part_tlul_addr   = tlul_addr;
           Tests:       T1 T2 T3 
285        1/1              part_tlul_req    = '0;
           Tests:       T1 T2 T3 
286        1/1              tlul_oob_err_d   = 1'b0;
           Tests:       T1 T2 T3 
287        1/1              if (tlul_req) begin
           Tests:       T1 T2 T3 
288        1/1                if (tlul_part_sel_oh != '0) begin
           Tests:       T2 T3 T4 
289        1/1                  part_tlul_req[tlul_part_idx] = 1'b1;
           Tests:       T2 T3 T4 
290                           end else begin
291                             // Error out in the next cycle if address was out of bounds.
292        0/1     ==>          tlul_oob_err_d = 1'b1;
293                           end
294                         end
                        MISSING_ELSE
295                     
296                         // aggregate TL-UL responses
297        1/1              tlul_gnt         = |part_tlul_gnt    | tlul_oob_err_q;
           Tests:       T1 T2 T3 
298        1/1              tlul_rvalid      = |part_tlul_rvalid | tlul_oob_err_q;
           Tests:       T1 T2 T3 
299        1/1              tlul_rerror      = '0;
           Tests:       T1 T2 T3 
300        1/1              tlul_rdata       = '0;
           Tests:       T1 T2 T3 
301        1/1              for (int k = 0; k < NumPart; k++) begin
           Tests:       T1 T2 T3 
302        1/1                tlul_rerror |= part_tlul_rerror[k];
           Tests:       T1 T2 T3 
303        1/1                tlul_rdata  |= part_tlul_rdata[k];
           Tests:       T1 T2 T3 
304                         end
305                       end
306                     
307                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlul_reg
308        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
309        1/1                tlul_oob_err_q <= 1'b0;
           Tests:       T1 T2 T3 
310                         end else begin
311        1/1                tlul_oob_err_q <= tlul_oob_err_d;
           Tests:       T1 T2 T3 
312                         end
313                       end
314                     
315                       //////////////////////////////
316                       // Access Defaults and CSRs //
317                       //////////////////////////////
318                     
319                       // SEC_CM: ACCESS.CTRL.MUBI
320                       part_access_t [NumPart-1:0] part_access_pre, part_access;
321                       always_comb begin : p_access_control
322                         // Assigns default and extracts named CSR read enables for SW_CFG partitions.
323                         // SEC_CM: PART.MEM.REGREN
324        1/1              part_access_pre = named_part_access_pre(reg2hw);
           Tests:       T1 T2 T3 
325                     
326                         // Permanently lock DAI write and read access to the life cycle partition.
327                         // The LC partition can only be read from and written to via the LC controller.
328                         // SEC_CM: LC_PART.MEM.SW_NOACCESS
329        1/1              part_access_pre[LifeCycleIdx].write_lock = MuBi8True;
           Tests:       T1 T2 T3 
330        1/1              part_access_pre[LifeCycleIdx].read_lock = MuBi8True;
           Tests:       T1 T2 T3 
331                     
332                         // Special partitions for keymgr material only become writable when
333                         // provisioning is enabled.
334        1/1              if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en)) begin
           Tests:       T1 T2 T3 
335        1/1                for (int k = 0; k < NumPart; k++) begin
           Tests:       T1 T2 T3 
336        1/1                  if (PartInfo[k].iskeymgr_creator) begin
           Tests:       T1 T2 T3 
337        1/1                    part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}};
           Tests:       T1 T2 T3 
338                             end
                        MISSING_ELSE
339                           end
340                         end
                        MISSING_ELSE
341        1/1              if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en)) begin
           Tests:       T1 T2 T3 
342        1/1                for (int k = 0; k < NumPart; k++) begin
           Tests:       T1 T2 T3 
343        1/1                  if (PartInfo[k].iskeymgr_owner) begin
           Tests:       T1 T2 T3 
344        0/1     ==>            part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}};
345                             end
                        MISSING_ELSE
346                           end
347                         end
                        MISSING_ELSE
348                       end
349                     
350                       // This prevents the synthesis tool from optimizing the multibit signals.
351                       for (genvar k = 0; k < NumPart; k++) begin : gen_bufs
352                         prim_mubi8_sender #(
353                           .AsyncOn(0)
354                         ) u_prim_mubi8_sender_write_lock (
355                           .clk_i,
356                           .rst_ni,
357                           .mubi_i(part_access_pre[k].write_lock),
358                           .mubi_o(part_access[k].write_lock)
359                         );
360                         prim_mubi8_sender #(
361                           .AsyncOn(0)
362                         ) u_prim_mubi8_sender_read_lock (
363                           .clk_i,
364                           .rst_ni,
365                           .mubi_i(part_access_pre[k].read_lock),
366                           .mubi_o(part_access[k].read_lock)
367                         );
368                       end
369                     
370                       //////////////////////
371                       // DAI-related CSRs //
372                       //////////////////////
373                     
374                       logic                         dai_idle;
375                       logic                         dai_req;
376                       dai_cmd_e                     dai_cmd;
377                       logic [OtpByteAddrWidth-1:0]  dai_addr;
378                       logic [NumDaiWords-1:0][31:0] dai_wdata, dai_rdata;
379                       logic direct_access_regwen_d, direct_access_regwen_q;
380                     
381                       // This is the HWEXT implementation of a RW0C regwen bit.
382        1/1            assign direct_access_regwen_d = (reg2hw.direct_access_regwen.qe &&
           Tests:       T1 T2 T3 
383                                                        !reg2hw.direct_access_regwen.q) ? 1'b0 : direct_access_regwen_q;
384                     
385                       // Any write to this register triggers a DAI command.
386        1/1            assign dai_req = reg2hw.direct_access_cmd.digest.qe |
           Tests:       T1 T2 T3 
387                                        reg2hw.direct_access_cmd.wr.qe  |
388                                        reg2hw.direct_access_cmd.rd.qe;
389                     
390        1/1            assign dai_cmd = dai_cmd_e'({reg2hw.direct_access_cmd.digest.q,
           Tests:       T1 T2 T3 
391                                                    reg2hw.direct_access_cmd.wr.q,
392                                                    reg2hw.direct_access_cmd.rd.q});
393                     
394        1/1            assign dai_addr  = reg2hw.direct_access_address.q;
           Tests:       T1 T2 T3 
395        1/1            assign dai_wdata = reg2hw.direct_access_wdata;
           Tests:       T1 T2 T3 
396                     
397                       // The DAI and the LCI can initiate write transactions, which
398                       // are critical and we must not power down if such transactions
399                       // are pending. Hence, we signal the LCI/DAI idle state to the
400                       // power manager. This signal is flopped here as it has to
401                       // cross a clock boundary to the power manager.
402                       logic dai_prog_idle, lci_prog_idle, otp_idle_d, otp_idle_q;
403        1/1            assign otp_idle_d = lci_prog_idle & dai_prog_idle;
           Tests:       T1 T2 T3 
404        1/1            assign pwr_otp_o.otp_idle = otp_idle_q;
           Tests:       T1 T2 T3 
405                     
406                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_idle_regwen_regs
407        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
408        1/1                otp_idle_q <= 1'b0;
           Tests:       T1 T2 T3 
409                           // The regwen bit has to reset to 1 so that CSR accesses are enabled by default.
410        1/1                direct_access_regwen_q  <= 1'b1;
           Tests:       T1 T2 T3 
411                         end else begin
412        1/1                otp_idle_q <= otp_idle_d;
           Tests:       T1 T2 T3 
413        1/1                direct_access_regwen_q <= direct_access_regwen_d;
           Tests:       T1 T2 T3 
414                         end
415                       end
416                     
417                       //////////////////////////////////////
418                       // Ctrl/Status CSRs, Errors, Alerts //
419                       //////////////////////////////////////
420                     
421                       // Status and error reporting CSRs, error interrupt generation and alerts.
422                       otp_err_e [NumPart+1:0] part_error;
423                       logic [NumAgents-1:0] part_fsm_err;
424                       logic [NumPart+1:0] part_errors_reduced;
425                       logic otp_operation_done, otp_error;
426                       logic fatal_macro_error_d, fatal_macro_error_q;
427                       logic fatal_check_error_d, fatal_check_error_q;
428                       logic fatal_bus_integ_error_d, fatal_bus_integ_error_q;
429                       logic chk_pending, chk_timeout;
430                       logic lfsr_fsm_err, scrmbl_fsm_err;
431                       always_comb begin : p_errors_alerts
432                         // Note: since these are all fatal alert events, we latch them and keep on sending
433                         // alert events via the alert senders. These regs can only be cleared via a system reset.
434        1/1              fatal_macro_error_d = fatal_macro_error_q;
           Tests:       T1 T2 T3 
435        1/1              fatal_check_error_d = fatal_check_error_q;
           Tests:       T1 T2 T3 
436        1/1              fatal_bus_integ_error_d = fatal_bus_integ_error_q | (|intg_error);
           Tests:       T1 T2 T3 
437                         // These are the per-partition buffered escalation inputs
438        1/1              lc_escalate_en = lc_escalate_en_synced;
           Tests:       T1 T2 T3 
439                         // Need a single wire for gating assertions in arbitration and CDC primitives.
440        1/1              lc_escalate_en_any = 1'b0;
           Tests:       T1 T2 T3 
441                     
442                         // Aggregate all the macro alerts from the partitions
443        1/1              for (int k = 0; k < NumPart; k++) begin
           Tests:       T1 T2 T3 
444                           // Filter for critical error codes that should not occur in the field.
445        1/1                fatal_macro_error_d |= part_error[k] == MacroError;
           Tests:       T1 T2 T3 
446                           // While uncorrectable ECC errors are always reported, they do not trigger a fatal alert
447                           // event in some partitions like the VENDOR_TEST partition.
448        1/1                if (PartInfo[k].integrity) begin
           Tests:       T1 T2 T3 
449        1/1                  fatal_macro_error_d |= part_error[k] == MacroEccUncorrError;
           Tests:       T1 T2 T3 
450                           end
                        MISSING_ELSE
451                         end
452                         // Aggregate all the macro alerts from the DAI/LCI
453        1/1              for (int k = NumPart; k < NumPart+2; k++) begin
           Tests:       T1 T2 T3 
454                           // Filter for critical error codes that should not occur in the field.
455        1/1                fatal_macro_error_d |= part_error[k] inside {MacroError, MacroEccUncorrError};
           Tests:       T1 T2 T3 
456                         end
457                     
458                         // Aggregate all the remaining errors / alerts from the partitions and the DAI/LCI
459        1/1              for (int k = 0; k < NumPart+2; k++) begin
           Tests:       T1 T2 T3 
460                           // Set the error bit if the error status of the corresponding partition is nonzero.
461                           // Need to reverse the order here since the field enumeration in hw2reg.status is reversed.
462        1/1                part_errors_reduced[NumPart+1-k] = |part_error[k];
           Tests:       T1 T2 T3 
463                           // Filter for integrity and consistency check failures.
464        1/1                fatal_check_error_d |= part_error[k] inside {CheckFailError, FsmStateError};
           Tests:       T1 T2 T3 
465                     
466                           // If a fatal alert has been observed in any of the partitions/FSMs,
467                           // we locally trigger escalation within OTP, which moves all FSMs
468                           // to a terminal error state.
469        1/1                if (fatal_macro_error_q || fatal_check_error_q) begin
           Tests:       T1 T2 T3 
470        1/1                  lc_escalate_en[k] = lc_ctrl_pkg::On;
           Tests:       T3 T9 T44 
471                           end
                        MISSING_ELSE
472        1/1                if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k])) begin
           Tests:       T1 T2 T3 
473        1/1                  lc_escalate_en_any = 1'b1;
           Tests:       T3 T9 T44 
474                           end
                        MISSING_ELSE
475                         end
476                     
477                         // Errors from other non-partition FSMs.
478        1/1              fatal_check_error_d |= chk_timeout       |
           Tests:       T1 T2 T3 
479                                                lfsr_fsm_err      |
480                                                scrmbl_fsm_err    |
481                                                (|part_fsm_err);
482                       end
483                     
484                       // If we got an error, we trigger an interrupt.
485                       logic [$bits(part_errors_reduced)+4-1:0] interrupt_triggers_d, interrupt_triggers_q;
486                     
487                       // This makes sure that interrupts are not sticky.
488        1/1            assign interrupt_triggers_d = {
           Tests:       T1 T2 T3 
489                         part_errors_reduced,
490                         chk_timeout,
491                         lfsr_fsm_err,
492                         scrmbl_fsm_err,
493                         |part_fsm_err
494                       };
495                     
496        1/1            assign otp_error = |(interrupt_triggers_d & ~interrupt_triggers_q);
           Tests:       T1 T2 T3 
497                     
498                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_alert_regs
499        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
500        1/1                fatal_macro_error_q     <= '0;
           Tests:       T1 T2 T3 
501        1/1                fatal_check_error_q     <= '0;
           Tests:       T1 T2 T3 
502        1/1                fatal_bus_integ_error_q <= '0;
           Tests:       T1 T2 T3 
503        1/1                interrupt_triggers_q    <= '0;
           Tests:       T1 T2 T3 
504                         end else begin
505        1/1                fatal_macro_error_q     <= fatal_macro_error_d;
           Tests:       T1 T2 T3 
506        1/1                fatal_check_error_q     <= fatal_check_error_d;
           Tests:       T1 T2 T3 
507        1/1                fatal_bus_integ_error_q <= fatal_bus_integ_error_d;
           Tests:       T1 T2 T3 
508        1/1                interrupt_triggers_q    <= interrupt_triggers_d;
           Tests:       T1 T2 T3 
509                         end
510                       end
511                     
512                       // CSR assignments are done in one combo process so that we can use
513                       // the parameterized digest_assign task below without multiple driver issues.
514                       logic unused_part_digest;
515                       logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest;
516                       logic intr_state_otp_operation_done_d, intr_state_otp_operation_done_de;
517                       logic intr_state_otp_error_d, intr_state_otp_error_de;
518                       always_comb begin : p_csr_assign
519                         // Not all partition digests are consumed, and assigning them to an unused_* signal in the
520                         // function below does not seem to work for some linters.
521        1/1              unused_part_digest = ^part_digest;
           Tests:       T1 T2 T3 
522                         // Assign named CSRs (like digests).
523        1/1              hw2reg = named_reg_assign(part_digest);
           Tests:       T1 T2 T3 
524                         // DAI related CSRs
525        1/1              hw2reg.direct_access_rdata = dai_rdata;
           Tests:       T1 T2 T3 
526                         // ANDing this state with dai_idle write-protects all DAI regs during pending operations.
527        1/1              hw2reg.direct_access_regwen.d = direct_access_regwen_q & dai_idle;
           Tests:       T1 T2 T3 
528                         // Assign these to the status register.
529        1/1              hw2reg.status = {part_errors_reduced,
           Tests:       T1 T2 T3 
530                                          chk_timeout,
531                                          lfsr_fsm_err,
532                                          scrmbl_fsm_err,
533                                          part_fsm_err[KdiIdx],
534                                          fatal_bus_integ_error_q,
535                                          dai_idle,
536                                          chk_pending};
537                         // Error code registers.
538        1/1              hw2reg.err_code = part_error;
           Tests:       T1 T2 T3 
539                         // Interrupt signals
540        1/1              hw2reg.intr_state.otp_operation_done.de = intr_state_otp_operation_done_de;
           Tests:       T1 T2 T3 
541        1/1              hw2reg.intr_state.otp_operation_done.d  = intr_state_otp_operation_done_d;
           Tests:       T1 T2 T3 
542        1/1              hw2reg.intr_state.otp_error.de = intr_state_otp_error_de;
           Tests:       T1 T2 T3 
543        1/1              hw2reg.intr_state.otp_error.d  = intr_state_otp_error_d;
           Tests:       T1 T2 T3 
544                     end
545                     
546                     
547                       //////////////////////////////////
548                       // Interrupts and Alert Senders //
549                       //////////////////////////////////
550                     
551                       prim_intr_hw #(
552                         .Width(1)
553                       ) u_intr_operation_done (
554                         .clk_i,
555                         .rst_ni,
556                         .event_intr_i           ( otp_operation_done                      ),
557                         .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.otp_operation_done.q ),
558                         .reg2hw_intr_test_q_i   ( reg2hw.intr_test.otp_operation_done.q   ),
559                         .reg2hw_intr_test_qe_i  ( reg2hw.intr_test.otp_operation_done.qe  ),
560                         .reg2hw_intr_state_q_i  ( reg2hw.intr_state.otp_operation_done.q  ),
561                         .hw2reg_intr_state_de_o ( intr_state_otp_operation_done_de        ),
562                         .hw2reg_intr_state_d_o  ( intr_state_otp_operation_done_d         ),
563                         .intr_o                 ( intr_otp_operation_done_o               )
564                       );
565                     
566                       prim_intr_hw #(
567                         .Width(1)
568                       ) u_intr_error (
569                         .clk_i,
570                         .rst_ni,
571                         .event_intr_i           ( otp_error                      ),
572                         .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.otp_error.q ),
573                         .reg2hw_intr_test_q_i   ( reg2hw.intr_test.otp_error.q   ),
574                         .reg2hw_intr_test_qe_i  ( reg2hw.intr_test.otp_error.qe  ),
575                         .reg2hw_intr_state_q_i  ( reg2hw.intr_state.otp_error.q  ),
576                         .hw2reg_intr_state_de_o ( intr_state_otp_error_de        ),
577                         .hw2reg_intr_state_d_o  ( intr_state_otp_error_d         ),
578                         .intr_o                 ( intr_otp_error_o               )
579                       );
580                     
581                       logic [NumAlerts-1:0] alerts;
582                       logic [NumAlerts-1:0] alert_test;
583                       logic fatal_prim_otp_alert, recov_prim_otp_alert;
584                     
585        1/1            assign alerts = {
           Tests:       T1 T2 T3 
586                         recov_prim_otp_alert,
587                         fatal_prim_otp_alert,
588                         fatal_bus_integ_error_q,
589                         fatal_check_error_q,
590                         fatal_macro_error_q
591                       };
592                     
593        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
594                         reg2hw.alert_test.recov_prim_otp_alert.q &
595                         reg2hw.alert_test.recov_prim_otp_alert.qe,
596                         reg2hw.alert_test.fatal_prim_otp_alert.q &
597                         reg2hw.alert_test.fatal_prim_otp_alert.qe,
598                         reg2hw.alert_test.fatal_bus_integ_error.q &
599                         reg2hw.alert_test.fatal_bus_integ_error.qe,
600                         reg2hw.alert_test.fatal_check_error.q &
601                         reg2hw.alert_test.fatal_check_error.qe,
602                         reg2hw.alert_test.fatal_macro_error.q &
603                         reg2hw.alert_test.fatal_macro_error.qe
604                       };
605                     
606                       localparam logic [NumAlerts-1:0] AlertIsFatal = {
607                         1'b0, // recov_prim_otp_alert
608                         1'b1, // fatal_prim_otp_alert
609                         1'b1, // fatal_bus_integ_error_q
610                         1'b1, // fatal_check_error_q
611                         1'b1  // fatal_macro_error_q
612                       };
613                     
614                       for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx
615                         prim_alert_sender #(
616                           .AsyncOn(AlertAsyncOn[k]),
617                           .IsFatal(AlertIsFatal[k])
618                         ) u_prim_alert_sender (
619                           .clk_i,
620                           .rst_ni,
621                           .alert_test_i  ( alert_test[k] ),
622                           .alert_req_i   ( alerts[k]     ),
623                           .alert_ack_o   (               ),
624                           .alert_state_o (               ),
625                           .alert_rx_i    ( alert_rx_i[k] ),
626                           .alert_tx_o    ( alert_tx_o[k] )
627                         );
628                       end
629                     
630                       ////////////////////////////////
631                       // LFSR Timer and CSR mapping //
632                       ////////////////////////////////
633                     
634                       logic integ_chk_trig, cnsty_chk_trig;
635                       logic [NumPart-1:0] integ_chk_req, integ_chk_ack;
636                       logic [NumPart-1:0] cnsty_chk_req, cnsty_chk_ack;
637                       logic lfsr_edn_req, lfsr_edn_ack;
638                       logic [EdnDataWidth-1:0] edn_data;
639                     
640        1/1            assign integ_chk_trig   = reg2hw.check_trigger.integrity.q &
           Tests:       T1 T2 T3 
641                                                 reg2hw.check_trigger.integrity.qe;
642        1/1            assign cnsty_chk_trig   = reg2hw.check_trigger.consistency.q &
           Tests:       T1 T2 T3 
643                                                 reg2hw.check_trigger.consistency.qe;
644                     
645                       // SEC_CM: PART.DATA_REG.BKGN_CHK
646                       otp_ctrl_lfsr_timer #(
647                         .RndCnstLfsrSeed(RndCnstLfsrSeed),
648                         .RndCnstLfsrPerm(RndCnstLfsrPerm)
649                       ) u_otp_ctrl_lfsr_timer (
650                         .clk_i,
651                         .rst_ni,
652                         .edn_req_o          ( lfsr_edn_req              ),
653                         .edn_ack_i          ( lfsr_edn_ack              ),
654                         .edn_data_i         ( edn_data                  ),
655                         // We can enable the timer once OTP has initialized.
656                         // Note that this is only the initial release that gets
657                         // the timer FSM into an operational state.
658                         // Whether or not the timers / background checks are
659                         // activated depends on the CSR configuration (by default
660                         // they are switched off).
661                         .timer_en_i         ( pwr_otp_o.otp_done        ),
662                         // This idle signal is the same that is output to the power
663                         // manager, and indicates whether there is an ongoing OTP programming
664                         // operation. It is used to pause the consistency check timeout
665                         // counter in order to prevent spurious timeouts (OTP programming
666                         // operations are very slow compared to readout operations and can
667                         // hence interfere with the timeout mechanism).
668                         .otp_prog_busy_i    ( ~otp_idle_d               ),
669                         .integ_chk_trig_i   ( integ_chk_trig            ),
670                         .cnsty_chk_trig_i   ( cnsty_chk_trig            ),
671                         .chk_pending_o      ( chk_pending               ),
672                         .timeout_i          ( reg2hw.check_timeout.q    ),
673                         .integ_period_msk_i ( reg2hw.integrity_check_period.q   ),
674                         .cnsty_period_msk_i ( reg2hw.consistency_check_period.q ),
675                         .integ_chk_req_o    ( integ_chk_req             ),
676                         .cnsty_chk_req_o    ( cnsty_chk_req             ),
677                         .integ_chk_ack_i    ( integ_chk_ack             ),
678                         .cnsty_chk_ack_i    ( cnsty_chk_ack             ),
679                         .escalate_en_i      ( lc_escalate_en[NumAgents] ),
680                         .chk_timeout_o      ( chk_timeout               ),
681                         .fsm_err_o          ( lfsr_fsm_err              )
682                       );
683                     
684                       ///////////////////////////////////////
685                       // EDN Arbitration, Request and Sync //
686                       ///////////////////////////////////////
687                     
688                       // Both the key derivation and LFSR reseeding are low bandwidth,
689                       // hence they can share the same EDN interface.
690                       logic edn_req, edn_ack;
691                       logic key_edn_req, key_edn_ack;
692                       prim_arbiter_tree #(
693                         .N(2),
694                         .EnDataPort(0)
695                       ) u_edn_arb (
696                         .clk_i,
697                         .rst_ni,
698                         .req_chk_i ( ~lc_escalate_en_any         ),
699                         .req_i     ( {lfsr_edn_req, key_edn_req} ),
700                         .data_i    ( '{default: '0}              ),
701                         .gnt_o     ( {lfsr_edn_ack, key_edn_ack} ),
702                         .idx_o     (                             ), // unused
703                         .valid_o   ( edn_req                     ),
704                         .data_o    (                             ), // unused
705                         .ready_i   ( edn_ack                     )
706                       );
707                     
708                       // This synchronizes the data coming from EDN and stacks the
709                       // 32bit EDN words to achieve an internal entropy width of 64bit.
710                       prim_edn_req #(
711                         .OutWidth(EdnDataWidth)
712                       ) u_prim_edn_req (
713                         .clk_i,
714                         .rst_ni,
715                         .req_chk_i ( ~lc_escalate_en_any ),
716                         .req_i     ( edn_req             ),
717                         .ack_o     ( edn_ack             ),
718                         .data_o    ( edn_data            ),
719                         .fips_o    (                     ), // unused
720                         .err_o     (                     ), // unused
721                         .clk_edn_i,
722                         .rst_edn_ni,
723                         .edn_o,
724                         .edn_i
725                       );
726                     
727                       ///////////////////////////////
728                       // OTP Macro and Arbitration //
729                       ///////////////////////////////
730                     
731                       typedef struct packed {
732                         prim_otp_pkg::cmd_e          cmd;
733                         logic [OtpSizeWidth-1:0]     size; // Number of native words to write.
734                         logic [OtpIfWidth-1:0]       wdata;
735                         logic [OtpAddrWidth-1:0]     addr; // Halfword address.
736                       } otp_bundle_t;
737                     
738                       logic [NumAgents-1:0]        part_otp_arb_req, part_otp_arb_gnt;
739                       otp_bundle_t                 part_otp_arb_bundle [NumAgents];
740                       logic                        otp_arb_valid, otp_arb_ready;
741                       logic                        otp_prim_valid, otp_prim_ready;
742                       logic                        otp_rsp_fifo_valid, otp_rsp_fifo_ready;
743                       logic [vbits(NumAgents)-1:0] otp_arb_idx;
744                       otp_bundle_t                 otp_arb_bundle;
745                     
746                       // The OTP interface is arbitrated on a per-cycle basis, meaning that back-to-back
747                       // transactions can be completely independent.
748                       prim_arbiter_tree #(
749                         .N(NumAgents),
750                         .DW($bits(otp_bundle_t))
751                       ) u_otp_arb (
752                         .clk_i,
753                         .rst_ni,
754                         .req_chk_i ( ~lc_escalate_en_any ),
755                         .req_i     ( part_otp_arb_req    ),
756                         .data_i    ( part_otp_arb_bundle ),
757                         .gnt_o     ( part_otp_arb_gnt    ),
758                         .idx_o     ( otp_arb_idx         ),
759                         .valid_o   ( otp_arb_valid       ),
760                         .data_o    ( otp_arb_bundle      ),
761                         .ready_i   ( otp_arb_ready       )
762                       );
763                     
764                       // Don't issue more transactions than what the rsp_fifo can keep track of.
765        1/1            assign otp_arb_ready      = otp_prim_ready & otp_rsp_fifo_ready;
           Tests:       T1 T2 T3 
766        1/1            assign otp_prim_valid     = otp_arb_valid & otp_rsp_fifo_ready;
           Tests:       T1 T2 T3 
767        1/1            assign otp_rsp_fifo_valid = otp_prim_ready & otp_prim_valid;
           Tests:       T1 T2 T3 
768                     
769                       prim_otp_pkg::err_e          part_otp_err;
770                       logic [OtpIfWidth-1:0]       part_otp_rdata;
771                       logic                        otp_rvalid;
772                       tlul_pkg::tl_h2d_t           prim_tl_h2d_gated;
773                       tlul_pkg::tl_d2h_t           prim_tl_d2h_gated;
774                     
775                       // Life cycle qualification of TL-UL test interface.
776                       // SEC_CM: TEST.BUS.LC_GATED
777                       // SEC_CM: TEST_TL_LC_GATE.FSM.SPARSE
778                       tlul_lc_gate #(
779                         .NumGatesPerDirection(2)
780                       ) u_tlul_lc_gate (
781                         .clk_i,
782                         .rst_ni,
783                         .tl_h2d_i(prim_tl_i),
784                         .tl_d2h_o(prim_tl_o),
785                         .tl_h2d_o(prim_tl_h2d_gated),
786                         .tl_d2h_i(prim_tl_d2h_gated),
787                         .lc_en_i (lc_dft_en[0]),
788                         .flush_req_i('0),
789                         .flush_ack_o(),
790                         .resp_pending_o(),
791                         .err_o   (intg_error[2])
792                       );
793                     
794                       // Test-related GPIOs.
795                       // SEC_CM: TEST.BUS.LC_GATED
796                       logic [OtpTestVectWidth-1:0] otp_test_vect;
797        1/1            assign cio_test_o    = (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[1])) ?
           Tests:       T1 T2 T3 
798                                              otp_test_vect            : '0;
799        1/1            assign cio_test_en_o = (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[2])) ?
           Tests:       T1 T2 T3 
800                                              {OtpTestVectWidth{1'b1}} : '0;
801                     
802                       // SEC_CM: MACRO.MEM.CM, MACRO.MEM.INTEGRITY
803                       prim_otp #(
804                         .Width            ( OtpWidth            ),
805                         .Depth            ( OtpDepth            ),
806                         .SizeWidth        ( OtpSizeWidth        ),
807                         .PwrSeqWidth      ( OtpPwrSeqWidth      ),
808                         .TestCtrlWidth    ( OtpTestCtrlWidth    ),
809                         .TestStatusWidth  ( OtpTestStatusWidth  ),
810                         .TestVectWidth    ( OtpTestVectWidth    ),
811                         .MemInitFile      ( MemInitFile         ),
812                         .VendorTestOffset ( VendorTestOffset    ),
813                         .VendorTestSize   ( VendorTestSize      )
814                       ) u_otp (
815                         .clk_i,
816                         .rst_ni,
817                         // Observability controls to/from AST
818                         .obs_ctrl_i,
819                         .otp_obs_o,
820                         // Power sequencing signals to/from AST
821                         .pwr_seq_o        ( otp_ast_pwr_seq_o.pwr_seq     ),
822                         .pwr_seq_h_i      ( otp_ast_pwr_seq_h_i.pwr_seq_h ),
823                         .ext_voltage_io   ( otp_ext_voltage_h_io          ),
824                         // Test interface
825                         .test_ctrl_i      ( lc_otp_vendor_test_i.ctrl     ),
826                         .test_status_o    ( lc_otp_vendor_test_o.status   ),
827                         .test_vect_o      ( otp_test_vect                 ),
828                         .test_tl_i        ( prim_tl_h2d_gated             ),
829                         .test_tl_o        ( prim_tl_d2h_gated             ),
830                         // Other DFT signals
831                         .scan_en_i,
832                         .scan_rst_ni,
833                         .scanmode_i,
834                         // Alerts
835                         .fatal_alert_o    ( fatal_prim_otp_alert ),
836                         .recov_alert_o    ( recov_prim_otp_alert ),
837                         // Read / Write command interface
838                         .ready_o          ( otp_prim_ready       ),
839                         .valid_i          ( otp_prim_valid       ),
840                         .cmd_i            ( otp_arb_bundle.cmd   ),
841                         .size_i           ( otp_arb_bundle.size  ),
842                         .addr_i           ( otp_arb_bundle.addr  ),
843                         .wdata_i          ( otp_arb_bundle.wdata ),
844                         // Read data out
845                         .valid_o          ( otp_rvalid           ),
846                         .rdata_o          ( part_otp_rdata       ),
847                         .err_o            ( part_otp_err         )
848                       );
849                     
850                       logic otp_fifo_valid;
851                       logic [vbits(NumAgents)-1:0] otp_part_idx;
852                       logic [NumAgents-1:0] part_otp_rvalid;
853                     
854                       // We can have up to two OTP commands in flight, hence we size this to be 2 deep.
855                       // The partitions can unconditionally sink requested data.
856                       prim_fifo_sync #(
857                         .Width(vbits(NumAgents)),
858                         .Depth(2)
859                       ) u_otp_rsp_fifo (
860                         .clk_i,
861                         .rst_ni,
862                         .clr_i    ( 1'b0               ),
863                         .wvalid_i ( otp_rsp_fifo_valid ),
864                         .wready_o ( otp_rsp_fifo_ready ),
865                         .wdata_i  ( otp_arb_idx        ),
866                         .rvalid_o ( otp_fifo_valid     ),
867                         .rready_i ( otp_rvalid         ),
868                         .rdata_o  ( otp_part_idx       ),
869                         .depth_o  (                    ),
870                         .full_o   (                    ),
871                         .err_o    (                    )
872                       );
873                     
874                       // Steer response back to the partition where this request originated.
875                       always_comb begin : p_rvalid
876        1/1              part_otp_rvalid = '0;
           Tests:       T1 T2 T3 
877        1/1              part_otp_rvalid[otp_part_idx] = otp_rvalid & otp_fifo_valid;
           Tests:       T1 T2 T3 
878                       end
879                     
880                       // Note that this must be true by construction.
881                       `ASSERT(OtpRespFifoUnderflow_A, otp_rvalid |-> otp_fifo_valid)
882                     
883                       /////////////////////////////////////////
884                       // Scrambling Datapath and Arbitration //
885                       /////////////////////////////////////////
886                     
887                       // Note: as opposed to the OTP arbitration above, we do not perform cycle-wise arbitration, but
888                       // transaction-wise arbitration. This is implemented using a RR arbiter that acts as a mutex.
889                       // I.e., each agent (e.g. the DAI or a partition) can request a lock on the mutex. Once granted,
890                       // the partition can keep the lock as long as needed for the transaction to complete. The
891                       // partition must yield its lock by deasserting the request signal for the arbiter to proceed.
892                       // Since this scheme does not have built-in preemtion, it must be ensured that the agents
893                       // eventually release their locks for this to be fair.
894                       //
895                       // See also https://docs.opentitan.org/hw/ip/otp_ctrl/doc/index.html#block-diagram for details.
896                       typedef struct packed {
897                         otp_scrmbl_cmd_e             cmd;
898                         digest_mode_e                mode;
899                         logic [ConstSelWidth-1:0]    sel;
900                         logic [ScrmblBlockWidth-1:0] data;
901                         logic                        valid;
902                       } scrmbl_bundle_t;
903                     
904                       logic [NumAgents-1:0]        part_scrmbl_mtx_req, part_scrmbl_mtx_gnt;
905                       scrmbl_bundle_t              part_scrmbl_req_bundle [NumAgents];
906                       scrmbl_bundle_t              scrmbl_req_bundle;
907                       logic [vbits(NumAgents)-1:0] scrmbl_mtx_idx;
908                       logic                        scrmbl_mtx_valid;
909                     
910                       // Note that arbiter decisions do not change when backpressured.
911                       // Hence, the idx_o signal is guaranteed to remain stable until ack'ed.
912                       prim_arbiter_tree #(
913                         .N(NumAgents),
914                         .DW($bits(scrmbl_bundle_t))
915                       ) u_scrmbl_mtx (
916                         .clk_i,
917                         .rst_ni,
918                         .req_chk_i ( 1'b0                   ), // REQ is allowed to go low again without ACK even
919                                                                // during normal operation.
920                         .req_i     ( part_scrmbl_mtx_req    ),
921                         .data_i    ( part_scrmbl_req_bundle ),
922                         .gnt_o     (                        ),
923                         .idx_o     ( scrmbl_mtx_idx         ),
924                         .valid_o   ( scrmbl_mtx_valid       ),
925                         .data_o    ( scrmbl_req_bundle      ),
926                         .ready_i   ( 1'b0                   )
927                       );
928                     
929                       // Since the ready_i signal of the arbiter is statically set to 1'b0 above, we are always in a
930                       // "backpressure" situation, where the RR arbiter will automatically advance the internal RR state
931                       // to give the current winner max priority in subsequent cycles in order to keep the decision
932                       // stable. Rearbitration occurs once the winning agent deasserts its request.
933                       always_comb begin : p_mutex
934        1/1              part_scrmbl_mtx_gnt = '0;
           Tests:       T1 T2 T3 
935        1/1              part_scrmbl_mtx_gnt[scrmbl_mtx_idx] = scrmbl_mtx_valid;
           Tests:       T1 T2 T3 
936                       end
937                     
938                       logic [ScrmblBlockWidth-1:0] part_scrmbl_rsp_data;
939                       logic scrmbl_arb_req_ready, scrmbl_arb_rsp_valid;
940                       logic [NumAgents-1:0] part_scrmbl_req_ready, part_scrmbl_rsp_valid;
941                     
942                       // SEC_CM: SECRET.MEM.SCRAMBLE
943                       // SEC_CM: PART.MEM.DIGEST
944                       otp_ctrl_scrmbl u_otp_ctrl_scrmbl (
945                         .clk_i,
946                         .rst_ni,
947                         .cmd_i         ( scrmbl_req_bundle.cmd       ),
948                         .mode_i        ( scrmbl_req_bundle.mode      ),
949                         .sel_i         ( scrmbl_req_bundle.sel       ),
950                         .data_i        ( scrmbl_req_bundle.data      ),
951                         .valid_i       ( scrmbl_req_bundle.valid     ),
952                         .ready_o       ( scrmbl_arb_req_ready        ),
953                         .data_o        ( part_scrmbl_rsp_data        ),
954                         .valid_o       ( scrmbl_arb_rsp_valid        ),
955                         .escalate_en_i ( lc_escalate_en[NumAgents+1] ),
956                         .fsm_err_o     ( scrmbl_fsm_err              )
957                       );
958                     
959                       // steer back responses
960                       always_comb begin : p_scmrbl_resp
961        1/1              part_scrmbl_req_ready = '0;
           Tests:       T1 T2 T3 
962        1/1              part_scrmbl_rsp_valid = '0;
           Tests:       T1 T2 T3 
963        1/1              part_scrmbl_req_ready[scrmbl_mtx_idx] = scrmbl_arb_req_ready;
           Tests:       T1 T2 T3 
964        1/1              part_scrmbl_rsp_valid[scrmbl_mtx_idx] = scrmbl_arb_rsp_valid;
           Tests:       T1 T2 T3 
965                       end
966                     
967                       /////////////////////////////
968                       // Direct Access Interface //
969                       /////////////////////////////
970                     
971                       logic                           part_init_req;
972                       logic [NumPart-1:0]             part_init_done;
973                       part_access_t [NumPart-1:0]     part_access_dai;
974                     
975                       // The init request comes from the power manager, which lives in the AON clock domain.
976                       logic pwr_otp_req_synced;
977                       prim_flop_2sync #(
978                         .Width(1)
979                       ) u_otp_init_sync (
980                         .clk_i,
981                         .rst_ni,
982                         .d_i ( pwr_otp_i.otp_init ),
983                         .q_o ( pwr_otp_req_synced )
984                       );
985                     
986                       // Register this signal as it has to cross a clock boundary.
987                       logic pwr_otp_rsp_d, pwr_otp_rsp_q;
988        1/1            assign pwr_otp_o.otp_done = pwr_otp_rsp_q;
           Tests:       T1 T2 T3 
989                     
990                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_init_reg
991        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
992        1/1                pwr_otp_rsp_q <= 1'b0;
           Tests:       T1 T2 T3 
993                         end else begin
994        1/1                pwr_otp_rsp_q <= pwr_otp_rsp_d;
           Tests:       T1 T2 T3 
995                         end
996                       end
997                     
998                       otp_ctrl_dai u_otp_ctrl_dai (
999                         .clk_i,
1000                        .rst_ni,
1001                        .init_req_i       ( pwr_otp_req_synced                    ),
1002                        .init_done_o      ( pwr_otp_rsp_d                         ),
1003                        .part_init_req_o  ( part_init_req                         ),
1004                        .part_init_done_i ( part_init_done                        ),
1005                        .escalate_en_i    ( lc_escalate_en[DaiIdx]                ),
1006                        .error_o          ( part_error[DaiIdx]                    ),
1007                        .fsm_err_o        ( part_fsm_err[DaiIdx]                  ),
1008                        .part_access_i    ( part_access_dai                       ),
1009                        .dai_addr_i       ( dai_addr                              ),
1010                        .dai_cmd_i        ( dai_cmd                               ),
1011                        .dai_req_i        ( dai_req                               ),
1012                        .dai_wdata_i      ( dai_wdata                             ),
1013                        .dai_idle_o       ( dai_idle                              ),
1014                        .dai_prog_idle_o  ( dai_prog_idle                         ),
1015                        .dai_cmd_done_o   ( otp_operation_done                    ),
1016                        .dai_rdata_o      ( dai_rdata                             ),
1017                        .otp_req_o        ( part_otp_arb_req[DaiIdx]              ),
1018                        .otp_cmd_o        ( part_otp_arb_bundle[DaiIdx].cmd       ),
1019                        .otp_size_o       ( part_otp_arb_bundle[DaiIdx].size      ),
1020                        .otp_wdata_o      ( part_otp_arb_bundle[DaiIdx].wdata     ),
1021                        .otp_addr_o       ( part_otp_arb_bundle[DaiIdx].addr      ),
1022                        .otp_gnt_i        ( part_otp_arb_gnt[DaiIdx]              ),
1023                        .otp_rvalid_i     ( part_otp_rvalid[DaiIdx]               ),
1024                        .otp_rdata_i      ( part_otp_rdata                        ),
1025                        .otp_err_i        ( part_otp_err                          ),
1026                        .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[DaiIdx]           ),
1027                        .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[DaiIdx]           ),
1028                        .scrmbl_cmd_o     ( part_scrmbl_req_bundle[DaiIdx].cmd    ),
1029                        .scrmbl_mode_o    ( part_scrmbl_req_bundle[DaiIdx].mode   ),
1030                        .scrmbl_sel_o     ( part_scrmbl_req_bundle[DaiIdx].sel    ),
1031                        .scrmbl_data_o    ( part_scrmbl_req_bundle[DaiIdx].data   ),
1032                        .scrmbl_valid_o   ( part_scrmbl_req_bundle[DaiIdx].valid  ),
1033                        .scrmbl_ready_i   ( part_scrmbl_req_ready[DaiIdx]         ),
1034                        .scrmbl_valid_i   ( part_scrmbl_rsp_valid[DaiIdx]         ),
1035                        .scrmbl_data_i    ( part_scrmbl_rsp_data                  )
1036                      );
1037                    
1038                      ////////////////////////////////////
1039                      // Lifecycle Transition Interface //
1040                      ////////////////////////////////////
1041                    
1042                      logic [PartInfo[LifeCycleIdx].size-1:0][7:0] lc_otp_program_data;
1043       1/1            assign lc_otp_program_data[LcStateOffset-LifeCycleOffset +: LcStateSize] =
           Tests:       T2 T4 T9 
1044                          lc_otp_program_i.state;
1045       1/1            assign lc_otp_program_data[LcTransitionCntOffset-LifeCycleOffset +: LcTransitionCntSize] =
           Tests:       T2 T4 T9 
1046                          lc_otp_program_i.count;
1047                    
1048                      otp_ctrl_lci #(
1049                        .Info(PartInfo[LifeCycleIdx])
1050                      ) u_otp_ctrl_lci (
1051                        .clk_i,
1052                        .rst_ni,
1053                        .lci_en_i         ( pwr_otp_o.otp_done                ),
1054                        .escalate_en_i    ( lc_escalate_en[LciIdx]            ),
1055                        .error_o          ( part_error[LciIdx]                ),
1056                        .fsm_err_o        ( part_fsm_err[LciIdx]              ),
1057                        .lci_prog_idle_o  ( lci_prog_idle                     ),
1058                        .lc_req_i         ( lc_otp_program_i.req              ),
1059                        .lc_data_i        ( lc_otp_program_data               ),
1060                        .lc_ack_o         ( lc_otp_program_o.ack              ),
1061                        .lc_err_o         ( lc_otp_program_o.err              ),
1062                        .otp_req_o        ( part_otp_arb_req[LciIdx]          ),
1063                        .otp_cmd_o        ( part_otp_arb_bundle[LciIdx].cmd   ),
1064                        .otp_size_o       ( part_otp_arb_bundle[LciIdx].size  ),
1065                        .otp_wdata_o      ( part_otp_arb_bundle[LciIdx].wdata ),
1066                        .otp_addr_o       ( part_otp_arb_bundle[LciIdx].addr  ),
1067                        .otp_gnt_i        ( part_otp_arb_gnt[LciIdx]          ),
1068                        .otp_rvalid_i     ( part_otp_rvalid[LciIdx]           ),
1069                        .otp_rdata_i      ( part_otp_rdata                    ),
1070                        .otp_err_i        ( part_otp_err                      )
1071                      );
1072                    
1073                      // Tie off unused connections.
1074                      assign part_scrmbl_mtx_req[LciIdx]    = '0;
1075                      assign part_scrmbl_req_bundle[LciIdx] = '0;
1076                    
1077                      // This stops lint from complaining about unused signals.
1078                      logic unused_lci_scrmbl_sigs;
1079       0/1     ==>    assign unused_lci_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[LciIdx],
1080                                                        part_scrmbl_req_ready[LciIdx],
1081                                                        part_scrmbl_rsp_valid[LciIdx]};
1082                    
1083                      ////////////////////////////////////
1084                      // Key Derivation Interface (KDI) //
1085                      ////////////////////////////////////
1086                    
1087                      logic scrmbl_key_seed_valid;
1088                      logic [SramKeySeedWidth-1:0] sram_data_key_seed;
1089                      logic [FlashKeySeedWidth-1:0] flash_data_key_seed, flash_addr_key_seed;
1090                    
1091                      otp_ctrl_kdi #(
1092                        .RndCnstScrmblKeyInit(RndCnstScrmblKeyInit)
1093                      ) u_otp_ctrl_kdi (
1094                        .clk_i,
1095                        .rst_ni,
1096                        .kdi_en_i                ( pwr_otp_o.otp_done      ),
1097                        .escalate_en_i           ( lc_escalate_en[KdiIdx]  ),
1098                        .fsm_err_o               ( part_fsm_err[KdiIdx]    ),
1099                        .scrmbl_key_seed_valid_i ( scrmbl_key_seed_valid   ),
1100                        .flash_data_key_seed_i   ( flash_data_key_seed     ),
1101                        .flash_addr_key_seed_i   ( flash_addr_key_seed     ),
1102                        .sram_data_key_seed_i    ( sram_data_key_seed      ),
1103                        .edn_req_o               ( key_edn_req             ),
1104                        .edn_ack_i               ( key_edn_ack             ),
1105                        .edn_data_i              ( edn_data                ),
1106                        .flash_otp_key_i,
1107                        .flash_otp_key_o,
1108                        .sram_otp_key_i,
1109                        .sram_otp_key_o,
1110                        .otbn_otp_key_i,
1111                        .otbn_otp_key_o,
1112                        .scrmbl_mtx_req_o        ( part_scrmbl_mtx_req[KdiIdx]          ),
1113                        .scrmbl_mtx_gnt_i        ( part_scrmbl_mtx_gnt[KdiIdx]          ),
1114                        .scrmbl_cmd_o            ( part_scrmbl_req_bundle[KdiIdx].cmd   ),
1115                        .scrmbl_mode_o           ( part_scrmbl_req_bundle[KdiIdx].mode  ),
1116                        .scrmbl_sel_o            ( part_scrmbl_req_bundle[KdiIdx].sel   ),
1117                        .scrmbl_data_o           ( part_scrmbl_req_bundle[KdiIdx].data  ),
1118                        .scrmbl_valid_o          ( part_scrmbl_req_bundle[KdiIdx].valid ),
1119                        .scrmbl_ready_i          ( part_scrmbl_req_ready[KdiIdx]        ),
1120                        .scrmbl_valid_i          ( part_scrmbl_rsp_valid[KdiIdx]        ),
1121                        .scrmbl_data_i           ( part_scrmbl_rsp_data                 )
1122                      );
1123                    
1124                      // Tie off OTP bus access, since this is not needed.
1125                      assign part_otp_arb_req[KdiIdx] = 1'b0;
1126                      assign part_otp_arb_bundle[KdiIdx] = '0;
1127                    
1128                      // This stops lint from complaining about unused signals.
1129                      logic unused_kdi_otp_sigs;
1130       0/1     ==>    assign unused_kdi_otp_sigs = ^{part_otp_arb_gnt[KdiIdx],
1131                                                     part_otp_rvalid[KdiIdx]};
1132                    
1133                      /////////////////////////
1134                      // Partition Instances //
1135                      /////////////////////////
1136                    
1137                      logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data;
1138                    
1139                      for (genvar k = 0; k < NumPart; k ++) begin : gen_partitions
1140                        ////////////////////////////////////////////////////////////////////////////////////////////////
1141                        if (PartInfo[k].variant == Unbuffered) begin : gen_unbuffered
1142                          otp_ctrl_part_unbuf #(
1143                            .Info(PartInfo[k])
1144                          ) u_part_unbuf (
1145                            .clk_i,
1146                            .rst_ni,
1147                            .init_req_i    ( part_init_req                ),
1148                            .init_done_o   ( part_init_done[k]            ),
1149                            .escalate_en_i ( lc_escalate_en[k]            ),
1150                            .error_o       ( part_error[k]                ),
1151                            .fsm_err_o     ( part_fsm_err[k]              ),
1152                            .access_i      ( part_access[k]               ),
1153                            .access_o      ( part_access_dai[k]           ),
1154                            .digest_o      ( part_digest[k]               ),
1155                            .tlul_req_i    ( part_tlul_req[k]             ),
1156                            .tlul_gnt_o    ( part_tlul_gnt[k]             ),
1157                            .tlul_addr_i   ( part_tlul_addr               ),
1158                            .tlul_rerror_o ( part_tlul_rerror[k]          ),
1159                            .tlul_rvalid_o ( part_tlul_rvalid[k]          ),
1160                            .tlul_rdata_o  ( part_tlul_rdata[k]           ),
1161                            .otp_req_o     ( part_otp_arb_req[k]          ),
1162                            .otp_cmd_o     ( part_otp_arb_bundle[k].cmd   ),
1163                            .otp_size_o    ( part_otp_arb_bundle[k].size  ),
1164                            .otp_wdata_o   ( part_otp_arb_bundle[k].wdata ),
1165                            .otp_addr_o    ( part_otp_arb_bundle[k].addr  ),
1166                            .otp_gnt_i     ( part_otp_arb_gnt[k]          ),
1167                            .otp_rvalid_i  ( part_otp_rvalid[k]           ),
1168                            .otp_rdata_i   ( part_otp_rdata               ),
1169                            .otp_err_i     ( part_otp_err                 )
1170                          );
1171                    
1172                          // Tie off unused connections.
1173                          assign part_scrmbl_mtx_req[k]    = '0;
1174                          assign part_scrmbl_req_bundle[k] = '0;
1175                          // These checks do not exist in this partition type,
1176                          // so we always acknowledge the request.
1177                          assign integ_chk_ack[k]          = 1'b1;
1178                          assign cnsty_chk_ack[k]          = 1'b1;
1179                    
1180                          // No buffered data to expose.
1181                          assign part_buf_data[PartInfo[k].offset +: PartInfo[k].size] = '0;
1182                    
1183                          // This stops lint from complaining about unused signals.
1184                          logic unused_part_scrmbl_sigs;
1185       5/5                assign unused_part_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[k],
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
1186                                                             part_scrmbl_req_ready[k],
1187                                                             part_scrmbl_rsp_valid[k],
1188                                                             integ_chk_req[k],
1189                                                             cnsty_chk_req[k]};
1190                    
1191                          // Alert assertion for sparse FSM.
1192                          `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartUnbufFsmCheck_A,
1193                              u_part_unbuf.u_state_regs, alert_tx_o[1])
1194                        ////////////////////////////////////////////////////////////////////////////////////////////////
1195                        end else if (PartInfo[k].variant == Buffered) begin : gen_buffered
1196                          otp_ctrl_part_buf #(
1197                            .Info(PartInfo[k]),
1198                            .DataDefault(PartInvDefault[PartInfo[k].offset*8 +: PartInfo[k].size*8])
1199                          ) u_part_buf (
1200                            .clk_i,
1201                            .rst_ni,
1202                            .init_req_i        ( part_init_req                   ),
1203                            .init_done_o       ( part_init_done[k]               ),
1204                            .integ_chk_req_i   ( integ_chk_req[k]                ),
1205                            .integ_chk_ack_o   ( integ_chk_ack[k]                ),
1206                            .cnsty_chk_req_i   ( cnsty_chk_req[k]                ),
1207                            .cnsty_chk_ack_o   ( cnsty_chk_ack[k]                ),
1208                            .escalate_en_i     ( lc_escalate_en[k]               ),
1209                            // Only supported by life cycle partition (see further below).
1210                            .check_byp_en_i    ( lc_ctrl_pkg::Off                ),
1211                            .error_o           ( part_error[k]                   ),
1212                            .fsm_err_o         ( part_fsm_err[k]                 ),
1213                            .access_i          ( part_access[k]                  ),
1214                            .access_o          ( part_access_dai[k]              ),
1215                            .digest_o          ( part_digest[k]                  ),
1216                            .data_o            ( part_buf_data[PartInfo[k].offset +: PartInfo[k].size] ),
1217                            .otp_req_o         ( part_otp_arb_req[k]             ),
1218                            .otp_cmd_o         ( part_otp_arb_bundle[k].cmd      ),
1219                            .otp_size_o        ( part_otp_arb_bundle[k].size     ),
1220                            .otp_wdata_o       ( part_otp_arb_bundle[k].wdata    ),
1221                            .otp_addr_o        ( part_otp_arb_bundle[k].addr     ),
1222                            .otp_gnt_i         ( part_otp_arb_gnt[k]             ),
1223                            .otp_rvalid_i      ( part_otp_rvalid[k]              ),
1224                            .otp_rdata_i       ( part_otp_rdata                  ),
1225                            .otp_err_i         ( part_otp_err                    ),
1226                            .scrmbl_mtx_req_o  ( part_scrmbl_mtx_req[k]          ),
1227                            .scrmbl_mtx_gnt_i  ( part_scrmbl_mtx_gnt[k]          ),
1228                            .scrmbl_cmd_o      ( part_scrmbl_req_bundle[k].cmd   ),
1229                            .scrmbl_mode_o     ( part_scrmbl_req_bundle[k].mode  ),
1230                            .scrmbl_sel_o      ( part_scrmbl_req_bundle[k].sel   ),
1231                            .scrmbl_data_o     ( part_scrmbl_req_bundle[k].data  ),
1232                            .scrmbl_valid_o    ( part_scrmbl_req_bundle[k].valid ),
1233                            .scrmbl_ready_i    ( part_scrmbl_req_ready[k]        ),
1234                            .scrmbl_valid_i    ( part_scrmbl_rsp_valid[k]        ),
1235                            .scrmbl_data_i     ( part_scrmbl_rsp_data            )
1236                          );
1237                    
1238                          // Buffered partitions are not accessible via the TL-UL window.
1239                          logic unused_part_tlul_sigs;
1240       0/5     ==>        assign unused_part_tlul_sigs = ^part_tlul_req[k];
1241                          assign part_tlul_gnt[k]    = 1'b0;
1242                          assign part_tlul_rerror[k] = '0;
1243                          assign part_tlul_rvalid[k] = 1'b0;
1244                          assign part_tlul_rdata[k]  = '0;
1245                    
1246                          // Alert assertion for sparse FSM.
1247                          `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartBufFsmCheck_A,
1248                              u_part_buf.u_state_regs, alert_tx_o[1])
1249                          `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntPartBufCheck_A,
1250                              u_part_buf.u_prim_count, alert_tx_o[1])
1251                        ////////////////////////////////////////////////////////////////////////////////////////////////
1252                        end else if (PartInfo[k].variant == LifeCycle) begin : gen_lifecycle
1253                          otp_ctrl_part_buf #(
1254                            .Info(PartInfo[k]),
1255                            .DataDefault(PartInvDefault[PartInfo[k].offset*8 +: PartInfo[k].size*8])
1256                          ) u_part_buf (
1257                            .clk_i,
1258                            .rst_ni,
1259                            .init_req_i        ( part_init_req                   ),
1260                            .init_done_o       ( part_init_done[k]               ),
1261                            .integ_chk_req_i   ( integ_chk_req[k]                ),
1262                            .integ_chk_ack_o   ( integ_chk_ack[k]                ),
1263                            .cnsty_chk_req_i   ( cnsty_chk_req[k]                ),
1264                            .cnsty_chk_ack_o   ( cnsty_chk_ack[k]                ),
1265                            .escalate_en_i     ( lc_escalate_en[k]               ),
1266                            // This is only supported by the life cycle partition. We need to prevent this partition
1267                            // from escalating once the life cycle state in memory is being updated (and hence not
1268                            // consistent with the values in the buffer regs anymore).
1269                            .check_byp_en_i    ( lc_check_byp_en                 ),
1270                            .error_o           ( part_error[k]                   ),
1271                            .fsm_err_o         ( part_fsm_err[k]                 ),
1272                            .access_i          ( part_access[k]                  ),
1273                            .access_o          ( part_access_dai[k]              ),
1274                            .digest_o          ( part_digest[k]                  ),
1275                            .data_o            ( part_buf_data[PartInfo[k].offset +: PartInfo[k].size] ),
1276                            .otp_req_o         ( part_otp_arb_req[k]             ),
1277                            .otp_cmd_o         ( part_otp_arb_bundle[k].cmd      ),
1278                            .otp_size_o        ( part_otp_arb_bundle[k].size     ),
1279                            .otp_wdata_o       ( part_otp_arb_bundle[k].wdata    ),
1280                            .otp_addr_o        ( part_otp_arb_bundle[k].addr     ),
1281                            .otp_gnt_i         ( part_otp_arb_gnt[k]             ),
1282                            .otp_rvalid_i      ( part_otp_rvalid[k]              ),
1283                            .otp_rdata_i       ( part_otp_rdata                  ),
1284                            .otp_err_i         ( part_otp_err                    ),
1285                            // The LC partition does not need any scrambling features.
1286                            .scrmbl_mtx_req_o  (                                 ),
1287                            .scrmbl_mtx_gnt_i  ( 1'b0                            ),
1288                            .scrmbl_cmd_o      (                                 ),
1289                            .scrmbl_mode_o     (                                 ),
1290                            .scrmbl_sel_o      (                                 ),
1291                            .scrmbl_data_o     (                                 ),
1292                            .scrmbl_valid_o    (                                 ),
1293                            .scrmbl_ready_i    ( 1'b0                            ),
1294                            .scrmbl_valid_i    ( 1'b0                            ),
1295                            .scrmbl_data_i     ( '0                              )
1296                          );
1297                    
1298                          // Buffered partitions are not accessible via the TL-UL window.
1299                          logic unused_part_tlul_sigs;
1300       0/1     ==>        assign unused_part_tlul_sigs = ^part_tlul_req[k];
1301                          assign part_tlul_gnt[k]    = 1'b0;
1302                          assign part_tlul_rerror[k] = '0;
1303                          assign part_tlul_rvalid[k] = 1'b0;
1304                          assign part_tlul_rdata[k]  = '0;
1305                    
1306                          // Tie off unused connections.
1307                          assign part_scrmbl_mtx_req[k]    = '0;
1308                          assign part_scrmbl_req_bundle[k] = '0;
1309                    
1310                          // This stops lint from complaining about unused signals.
1311                          logic unused_part_scrmbl_sigs;
1312       0/1     ==>        assign unused_part_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[k],
1313                                                             part_scrmbl_req_ready[k],
1314                                                             part_scrmbl_rsp_valid[k]};
1315                          // Alert assertion for sparse FSM.
1316                          `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartLcFsmCheck_A,
1317                              u_part_buf.u_state_regs, alert_tx_o[1])
1318                          `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntPartLcCheck_A,
1319                              u_part_buf.u_prim_count, alert_tx_o[1])
1320                        ////////////////////////////////////////////////////////////////////////////////////////////////
1321                        end else begin : gen_invalid
1322                          // This is invalid and should break elaboration
1323                          assert_static_in_generate_invalid assert_static_in_generate_invalid();
1324                        end
1325                        ////////////////////////////////////////////////////////////////////////////////////////////////
1326                      end
1327                    
1328                      //////////////////////////////////
1329                      // Buffered Data Output Mapping //
1330                      //////////////////////////////////
1331                    
1332                      // Output complete hardware config partition.
1333                      // Actual mapping to other IPs is done via the intersignal topgen feature,
1334                      // selection of fields can be done using the otp_hw_cfg_t struct fields.
1335                      otp_broadcast_t otp_broadcast;
1336       1/1            assign otp_broadcast = named_broadcast_assign(part_init_done, part_buf_data);
           Tests:       T1 T2 T3 
1337                    
1338                      // Make sure the broadcast valid is flopped before sending it out.
1339                      lc_ctrl_pkg::lc_tx_t otp_broadcast_valid_q;
1340                      prim_lc_sender u_prim_lc_sender_otp_broadcast_valid (
1341                        .clk_i,
1342                        .rst_ni,
1343                        .lc_en_i(otp_broadcast.valid),
1344                        .lc_en_o(otp_broadcast_valid_q)
1345                      );
1346                    
1347                      always_comb begin : p_otp_broadcast_valid
1348       1/1              otp_broadcast_o       = otp_broadcast;
           Tests:       T1 T2 T3 
1349       1/1              otp_broadcast_o.valid = otp_broadcast_valid_q;
           Tests:       T1 T2 T3 
1350                      end
1351                    
1352                      // Root keys and seeds.
1353                      // This uses a generated function to assign all collateral that is marked with "iskeymgr" in
1354                      // the memory map. Note that in this case the type is static and represents a superset of all
1355                      // options so that we can maintain a stable interface with keymgr (otherwise keymgr will have
1356                      // to be templated as well. Unused key material will be tied off to '0. The keymgr has to be
1357                      // parameterized accordingly (via SV parameters) to consume the correct key material.
1358                      //
1359                      // The key material valid signals are set to true if the corresponding digest is nonzero and the
1360                      // partition is initialized. On top of that, the entire output is gated by lc_seed_hw_rd_en.
1361                      otp_keymgr_key_t otp_keymgr_key;
1362       1/1            assign otp_keymgr_key = named_keymgr_key_assign(part_digest,
           Tests:       T1 T2 T3 
1363                                                                      part_buf_data,
1364                                                                      lc_seed_hw_rd_en);
1365                    
1366                      // Note regarding these breakouts: named_keymgr_key_assign will tie off unused key material /
1367                      // valid signals to '0. This is the case for instance in system configurations that keep the seed
1368                      // material in the flash instead of OTP.
1369                      logic creator_root_key_share0_valid_d, creator_root_key_share0_valid_q;
1370                      logic creator_root_key_share1_valid_d, creator_root_key_share1_valid_q;
1371                      logic creator_seed_valid_d, creator_seed_valid_q;
1372                      logic owner_seed_valid_d, owner_seed_valid_q;
1373                      prim_flop #(
1374                        .Width(4)
1375                      ) u_keygmr_key_valid (
1376                        .clk_i,
1377                        .rst_ni,
1378                        .d_i ({creator_root_key_share0_valid_d,
1379                               creator_root_key_share1_valid_d,
1380                               creator_seed_valid_d,
1381                               owner_seed_valid_d}),
1382                        .q_o ({creator_root_key_share0_valid_q,
1383                               creator_root_key_share1_valid_q,
1384                               creator_seed_valid_q,
1385                               owner_seed_valid_q})
1386                      );
1387                    
1388                      always_comb begin : p_otp_keymgr_key_valid
1389                        // Valid reg inputs
1390       1/1              creator_root_key_share0_valid_d = otp_keymgr_key.creator_root_key_share0_valid;
           Tests:       T1 T2 T3 
1391       1/1              creator_root_key_share1_valid_d = otp_keymgr_key.creator_root_key_share1_valid;
           Tests:       T1 T2 T3 
1392       1/1              creator_seed_valid_d            = otp_keymgr_key.creator_seed_valid;
           Tests:       T1 T2 T3 
1393       1/1              owner_seed_valid_d              = otp_keymgr_key.owner_seed_valid;
           Tests:       T1 T2 T3 
1394                        // Output to keymgr
1395       1/1              otp_keymgr_key_o                               = otp_keymgr_key;
           Tests:       T1 T2 T3 
1396       1/1              otp_keymgr_key_o.creator_root_key_share0_valid = creator_root_key_share0_valid_q;
           Tests:       T1 T2 T3 
1397       1/1              otp_keymgr_key_o.creator_root_key_share1_valid = creator_root_key_share1_valid_q;
           Tests:       T1 T2 T3 
1398       1/1              otp_keymgr_key_o.creator_seed_valid            = creator_seed_valid_q;
           Tests:       T1 T2 T3 
1399       1/1              otp_keymgr_key_o.owner_seed_valid              = owner_seed_valid_q;
           Tests:       T1 T2 T3 
1400                      end
1401                    
1402                      // Check that the lc_seed_hw_rd_en remains stable, once the key material is valid.
1403                      `ASSERT(LcSeedHwRdEnStable0_A,
1404                        $rose(creator_root_key_share0_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$],
1405                        clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating
1406                      )
1407                      `ASSERT(LcSeedHwRdEnStable1_A,
1408                        $rose(creator_root_key_share1_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$],
1409                        clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating
1410                      )
1411                      `ASSERT(LcSeedHwRdEnStable2_A,
1412                        $rose(creator_seed_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$],
1413                        clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating
1414                      )
1415                      `ASSERT(LcSeedHwRdEnStable3_A,
1416                        $rose(owner_seed_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$],
1417                        clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating
1418                      )
1419                    
1420                      // Scrambling Keys
1421       1/1            assign scrmbl_key_seed_valid = part_digest[Secret1Idx] != '0;
           Tests:       T1 T2 T3 
1422       1/1            assign sram_data_key_seed    = part_buf_data[SramDataKeySeedOffset +:
           Tests:       T1 T2 T3 
1423                                                                   SramDataKeySeedSize];
1424       1/1            assign flash_data_key_seed   = part_buf_data[FlashDataKeySeedOffset +:
           Tests:       T1 T2 T3 
1425                                                                   FlashDataKeySeedSize];
1426       1/1            assign flash_addr_key_seed   = part_buf_data[FlashAddrKeySeedOffset +:
           Tests:       T1 T2 T3 
1427                                                                   FlashAddrKeySeedSize];
1428                    
1429                      // Test unlock and exit tokens and RMA token
1430       1/1            assign otp_lc_data_o.test_exit_token   = part_buf_data[TestExitTokenOffset +:
           Tests:       T1 T2 T3 
1431                                                                             TestExitTokenSize];
1432       1/1            assign otp_lc_data_o.test_unlock_token = part_buf_data[TestUnlockTokenOffset +:
           Tests:       T1 T2 T3 
1433                                                                             TestUnlockTokenSize];
1434       1/1            assign otp_lc_data_o.rma_token         = part_buf_data[RmaTokenOffset +:
           Tests:       T1 T2 T3 
1435                                                                             RmaTokenSize];
1436                    
1437                      lc_ctrl_pkg::lc_tx_t test_tokens_valid, rma_token_valid, secrets_valid;
1438                      // The test tokens have been provisioned.
1439       1/1            assign test_tokens_valid = (part_digest[Secret0Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
           Tests:       T1 T2 T3 
1440                      // The rma token has been provisioned.
1441       1/1            assign rma_token_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
           Tests:       T1 T2 T3 
1442                      // The device is personalized if the root key has been provisioned and locked.
1443       1/1            assign secrets_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
           Tests:       T1 T2 T3 
1444                    
1445                      // Buffer these constants in order to ensure that synthesis does not try to optimize the encoding.
1446                      // SEC_CM: TOKEN_VALID.CTRL.MUBI
1447                      prim_lc_sender #(
1448                        .AsyncOn(0)
1449                      ) u_prim_lc_sender_test_tokens_valid (
1450                        .clk_i,
1451                        .rst_ni,
1452                        .lc_en_i(test_tokens_valid),
1453                        .lc_en_o(otp_lc_data_o.test_tokens_valid)
1454                      );
1455                    
1456                      prim_lc_sender #(
1457                        .AsyncOn(0)
1458                      ) u_prim_lc_sender_rma_token_valid (
1459                        .clk_i,
1460                        .rst_ni,
1461                        .lc_en_i(rma_token_valid),
1462                        .lc_en_o(otp_lc_data_o.rma_token_valid)
1463                      );
1464                    
1465                      prim_lc_sender #(
1466                        .AsyncOn(0)
1467                      ) u_prim_lc_sender_secrets_valid (
1468                        .clk_i,
1469                        .rst_ni,
1470                        .lc_en_i(secrets_valid),
1471                        .lc_en_o(otp_lc_data_o.secrets_valid)
1472                      );
1473                    
1474                      // Lifecycle state
1475       1/1            assign otp_lc_data_o.state = lc_ctrl_state_pkg::lc_state_e'(part_buf_data[LcStateOffset +:
           Tests:       T1 T2 T3 
1476                                                                                                LcStateSize]);
1477       1/1            assign otp_lc_data_o.count = lc_ctrl_state_pkg::lc_cnt_e'(part_buf_data[LcTransitionCntOffset +:
           Tests:       T1 T2 T3 
1478                                                                                              LcTransitionCntSize]);
1479                    
1480                      // Assert life cycle state valid signal only when all partitions have initialized.
1481       1/1            assign otp_lc_data_o.valid    = &part_init_done;
           Tests:       T1 T2 T3 
1482                      // Signal whether there are any errors in the life cycle partition (both correctable and
1483                      // uncorrectable ones). This bit is made available via the JTAG TAP, which is useful for
1484                      // production testing in RAW life cycle state where the OTP regs are not accessible.
1485       1/1            assign otp_lc_data_o.error    = |part_error[LifeCycleIdx];
           Tests:       T1 T2 T3 
1486                    
1487                      // Not all bits of part_buf_data are used here.
1488                      logic unused_buf_data;
1489       1/1            assign unused_buf_data = ^part_buf_data;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : otp_ctrl

	Total	Covered	Percent
Conditions	115	100	86.96
Logical	115	100	86.96
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00110110000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T14,T15,T16

 LINE       288
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T2,T3,T4

 LINE       297
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       298
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       382
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       382
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       386
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       403
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Not Covered

 LINE       445
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       449
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T68,T55

 LINE       469
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T44,T35
1	0	Covered	T3,T68,T55

 LINE       478
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T3,T44,T68
0	0	1	0	Covered	T26,T27,T28
0	1	0	0	Covered	T26,T27,T28
1	0	0	0	Covered	T35,T51,T55

 LINE       527
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       640
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T9,T5

 LINE       642
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T9,T5

 LINE       765
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       766
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       767
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       877
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1421
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T97,T24

 LINE       1439
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T44,T97

 LINE       1439
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T44,T97

 LINE       1441
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T97

 LINE       1441
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T97

 LINE       1443
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T97

 LINE       1443
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T97

---

Toggle Coverage for Module : otp_ctrl

	Total	Covered	Percent
Totals	156	142	91.03
Total Bits	11096	9714	87.55
Total Bits 0->1	5548	4857	87.55
Total Bits 1->0	5548	4857	87.55

Ports	156	142	91.03
Port Bits	11096	9714	87.55
Port Bits 0->1	5548	4857	87.55
Port Bits 1->0	5548	4857	87.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
edn_i.edn_fips	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
edn_i.edn_ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
core_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T24,T55	Yes	T2,T24,T55	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T4,T9,T35	Yes	T4,T9,T35	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T9,T12,T94	Yes	T1,T9,T10	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T9,T10,T12	Yes	T9,T12,T94	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T1,T9,T12	Yes	T9,T10,T12	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T9,T12,T94	Yes	T1,T9,T12	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	INPUT
prim_tl_i.a_valid	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
prim_tl_o.a_ready	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
prim_tl_o.d_error	Yes	Yes	T11,T17,T18	Yes	T19,T20,T21	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T4,*T9	Yes	T2,T4,T9	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T11,T17,T18	Yes	T19,T20,T21	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T2,*T4,*T9	Yes	T2,T4,T9	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	OUTPUT
intr_otp_error_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T11,T17	Yes	T3,T11,T17	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T11,T17	Yes	T3,T11,T17	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T4,T12,T97	Yes	T2,T9,T5	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	No	No		No		OUTPUT
lc_otp_program_i.count[383:0]	Yes	Yes	T186,T230,T236	Yes	T237,T238,T239	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T14,T238,T239	Yes	T184,T186,T236	INPUT
lc_otp_program_i.req	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
lc_otp_program_o.ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_otp_program_o.err	Yes	Yes	T184,T186,T230	Yes	T184,T186,T230	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T4,T9,T35	Yes	T4,T35,T51	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T4,T9,T35	Yes	T4,T9,T35	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T2,T3,T4	Yes	T4,T9,T5	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T3,T4,T97	Yes	T2,T4,T9	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T9,T94,T100	Yes	T9,T94,T100	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T4,T97,T51	Yes	T2,T4,T97	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T4,T44,T97	Yes	T4,T44,T97	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T4,T97,T51	Yes	T2,T4,T97	OUTPUT
otp_lc_data_o.count[1:0]	No	No		No		OUTPUT
otp_lc_data_o.count[4:2]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[5]	No	No		No		OUTPUT
otp_lc_data_o.count[10:6]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[11]	No	No		No		OUTPUT
otp_lc_data_o.count[12]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[13]	No	No		No		OUTPUT
otp_lc_data_o.count[16:14]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[18:17]	No	No		No		OUTPUT
otp_lc_data_o.count[44:19]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[45]	No	No		No		OUTPUT
otp_lc_data_o.count[46]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[47]	No	No		No		OUTPUT
otp_lc_data_o.count[53:48]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[54]	No	No		No		OUTPUT
otp_lc_data_o.count[55]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[56]	No	No		No		OUTPUT
otp_lc_data_o.count[57]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[58]	No	No		No		OUTPUT
otp_lc_data_o.count[70:59]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[71]	No	No		No		OUTPUT
otp_lc_data_o.count[74:72]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[75]	No	No		No		OUTPUT
otp_lc_data_o.count[79:76]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[80]	No	No		No		OUTPUT
otp_lc_data_o.count[89:81]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[90]	No	No		No		OUTPUT
otp_lc_data_o.count[104:91]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[105]	No	No		No		OUTPUT
otp_lc_data_o.count[125:106]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[126]	No	No		No		OUTPUT
otp_lc_data_o.count[140:127]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[141]	No	No		No		OUTPUT
otp_lc_data_o.count[142]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[148:144]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[149]	No	No		No		OUTPUT
otp_lc_data_o.count[152:150]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[153]	No	No		No		OUTPUT
otp_lc_data_o.count[162:154]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T97	OUTPUT
otp_lc_data_o.count[163]	No	No		No		OUTPUT
otp_lc_data_o.count[164]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[174:166]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T97	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[181:176]	Yes	Yes	T4,*T97,*T51	Yes	T4,T97,T35	OUTPUT
otp_lc_data_o.count[183:182]	No	No		No		OUTPUT
otp_lc_data_o.count[187:184]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[188]	No	No		No		OUTPUT
otp_lc_data_o.count[197:189]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[198]	No	No		No		OUTPUT
otp_lc_data_o.count[201:199]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[202]	No	No		No		OUTPUT
otp_lc_data_o.count[233:203]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[234]	No	No		No		OUTPUT
otp_lc_data_o.count[263:235]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[264]	No	No		No		OUTPUT
otp_lc_data_o.count[270:265]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[271]	No	No		No		OUTPUT
otp_lc_data_o.count[280:272]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[281]	No	No		No		OUTPUT
otp_lc_data_o.count[290:282]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[291]	No	No		No		OUTPUT
otp_lc_data_o.count[303:292]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[304]	No	No		No		OUTPUT
otp_lc_data_o.count[306:305]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[307]	No	No		No		OUTPUT
otp_lc_data_o.count[308]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[309]	No	No		No		OUTPUT
otp_lc_data_o.count[317:310]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[319:318]	No	No		No		OUTPUT
otp_lc_data_o.count[333:320]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[334]	No	No		No		OUTPUT
otp_lc_data_o.count[355:335]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[357:356]	No	No		No		OUTPUT
otp_lc_data_o.count[359:358]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[360]	No	No		No		OUTPUT
otp_lc_data_o.count[367:361]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[369:368]	No	No		No		OUTPUT
otp_lc_data_o.count[380:370]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[381]	No	No		No		OUTPUT
otp_lc_data_o.count[383:382]	Yes	Yes	T4,T5,T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[2:0]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[3]	No	No		No		OUTPUT
otp_lc_data_o.state[12:4]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[15:14]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[17:16]	No	No		No		OUTPUT
otp_lc_data_o.state[28:18]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[29]	No	No		No		OUTPUT
otp_lc_data_o.state[36:30]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[37]	No	No		No		OUTPUT
otp_lc_data_o.state[38]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[39]	No	No		No		OUTPUT
otp_lc_data_o.state[47:40]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[48]	No	No		No		OUTPUT
otp_lc_data_o.state[61:49]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[62]	No	No		No		OUTPUT
otp_lc_data_o.state[69:63]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[70]	No	No		No		OUTPUT
otp_lc_data_o.state[76:71]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[77]	No	No		No		OUTPUT
otp_lc_data_o.state[84:78]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[85]	No	No		No		OUTPUT
otp_lc_data_o.state[88:86]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[89]	No	No		No		OUTPUT
otp_lc_data_o.state[92:90]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[94:93]	No	No		No		OUTPUT
otp_lc_data_o.state[97:95]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[98]	No	No		No		OUTPUT
otp_lc_data_o.state[106:99]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[107]	No	No		No		OUTPUT
otp_lc_data_o.state[108]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[109]	No	No		No		OUTPUT
otp_lc_data_o.state[111:110]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[112]	No	No		No		OUTPUT
otp_lc_data_o.state[124:113]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[125]	No	No		No		OUTPUT
otp_lc_data_o.state[138:126]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[139]	No	No		No		OUTPUT
otp_lc_data_o.state[143:140]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[144]	No	No		No		OUTPUT
otp_lc_data_o.state[152:145]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[153]	No	No		No		OUTPUT
otp_lc_data_o.state[155:154]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[156]	No	No		No		OUTPUT
otp_lc_data_o.state[161:157]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[163:162]	No	No		No		OUTPUT
otp_lc_data_o.state[183:164]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[184]	No	No		No		OUTPUT
otp_lc_data_o.state[188:185]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[189]	No	No		No		OUTPUT
otp_lc_data_o.state[198:190]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[199]	No	No		No		OUTPUT
otp_lc_data_o.state[203:200]	Yes	Yes	T4,T5,T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[204]	No	No		No		OUTPUT
otp_lc_data_o.state[215:205]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[216]	No	No		No		OUTPUT
otp_lc_data_o.state[218:217]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[220:219]	No	No		No		OUTPUT
otp_lc_data_o.state[235:221]	Yes	Yes	T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[236]	No	No		No		OUTPUT
otp_lc_data_o.state[252:237]	Yes	Yes	T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[253]	No	No		No		OUTPUT
otp_lc_data_o.state[269:254]	Yes	Yes	T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[270]	No	No		No		OUTPUT
otp_lc_data_o.state[274:271]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[275]	No	No		No		OUTPUT
otp_lc_data_o.state[278:276]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[279]	No	No		No		OUTPUT
otp_lc_data_o.state[283:280]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[284]	No	No		No		OUTPUT
otp_lc_data_o.state[287:285]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[288]	No	No		No		OUTPUT
otp_lc_data_o.state[307:289]	Yes	Yes	T4,*T98,*T133	Yes	T4,T35,T98	OUTPUT
otp_lc_data_o.state[308]	No	No		No		OUTPUT
otp_lc_data_o.state[315:309]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[316]	No	No		No		OUTPUT
otp_lc_data_o.state[317]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[318]	No	No		No		OUTPUT
otp_lc_data_o.state[319]	Yes	Yes	T4,T133,T19	Yes	T4,T133,T19	OUTPUT
otp_lc_data_o.error	Yes	Yes	T3,T9,T44	Yes	T3,T9,T44	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.owner_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed_valid	No	No		No		OUTPUT
otp_keymgr_key_o.creator_seed[255:0]	No	No		No		OUTPUT
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T4,T97,T51	Yes	T2,T4,T97	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0]	Yes	Yes	T51,T240,T241	Yes	T240,T238,T242	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T4,T97,T51	Yes	T2,T4,T97	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0]	Yes	Yes	T3,T12,T97	Yes	T3,T10,T12	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_otp_key_i.data_req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
sram_otp_key_i[1].req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
sram_otp_key_i[2].req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
sram_otp_key_i[3].req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[39:0]	Yes	Yes	T5,T97,T95	Yes	T2,T5,T97	OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0]	Yes	Yes	T44,T97,T131	Yes	T44,T97,T131	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T3,T4,T9	Yes	T2,T4,T5	INPUT
scan_rst_ni	Yes	Yes	T3,T4,T44	Yes	T4,T9,T12	INPUT
scanmode_i[3:0]	Yes	Yes	T4,T5,T97	Yes	T3,T4,T97	INPUT
cio_test_o[7:0]	No	No		No		OUTPUT
cio_test_en_o[7:0]	Yes	Yes	T19,T20,T21	Yes	T11,T17,T18	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
Branches		29	27	93.10
TERNARY	382	2	1	50.00
TERNARY	1439	2	2	100.00
TERNARY	1441	2	2	100.00
TERNARY	1443	2	2	100.00
IF	287	3	2	66.67
IF	308	2	2	100.00
IF	334	2	2	100.00
IF	341	2	2	100.00
IF	407	2	2	100.00
IF	448	2	2	100.00
IF	469	2	2	100.00
IF	472	2	2	100.00
IF	499	2	2	100.00
IF	991	2	2	100.00

382          assign direct_access_regwen_d = (reg2hw.direct_access_regwen.qe &&
                                                                               
383                                           !reg2hw.direct_access_regwen.q) ? 1'b0 : direct_access_regwen_q;
                                                                              -1-  
                                                                              ==>  
                                                                              ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

1439         assign test_tokens_valid = (part_digest[Secret0Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
                                                                        -1-  
                                                                        ==>  
                                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T44,T97
0	Covered	T1,T2,T3

1441         assign rma_token_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
                                                                      -1-  
                                                                      ==>  
                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T97
0	Covered	T1,T2,T3

1443         assign secrets_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
                                                                    -1-  
                                                                    ==>  
                                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T97
0	Covered	T1,T2,T3

287            if (tlul_req) begin
               -1-  
288              if (tlul_part_sel_oh != '0) begin
                 -2-  
289                part_tlul_req[tlul_part_idx] = 1'b1;
                   ==>
290              end else begin
291                // Error out in the next cycle if address was out of bounds.
292                tlul_oob_err_d = 1'b1;
                   ==>
293              end
294            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Not Covered
0	-	Covered	T1,T2,T3

308            if (!rst_ni) begin
               -1-  
309              tlul_oob_err_q <= 1'b0;
                 ==>
310            end else begin
311              tlul_oob_err_q <= tlul_oob_err_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

334            if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en)) begin
               -1-  
335              for (int k = 0; k < NumPart; k++) begin
                 ==>
336                if (PartInfo[k].iskeymgr_creator) begin
337                  part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}};
338                end
339              end
340            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

341            if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en)) begin
               -1-  
342              for (int k = 0; k < NumPart; k++) begin
                 ==>
343                if (PartInfo[k].iskeymgr_owner) begin
344                  part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}};
345                end
346              end
347            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

407            if (!rst_ni) begin
               -1-  
408              otp_idle_q <= 1'b0;
                 ==>
409              // The regwen bit has to reset to 1 so that CSR accesses are enabled by default.
410              direct_access_regwen_q  <= 1'b1;
411            end else begin
412              otp_idle_q <= otp_idle_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

448              if (PartInfo[k].integrity) begin
                 -1-  
449                fatal_macro_error_d |= part_error[k] == MacroEccUncorrError;
                   ==>
450              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

469              if (fatal_macro_error_q || fatal_check_error_q) begin
                 -1-  
470                lc_escalate_en[k] = lc_ctrl_pkg::On;
                   ==>
471              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T44
0	Covered	T1,T2,T3

472              if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k])) begin
                 -1-  
473                lc_escalate_en_any = 1'b1;
                   ==>
474              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T44
0	Covered	T1,T2,T3

499            if (!rst_ni) begin
               -1-  
500              fatal_macro_error_q     <= '0;
                 ==>
501              fatal_check_error_q     <= '0;
502              fatal_bus_integ_error_q <= '0;
503              interrupt_triggers_q    <= '0;
504            end else begin
505              fatal_macro_error_q     <= fatal_macro_error_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

991            if (!rst_ni) begin
               -1-  
992              pwr_otp_rsp_q <= 1'b0;
                 ==>
993            end else begin
994              pwr_otp_rsp_q <= pwr_otp_rsp_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	71	71	100.00	69	97.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	71	71	100.00	69	97.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	84443599	83613730	0	0
CoreTlOutKnown_A	84443599	83613730	0	0
CreatorRootKeyShare0Size_A	1114	1114	0	0
CreatorRootKeyShare1Size_A	1114	1114	0	0
ErrorCodeWidth_A	1114	1114	0	0
FlashAddrKeySeedSize_A	1114	1114	0	0
FlashDataKeySeedSize_A	1114	1114	0	0
FlashOtpKeyRspKnown_A	84443599	83613730	0	0
FpvSecCmCntCnstyCheck_A	84443599	50	0	0
FpvSecCmCntDaiCheck_A	84443599	50	0	0
FpvSecCmCntIntegCheck_A	84443599	50	0	0
FpvSecCmCntKdiEntropyCheck_A	84443599	50	0	0
FpvSecCmCntKdiSeedCheck_A	84443599	50	0	0
FpvSecCmCntLciCheck_A	84443599	50	0	0
FpvSecCmCntScrmblCheck_A	84443599	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	84443599	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	84443599	50	0	0
FpvSecCmCtrlLciFsmCheck_A	84443599	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	84443599	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	84443599	50	0	0
FpvSecCmDoubleLfsrCheck_A	84443599	50	0	0
FpvSecCmRegWeOnehotCheck_A	84443599	50	0	0
FpvSecCmTlLcGateFsm_A	84443599	50	0	0
IntrOtpErrorKnown_A	84443599	83613730	0	0
IntrOtpOperationDoneKnown_A	84443599	83613730	0	0
LcOtpProgramRspKnown_A	84443599	83613730	0	0
LcSeedHwRdEnStable0_A	84443599	2120	0	0
LcSeedHwRdEnStable1_A	84443599	2120	0	0
LcSeedHwRdEnStable2_A	84443599	0	0	0
LcSeedHwRdEnStable3_A	84443599	0	0	0
LcStateSize_A	1114	1114	0	0
LcTransitionCntSize_A	1114	1114	0	0
OtpAstPwrSeqKnown_A	84443599	83613730	0	0
OtpBroadcastKnown_A	84443599	83613730	0	0
OtpErrorCode0_A	1114	1114	0	0
OtpErrorCode1_A	1114	1114	0	0
OtpErrorCode2_A	1114	1114	0	0
OtpErrorCode3_A	1114	1114	0	0
OtpErrorCode4_A	1114	1114	0	0
OtpIfWidth_A	1114	1114	0	0
OtpKeymgrKeyKnown_A	84443599	83613730	0	0
OtpLcDataKnown_A	84443599	83613730	0	0
OtpOtgnKeyKnown_A	84443599	83613730	0	0
OtpRespFifoUnderflow_A	84443599	1162017	0	0
OtpSramKeyKnown_A	84443599	83613730	0	0
PartSelMustBeOnehot_A	84443599	83613730	0	0
PrimTlOutKnown_A	84443599	83613730	0	0
PwrOtpInitRspKnown_A	84443599	83613730	0	0
RmaTokenSize_A	1114	1114	0	0
SramDataKeySeedSize_A	1114	1114	0	0
TestExitTokenSize_A	1114	1114	0	0
TestUnlockTokenSize_A	1114	1114	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	84443599	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	84443599	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	84443599	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	84443599	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	2120	0	0
T2	12798	1	0	0
T3	10127	0	0	0
T4	55214	6	0	0
T5	18048	0	0	0
T9	22622	0	0	0
T10	59751	0	0	0
T11	4514	0	0	0
T12	12039	0	0	0
T13	47890	0	0	0
T17	4541	0	0	0
T19	0	4	0	0
T51	0	3	0	0
T95	0	5	0	0
T97	0	2	0	0
T98	0	5	0	0
T124	0	8	0	0
T130	0	2	0	0
T131	0	2	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	2120	0	0
T2	12798	1	0	0
T3	10127	0	0	0
T4	55214	6	0	0
T5	18048	0	0	0
T9	22622	0	0	0
T10	59751	0	0	0
T11	4514	0	0	0
T12	12039	0	0	0
T13	47890	0	0	0
T17	4541	0	0	0
T19	0	4	0	0
T51	0	3	0	0
T95	0	5	0	0
T97	0	2	0	0
T98	0	5	0	0
T124	0	8	0	0
T130	0	2	0	0
T131	0	2	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	1162017	0	0
T1	5120	111	0	0
T2	12798	235	0	0
T3	10127	171	0	0
T4	55214	2350	0	0
T5	18048	266	0	0
T9	22622	151	0	0
T10	59751	1356	0	0
T11	4514	55	0	0
T12	12039	299	0	0
T13	47890	949	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		154	145	94.16
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
ALWAYS	284	13	13	100.00
ALWAYS	308	3	3	100.00
ALWAYS	324	10	10	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	5	5	100.00
ALWAYS	434	19	19	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	9	9	100.00
ALWAYS	521	10	10	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	766	1	1	100.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
ALWAYS	876	2	2	100.00
ALWAYS	934	2	2	100.00
ALWAYS	961	4	4	100.00
CONT_ASSIGN	988	1	1	100.00
ALWAYS	991	3	3	100.00
CONT_ASSIGN	1043	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1079	1	0	0.00
CONT_ASSIGN	1130	1	0	0.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1240	1	0	0.00
CONT_ASSIGN	1300	1	0	0.00
CONT_ASSIGN	1312	1	0	0.00
CONT_ASSIGN	1336	1	1	100.00
ALWAYS	1348	2	2	100.00
CONT_ASSIGN	1362	1	1	100.00
ALWAYS	1390	9	9	100.00
CONT_ASSIGN	1421	1	1	100.00
CONT_ASSIGN	1422	1	1	100.00
CONT_ASSIGN	1424	1	1	100.00
CONT_ASSIGN	1426	1	1	100.00
CONT_ASSIGN	1430	1	1	100.00
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00
CONT_ASSIGN	1439	1	1	100.00
CONT_ASSIGN	1441	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1475	1	1	100.00
CONT_ASSIGN	1477	1	1	100.00
CONT_ASSIGN	1481	1	1	100.00
CONT_ASSIGN	1485	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00

250                         if (PartInfo[k].offset == 0) begin : gen_zero_offset
251        1/1                assign tlul_part_sel_oh[k] = ({1'b0, {tlul_addr, 2'b00}} < PartEnd);
           Tests:       T1 T2 T3 
252                         end else begin : gen_nonzero_offset
253        10/10              assign tlul_part_sel_oh[k] = ({tlul_addr, 2'b00} >= PartInfo[k].offset) &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
254                                                        ({1'b0, {tlul_addr, 2'b00}} < PartEnd);
255                         end
256                       end
257                     
258                       `ASSERT(PartSelMustBeOnehot_A, $onehot0(tlul_part_sel_oh))
259                     
260                       logic [NumPartWidth-1:0] tlul_part_idx;
261                       prim_arbiter_fixed #(
262                         .N(NumPart),
263                         .EnDataPort(0)
264                       ) u_part_sel_idx (
265                         .clk_i,
266                         .rst_ni,
267                         .req_i   ( tlul_part_sel_oh  ),
268                         .data_i  ( '{default: '0}    ),
269                         .gnt_o   (                   ), // unused
270                         .idx_o   ( tlul_part_idx     ),
271                         .valid_o (                   ), // unused
272                         .data_o  (                   ), // unused
273                         .ready_i ( 1'b0              )
274                       );
275                     
276                       logic tlul_oob_err_d, tlul_oob_err_q;
277                       logic [NumPart-1:0] part_tlul_req, part_tlul_gnt, part_tlul_rvalid;
278                       logic [SwWindowAddrWidth-1:0] part_tlul_addr;
279                       logic [NumPart-1:0][1:0]  part_tlul_rerror;
280                       logic [NumPart-1:0][31:0] part_tlul_rdata;
281                     
282                       always_comb begin : p_tlul_assign
283                         // Send request to the correct partition.
284        1/1              part_tlul_addr   = tlul_addr;
           Tests:       T1 T2 T3 
285        1/1              part_tlul_req    = '0;
           Tests:       T1 T2 T3 
286        1/1              tlul_oob_err_d   = 1'b0;
           Tests:       T1 T2 T3 
287        1/1              if (tlul_req) begin
           Tests:       T1 T2 T3 
288        1/1                if (tlul_part_sel_oh != '0) begin
           Tests:       T2 T3 T4 
289        1/1                  part_tlul_req[tlul_part_idx] = 1'b1;
           Tests:       T2 T3 T4 
290                           end else begin
291                             // Error out in the next cycle if address was out of bounds.
292        excluded             tlul_oob_err_d = 1'b1;
Exclude Annotation: VC_COV_UNR
293                           end
294                         end
                        MISSING_ELSE
295                     
296                         // aggregate TL-UL responses
297        1/1              tlul_gnt         = |part_tlul_gnt    | tlul_oob_err_q;
           Tests:       T1 T2 T3 
298        1/1              tlul_rvalid      = |part_tlul_rvalid | tlul_oob_err_q;
           Tests:       T1 T2 T3 
299        1/1              tlul_rerror      = '0;
           Tests:       T1 T2 T3 
300        1/1              tlul_rdata       = '0;
           Tests:       T1 T2 T3 
301        1/1              for (int k = 0; k < NumPart; k++) begin
           Tests:       T1 T2 T3 
302        1/1                tlul_rerror |= part_tlul_rerror[k];
           Tests:       T1 T2 T3 
303        1/1                tlul_rdata  |= part_tlul_rdata[k];
           Tests:       T1 T2 T3 
304                         end
305                       end
306                     
307                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlul_reg
308        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
309        1/1                tlul_oob_err_q <= 1'b0;
           Tests:       T1 T2 T3 
310                         end else begin
311        1/1                tlul_oob_err_q <= tlul_oob_err_d;
           Tests:       T1 T2 T3 
312                         end
313                       end
314                     
315                       //////////////////////////////
316                       // Access Defaults and CSRs //
317                       //////////////////////////////
318                     
319                       // SEC_CM: ACCESS.CTRL.MUBI
320                       part_access_t [NumPart-1:0] part_access_pre, part_access;
321                       always_comb begin : p_access_control
322                         // Assigns default and extracts named CSR read enables for SW_CFG partitions.
323                         // SEC_CM: PART.MEM.REGREN
324        1/1              part_access_pre = named_part_access_pre(reg2hw);
           Tests:       T1 T2 T3 
325                     
326                         // Permanently lock DAI write and read access to the life cycle partition.
327                         // The LC partition can only be read from and written to via the LC controller.
328                         // SEC_CM: LC_PART.MEM.SW_NOACCESS
329        1/1              part_access_pre[LifeCycleIdx].write_lock = MuBi8True;
           Tests:       T1 T2 T3 
330        1/1              part_access_pre[LifeCycleIdx].read_lock = MuBi8True;
           Tests:       T1 T2 T3 
331                     
332                         // Special partitions for keymgr material only become writable when
333                         // provisioning is enabled.
334        1/1              if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en)) begin
           Tests:       T1 T2 T3 
335        1/1                for (int k = 0; k < NumPart; k++) begin
           Tests:       T1 T2 T3 
336        1/1                  if (PartInfo[k].iskeymgr_creator) begin
           Tests:       T1 T2 T3 
337        1/1                    part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}};
           Tests:       T1 T2 T3 
338                             end
                        MISSING_ELSE
339                           end
340                         end
                        MISSING_ELSE
341        1/1              if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en)) begin
           Tests:       T1 T2 T3 
342        1/1                for (int k = 0; k < NumPart; k++) begin
           Tests:       T1 T2 T3 
343        1/1                  if (PartInfo[k].iskeymgr_owner) begin
           Tests:       T1 T2 T3 
344        excluded               part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}};
Exclude Annotation: VC_COV_UNR
345                             end
                        MISSING_ELSE
346                           end
347                         end
                        MISSING_ELSE
348                       end
349                     
350                       // This prevents the synthesis tool from optimizing the multibit signals.
351                       for (genvar k = 0; k < NumPart; k++) begin : gen_bufs
352                         prim_mubi8_sender #(
353                           .AsyncOn(0)
354                         ) u_prim_mubi8_sender_write_lock (
355                           .clk_i,
356                           .rst_ni,
357                           .mubi_i(part_access_pre[k].write_lock),
358                           .mubi_o(part_access[k].write_lock)
359                         );
360                         prim_mubi8_sender #(
361                           .AsyncOn(0)
362                         ) u_prim_mubi8_sender_read_lock (
363                           .clk_i,
364                           .rst_ni,
365                           .mubi_i(part_access_pre[k].read_lock),
366                           .mubi_o(part_access[k].read_lock)
367                         );
368                       end
369                     
370                       //////////////////////
371                       // DAI-related CSRs //
372                       //////////////////////
373                     
374                       logic                         dai_idle;
375                       logic                         dai_req;
376                       dai_cmd_e                     dai_cmd;
377                       logic [OtpByteAddrWidth-1:0]  dai_addr;
378                       logic [NumDaiWords-1:0][31:0] dai_wdata, dai_rdata;
379                       logic direct_access_regwen_d, direct_access_regwen_q;
380                     
381                       // This is the HWEXT implementation of a RW0C regwen bit.
382        1/1            assign direct_access_regwen_d = (reg2hw.direct_access_regwen.qe &&
           Tests:       T1 T2 T3 
383                                                        !reg2hw.direct_access_regwen.q) ? 1'b0 : direct_access_regwen_q;
384                     
385                       // Any write to this register triggers a DAI command.
386        1/1            assign dai_req = reg2hw.direct_access_cmd.digest.qe |
           Tests:       T1 T2 T3 
387                                        reg2hw.direct_access_cmd.wr.qe  |
388                                        reg2hw.direct_access_cmd.rd.qe;
389                     
390        1/1            assign dai_cmd = dai_cmd_e'({reg2hw.direct_access_cmd.digest.q,
           Tests:       T1 T2 T3 
391                                                    reg2hw.direct_access_cmd.wr.q,
392                                                    reg2hw.direct_access_cmd.rd.q});
393                     
394        1/1            assign dai_addr  = reg2hw.direct_access_address.q;
           Tests:       T1 T2 T3 
395        1/1            assign dai_wdata = reg2hw.direct_access_wdata;
           Tests:       T1 T2 T3 
396                     
397                       // The DAI and the LCI can initiate write transactions, which
398                       // are critical and we must not power down if such transactions
399                       // are pending. Hence, we signal the LCI/DAI idle state to the
400                       // power manager. This signal is flopped here as it has to
401                       // cross a clock boundary to the power manager.
402                       logic dai_prog_idle, lci_prog_idle, otp_idle_d, otp_idle_q;
403        1/1            assign otp_idle_d = lci_prog_idle & dai_prog_idle;
           Tests:       T1 T2 T3 
404        1/1            assign pwr_otp_o.otp_idle = otp_idle_q;
           Tests:       T1 T2 T3 
405                     
406                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_idle_regwen_regs
407        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
408        1/1                otp_idle_q <= 1'b0;
           Tests:       T1 T2 T3 
409                           // The regwen bit has to reset to 1 so that CSR accesses are enabled by default.
410        1/1                direct_access_regwen_q  <= 1'b1;
           Tests:       T1 T2 T3 
411                         end else begin
412        1/1                otp_idle_q <= otp_idle_d;
           Tests:       T1 T2 T3 
413        1/1                direct_access_regwen_q <= direct_access_regwen_d;
           Tests:       T1 T2 T3 
414                         end
415                       end
416                     
417                       //////////////////////////////////////
418                       // Ctrl/Status CSRs, Errors, Alerts //
419                       //////////////////////////////////////
420                     
421                       // Status and error reporting CSRs, error interrupt generation and alerts.
422                       otp_err_e [NumPart+1:0] part_error;
423                       logic [NumAgents-1:0] part_fsm_err;
424                       logic [NumPart+1:0] part_errors_reduced;
425                       logic otp_operation_done, otp_error;
426                       logic fatal_macro_error_d, fatal_macro_error_q;
427                       logic fatal_check_error_d, fatal_check_error_q;
428                       logic fatal_bus_integ_error_d, fatal_bus_integ_error_q;
429                       logic chk_pending, chk_timeout;
430                       logic lfsr_fsm_err, scrmbl_fsm_err;
431                       always_comb begin : p_errors_alerts
432                         // Note: since these are all fatal alert events, we latch them and keep on sending
433                         // alert events via the alert senders. These regs can only be cleared via a system reset.
434        1/1              fatal_macro_error_d = fatal_macro_error_q;
           Tests:       T1 T2 T3 
435        1/1              fatal_check_error_d = fatal_check_error_q;
           Tests:       T1 T2 T3 
436        1/1              fatal_bus_integ_error_d = fatal_bus_integ_error_q | (|intg_error);
           Tests:       T1 T2 T3 
437                         // These are the per-partition buffered escalation inputs
438        1/1              lc_escalate_en = lc_escalate_en_synced;
           Tests:       T1 T2 T3 
439                         // Need a single wire for gating assertions in arbitration and CDC primitives.
440        1/1              lc_escalate_en_any = 1'b0;
           Tests:       T1 T2 T3 
441                     
442                         // Aggregate all the macro alerts from the partitions
443        1/1              for (int k = 0; k < NumPart; k++) begin
           Tests:       T1 T2 T3 
444                           // Filter for critical error codes that should not occur in the field.
445        1/1                fatal_macro_error_d |= part_error[k] == MacroError;
           Tests:       T1 T2 T3 
446                           // While uncorrectable ECC errors are always reported, they do not trigger a fatal alert
447                           // event in some partitions like the VENDOR_TEST partition.
448        1/1                if (PartInfo[k].integrity) begin
           Tests:       T1 T2 T3 
449        1/1                  fatal_macro_error_d |= part_error[k] == MacroEccUncorrError;
           Tests:       T1 T2 T3 
450                           end
                        MISSING_ELSE
451                         end
452                         // Aggregate all the macro alerts from the DAI/LCI
453        1/1              for (int k = NumPart; k < NumPart+2; k++) begin
           Tests:       T1 T2 T3 
454                           // Filter for critical error codes that should not occur in the field.
455        1/1                fatal_macro_error_d |= part_error[k] inside {MacroError, MacroEccUncorrError};
           Tests:       T1 T2 T3 
456                         end
457                     
458                         // Aggregate all the remaining errors / alerts from the partitions and the DAI/LCI
459        1/1              for (int k = 0; k < NumPart+2; k++) begin
           Tests:       T1 T2 T3 
460                           // Set the error bit if the error status of the corresponding partition is nonzero.
461                           // Need to reverse the order here since the field enumeration in hw2reg.status is reversed.
462        1/1                part_errors_reduced[NumPart+1-k] = |part_error[k];
           Tests:       T1 T2 T3 
463                           // Filter for integrity and consistency check failures.
464        1/1                fatal_check_error_d |= part_error[k] inside {CheckFailError, FsmStateError};
           Tests:       T1 T2 T3 
465                     
466                           // If a fatal alert has been observed in any of the partitions/FSMs,
467                           // we locally trigger escalation within OTP, which moves all FSMs
468                           // to a terminal error state.
469        1/1                if (fatal_macro_error_q || fatal_check_error_q) begin
           Tests:       T1 T2 T3 
470        1/1                  lc_escalate_en[k] = lc_ctrl_pkg::On;
           Tests:       T3 T9 T44 
471                           end
                        MISSING_ELSE
472        1/1                if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k])) begin
           Tests:       T1 T2 T3 
473        1/1                  lc_escalate_en_any = 1'b1;
           Tests:       T3 T9 T44 
474                           end
                        MISSING_ELSE
475                         end
476                     
477                         // Errors from other non-partition FSMs.
478        1/1              fatal_check_error_d |= chk_timeout       |
           Tests:       T1 T2 T3 
479                                                lfsr_fsm_err      |
480                                                scrmbl_fsm_err    |
481                                                (|part_fsm_err);
482                       end
483                     
484                       // If we got an error, we trigger an interrupt.
485                       logic [$bits(part_errors_reduced)+4-1:0] interrupt_triggers_d, interrupt_triggers_q;
486                     
487                       // This makes sure that interrupts are not sticky.
488        1/1            assign interrupt_triggers_d = {
           Tests:       T1 T2 T3 
489                         part_errors_reduced,
490                         chk_timeout,
491                         lfsr_fsm_err,
492                         scrmbl_fsm_err,
493                         |part_fsm_err
494                       };
495                     
496        1/1            assign otp_error = |(interrupt_triggers_d & ~interrupt_triggers_q);
           Tests:       T1 T2 T3 
497                     
498                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_alert_regs
499        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
500        1/1                fatal_macro_error_q     <= '0;
           Tests:       T1 T2 T3 
501        1/1                fatal_check_error_q     <= '0;
           Tests:       T1 T2 T3 
502        1/1                fatal_bus_integ_error_q <= '0;
           Tests:       T1 T2 T3 
503        1/1                interrupt_triggers_q    <= '0;
           Tests:       T1 T2 T3 
504                         end else begin
505        1/1                fatal_macro_error_q     <= fatal_macro_error_d;
           Tests:       T1 T2 T3 
506        1/1                fatal_check_error_q     <= fatal_check_error_d;
           Tests:       T1 T2 T3 
507        1/1                fatal_bus_integ_error_q <= fatal_bus_integ_error_d;
           Tests:       T1 T2 T3 
508        1/1                interrupt_triggers_q    <= interrupt_triggers_d;
           Tests:       T1 T2 T3 
509                         end
510                       end
511                     
512                       // CSR assignments are done in one combo process so that we can use
513                       // the parameterized digest_assign task below without multiple driver issues.
514                       logic unused_part_digest;
515                       logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest;
516                       logic intr_state_otp_operation_done_d, intr_state_otp_operation_done_de;
517                       logic intr_state_otp_error_d, intr_state_otp_error_de;
518                       always_comb begin : p_csr_assign
519                         // Not all partition digests are consumed, and assigning them to an unused_* signal in the
520                         // function below does not seem to work for some linters.
521        1/1              unused_part_digest = ^part_digest;
           Tests:       T1 T2 T3 
522                         // Assign named CSRs (like digests).
523        1/1              hw2reg = named_reg_assign(part_digest);
           Tests:       T1 T2 T3 
524                         // DAI related CSRs
525        1/1              hw2reg.direct_access_rdata = dai_rdata;
           Tests:       T1 T2 T3 
526                         // ANDing this state with dai_idle write-protects all DAI regs during pending operations.
527        1/1              hw2reg.direct_access_regwen.d = direct_access_regwen_q & dai_idle;
           Tests:       T1 T2 T3 
528                         // Assign these to the status register.
529        1/1              hw2reg.status = {part_errors_reduced,
           Tests:       T1 T2 T3 
530                                          chk_timeout,
531                                          lfsr_fsm_err,
532                                          scrmbl_fsm_err,
533                                          part_fsm_err[KdiIdx],
534                                          fatal_bus_integ_error_q,
535                                          dai_idle,
536                                          chk_pending};
537                         // Error code registers.
538        1/1              hw2reg.err_code = part_error;
           Tests:       T1 T2 T3 
539                         // Interrupt signals
540        1/1              hw2reg.intr_state.otp_operation_done.de = intr_state_otp_operation_done_de;
           Tests:       T1 T2 T3 
541        1/1              hw2reg.intr_state.otp_operation_done.d  = intr_state_otp_operation_done_d;
           Tests:       T1 T2 T3 
542        1/1              hw2reg.intr_state.otp_error.de = intr_state_otp_error_de;
           Tests:       T1 T2 T3 
543        1/1              hw2reg.intr_state.otp_error.d  = intr_state_otp_error_d;
           Tests:       T1 T2 T3 
544                     end
545                     
546                     
547                       //////////////////////////////////
548                       // Interrupts and Alert Senders //
549                       //////////////////////////////////
550                     
551                       prim_intr_hw #(
552                         .Width(1)
553                       ) u_intr_operation_done (
554                         .clk_i,
555                         .rst_ni,
556                         .event_intr_i           ( otp_operation_done                      ),
557                         .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.otp_operation_done.q ),
558                         .reg2hw_intr_test_q_i   ( reg2hw.intr_test.otp_operation_done.q   ),
559                         .reg2hw_intr_test_qe_i  ( reg2hw.intr_test.otp_operation_done.qe  ),
560                         .reg2hw_intr_state_q_i  ( reg2hw.intr_state.otp_operation_done.q  ),
561                         .hw2reg_intr_state_de_o ( intr_state_otp_operation_done_de        ),
562                         .hw2reg_intr_state_d_o  ( intr_state_otp_operation_done_d         ),
563                         .intr_o                 ( intr_otp_operation_done_o               )
564                       );
565                     
566                       prim_intr_hw #(
567                         .Width(1)
568                       ) u_intr_error (
569                         .clk_i,
570                         .rst_ni,
571                         .event_intr_i           ( otp_error                      ),
572                         .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.otp_error.q ),
573                         .reg2hw_intr_test_q_i   ( reg2hw.intr_test.otp_error.q   ),
574                         .reg2hw_intr_test_qe_i  ( reg2hw.intr_test.otp_error.qe  ),
575                         .reg2hw_intr_state_q_i  ( reg2hw.intr_state.otp_error.q  ),
576                         .hw2reg_intr_state_de_o ( intr_state_otp_error_de        ),
577                         .hw2reg_intr_state_d_o  ( intr_state_otp_error_d         ),
578                         .intr_o                 ( intr_otp_error_o               )
579                       );
580                     
581                       logic [NumAlerts-1:0] alerts;
582                       logic [NumAlerts-1:0] alert_test;
583                       logic fatal_prim_otp_alert, recov_prim_otp_alert;
584                     
585        1/1            assign alerts = {
           Tests:       T1 T2 T3 
586                         recov_prim_otp_alert,
587                         fatal_prim_otp_alert,
588                         fatal_bus_integ_error_q,
589                         fatal_check_error_q,
590                         fatal_macro_error_q
591                       };
592                     
593        1/1            assign alert_test = {
           Tests:       T1 T2 T3 
594                         reg2hw.alert_test.recov_prim_otp_alert.q &
595                         reg2hw.alert_test.recov_prim_otp_alert.qe,
596                         reg2hw.alert_test.fatal_prim_otp_alert.q &
597                         reg2hw.alert_test.fatal_prim_otp_alert.qe,
598                         reg2hw.alert_test.fatal_bus_integ_error.q &
599                         reg2hw.alert_test.fatal_bus_integ_error.qe,
600                         reg2hw.alert_test.fatal_check_error.q &
601                         reg2hw.alert_test.fatal_check_error.qe,
602                         reg2hw.alert_test.fatal_macro_error.q &
603                         reg2hw.alert_test.fatal_macro_error.qe
604                       };
605                     
606                       localparam logic [NumAlerts-1:0] AlertIsFatal = {
607                         1'b0, // recov_prim_otp_alert
608                         1'b1, // fatal_prim_otp_alert
609                         1'b1, // fatal_bus_integ_error_q
610                         1'b1, // fatal_check_error_q
611                         1'b1  // fatal_macro_error_q
612                       };
613                     
614                       for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx
615                         prim_alert_sender #(
616                           .AsyncOn(AlertAsyncOn[k]),
617                           .IsFatal(AlertIsFatal[k])
618                         ) u_prim_alert_sender (
619                           .clk_i,
620                           .rst_ni,
621                           .alert_test_i  ( alert_test[k] ),
622                           .alert_req_i   ( alerts[k]     ),
623                           .alert_ack_o   (               ),
624                           .alert_state_o (               ),
625                           .alert_rx_i    ( alert_rx_i[k] ),
626                           .alert_tx_o    ( alert_tx_o[k] )
627                         );
628                       end
629                     
630                       ////////////////////////////////
631                       // LFSR Timer and CSR mapping //
632                       ////////////////////////////////
633                     
634                       logic integ_chk_trig, cnsty_chk_trig;
635                       logic [NumPart-1:0] integ_chk_req, integ_chk_ack;
636                       logic [NumPart-1:0] cnsty_chk_req, cnsty_chk_ack;
637                       logic lfsr_edn_req, lfsr_edn_ack;
638                       logic [EdnDataWidth-1:0] edn_data;
639                     
640        1/1            assign integ_chk_trig   = reg2hw.check_trigger.integrity.q &
           Tests:       T1 T2 T3 
641                                                 reg2hw.check_trigger.integrity.qe;
642        1/1            assign cnsty_chk_trig   = reg2hw.check_trigger.consistency.q &
           Tests:       T1 T2 T3 
643                                                 reg2hw.check_trigger.consistency.qe;
644                     
645                       // SEC_CM: PART.DATA_REG.BKGN_CHK
646                       otp_ctrl_lfsr_timer #(
647                         .RndCnstLfsrSeed(RndCnstLfsrSeed),
648                         .RndCnstLfsrPerm(RndCnstLfsrPerm)
649                       ) u_otp_ctrl_lfsr_timer (
650                         .clk_i,
651                         .rst_ni,
652                         .edn_req_o          ( lfsr_edn_req              ),
653                         .edn_ack_i          ( lfsr_edn_ack              ),
654                         .edn_data_i         ( edn_data                  ),
655                         // We can enable the timer once OTP has initialized.
656                         // Note that this is only the initial release that gets
657                         // the timer FSM into an operational state.
658                         // Whether or not the timers / background checks are
659                         // activated depends on the CSR configuration (by default
660                         // they are switched off).
661                         .timer_en_i         ( pwr_otp_o.otp_done        ),
662                         // This idle signal is the same that is output to the power
663                         // manager, and indicates whether there is an ongoing OTP programming
664                         // operation. It is used to pause the consistency check timeout
665                         // counter in order to prevent spurious timeouts (OTP programming
666                         // operations are very slow compared to readout operations and can
667                         // hence interfere with the timeout mechanism).
668                         .otp_prog_busy_i    ( ~otp_idle_d               ),
669                         .integ_chk_trig_i   ( integ_chk_trig            ),
670                         .cnsty_chk_trig_i   ( cnsty_chk_trig            ),
671                         .chk_pending_o      ( chk_pending               ),
672                         .timeout_i          ( reg2hw.check_timeout.q    ),
673                         .integ_period_msk_i ( reg2hw.integrity_check_period.q   ),
674                         .cnsty_period_msk_i ( reg2hw.consistency_check_period.q ),
675                         .integ_chk_req_o    ( integ_chk_req             ),
676                         .cnsty_chk_req_o    ( cnsty_chk_req             ),
677                         .integ_chk_ack_i    ( integ_chk_ack             ),
678                         .cnsty_chk_ack_i    ( cnsty_chk_ack             ),
679                         .escalate_en_i      ( lc_escalate_en[NumAgents] ),
680                         .chk_timeout_o      ( chk_timeout               ),
681                         .fsm_err_o          ( lfsr_fsm_err              )
682                       );
683                     
684                       ///////////////////////////////////////
685                       // EDN Arbitration, Request and Sync //
686                       ///////////////////////////////////////
687                     
688                       // Both the key derivation and LFSR reseeding are low bandwidth,
689                       // hence they can share the same EDN interface.
690                       logic edn_req, edn_ack;
691                       logic key_edn_req, key_edn_ack;
692                       prim_arbiter_tree #(
693                         .N(2),
694                         .EnDataPort(0)
695                       ) u_edn_arb (
696                         .clk_i,
697                         .rst_ni,
698                         .req_chk_i ( ~lc_escalate_en_any         ),
699                         .req_i     ( {lfsr_edn_req, key_edn_req} ),
700                         .data_i    ( '{default: '0}              ),
701                         .gnt_o     ( {lfsr_edn_ack, key_edn_ack} ),
702                         .idx_o     (                             ), // unused
703                         .valid_o   ( edn_req                     ),
704                         .data_o    (                             ), // unused
705                         .ready_i   ( edn_ack                     )
706                       );
707                     
708                       // This synchronizes the data coming from EDN and stacks the
709                       // 32bit EDN words to achieve an internal entropy width of 64bit.
710                       prim_edn_req #(
711                         .OutWidth(EdnDataWidth)
712                       ) u_prim_edn_req (
713                         .clk_i,
714                         .rst_ni,
715                         .req_chk_i ( ~lc_escalate_en_any ),
716                         .req_i     ( edn_req             ),
717                         .ack_o     ( edn_ack             ),
718                         .data_o    ( edn_data            ),
719                         .fips_o    (                     ), // unused
720                         .err_o     (                     ), // unused
721                         .clk_edn_i,
722                         .rst_edn_ni,
723                         .edn_o,
724                         .edn_i
725                       );
726                     
727                       ///////////////////////////////
728                       // OTP Macro and Arbitration //
729                       ///////////////////////////////
730                     
731                       typedef struct packed {
732                         prim_otp_pkg::cmd_e          cmd;
733                         logic [OtpSizeWidth-1:0]     size; // Number of native words to write.
734                         logic [OtpIfWidth-1:0]       wdata;
735                         logic [OtpAddrWidth-1:0]     addr; // Halfword address.
736                       } otp_bundle_t;
737                     
738                       logic [NumAgents-1:0]        part_otp_arb_req, part_otp_arb_gnt;
739                       otp_bundle_t                 part_otp_arb_bundle [NumAgents];
740                       logic                        otp_arb_valid, otp_arb_ready;
741                       logic                        otp_prim_valid, otp_prim_ready;
742                       logic                        otp_rsp_fifo_valid, otp_rsp_fifo_ready;
743                       logic [vbits(NumAgents)-1:0] otp_arb_idx;
744                       otp_bundle_t                 otp_arb_bundle;
745                     
746                       // The OTP interface is arbitrated on a per-cycle basis, meaning that back-to-back
747                       // transactions can be completely independent.
748                       prim_arbiter_tree #(
749                         .N(NumAgents),
750                         .DW($bits(otp_bundle_t))
751                       ) u_otp_arb (
752                         .clk_i,
753                         .rst_ni,
754                         .req_chk_i ( ~lc_escalate_en_any ),
755                         .req_i     ( part_otp_arb_req    ),
756                         .data_i    ( part_otp_arb_bundle ),
757                         .gnt_o     ( part_otp_arb_gnt    ),
758                         .idx_o     ( otp_arb_idx         ),
759                         .valid_o   ( otp_arb_valid       ),
760                         .data_o    ( otp_arb_bundle      ),
761                         .ready_i   ( otp_arb_ready       )
762                       );
763                     
764                       // Don't issue more transactions than what the rsp_fifo can keep track of.
765        1/1            assign otp_arb_ready      = otp_prim_ready & otp_rsp_fifo_ready;
           Tests:       T1 T2 T3 
766        1/1            assign otp_prim_valid     = otp_arb_valid & otp_rsp_fifo_ready;
           Tests:       T1 T2 T3 
767        1/1            assign otp_rsp_fifo_valid = otp_prim_ready & otp_prim_valid;
           Tests:       T1 T2 T3 
768                     
769                       prim_otp_pkg::err_e          part_otp_err;
770                       logic [OtpIfWidth-1:0]       part_otp_rdata;
771                       logic                        otp_rvalid;
772                       tlul_pkg::tl_h2d_t           prim_tl_h2d_gated;
773                       tlul_pkg::tl_d2h_t           prim_tl_d2h_gated;
774                     
775                       // Life cycle qualification of TL-UL test interface.
776                       // SEC_CM: TEST.BUS.LC_GATED
777                       // SEC_CM: TEST_TL_LC_GATE.FSM.SPARSE
778                       tlul_lc_gate #(
779                         .NumGatesPerDirection(2)
780                       ) u_tlul_lc_gate (
781                         .clk_i,
782                         .rst_ni,
783                         .tl_h2d_i(prim_tl_i),
784                         .tl_d2h_o(prim_tl_o),
785                         .tl_h2d_o(prim_tl_h2d_gated),
786                         .tl_d2h_i(prim_tl_d2h_gated),
787                         .lc_en_i (lc_dft_en[0]),
788                         .flush_req_i('0),
789                         .flush_ack_o(),
790                         .resp_pending_o(),
791                         .err_o   (intg_error[2])
792                       );
793                     
794                       // Test-related GPIOs.
795                       // SEC_CM: TEST.BUS.LC_GATED
796                       logic [OtpTestVectWidth-1:0] otp_test_vect;
797        1/1            assign cio_test_o    = (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[1])) ?
           Tests:       T1 T2 T3 
798                                              otp_test_vect            : '0;
799        1/1            assign cio_test_en_o = (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[2])) ?
           Tests:       T1 T2 T3 
800                                              {OtpTestVectWidth{1'b1}} : '0;
801                     
802                       // SEC_CM: MACRO.MEM.CM, MACRO.MEM.INTEGRITY
803                       prim_otp #(
804                         .Width            ( OtpWidth            ),
805                         .Depth            ( OtpDepth            ),
806                         .SizeWidth        ( OtpSizeWidth        ),
807                         .PwrSeqWidth      ( OtpPwrSeqWidth      ),
808                         .TestCtrlWidth    ( OtpTestCtrlWidth    ),
809                         .TestStatusWidth  ( OtpTestStatusWidth  ),
810                         .TestVectWidth    ( OtpTestVectWidth    ),
811                         .MemInitFile      ( MemInitFile         ),
812                         .VendorTestOffset ( VendorTestOffset    ),
813                         .VendorTestSize   ( VendorTestSize      )
814                       ) u_otp (
815                         .clk_i,
816                         .rst_ni,
817                         // Observability controls to/from AST
818                         .obs_ctrl_i,
819                         .otp_obs_o,
820                         // Power sequencing signals to/from AST
821                         .pwr_seq_o        ( otp_ast_pwr_seq_o.pwr_seq     ),
822                         .pwr_seq_h_i      ( otp_ast_pwr_seq_h_i.pwr_seq_h ),
823                         .ext_voltage_io   ( otp_ext_voltage_h_io          ),
824                         // Test interface
825                         .test_ctrl_i      ( lc_otp_vendor_test_i.ctrl     ),
826                         .test_status_o    ( lc_otp_vendor_test_o.status   ),
827                         .test_vect_o      ( otp_test_vect                 ),
828                         .test_tl_i        ( prim_tl_h2d_gated             ),
829                         .test_tl_o        ( prim_tl_d2h_gated             ),
830                         // Other DFT signals
831                         .scan_en_i,
832                         .scan_rst_ni,
833                         .scanmode_i,
834                         // Alerts
835                         .fatal_alert_o    ( fatal_prim_otp_alert ),
836                         .recov_alert_o    ( recov_prim_otp_alert ),
837                         // Read / Write command interface
838                         .ready_o          ( otp_prim_ready       ),
839                         .valid_i          ( otp_prim_valid       ),
840                         .cmd_i            ( otp_arb_bundle.cmd   ),
841                         .size_i           ( otp_arb_bundle.size  ),
842                         .addr_i           ( otp_arb_bundle.addr  ),
843                         .wdata_i          ( otp_arb_bundle.wdata ),
844                         // Read data out
845                         .valid_o          ( otp_rvalid           ),
846                         .rdata_o          ( part_otp_rdata       ),
847                         .err_o            ( part_otp_err         )
848                       );
849                     
850                       logic otp_fifo_valid;
851                       logic [vbits(NumAgents)-1:0] otp_part_idx;
852                       logic [NumAgents-1:0] part_otp_rvalid;
853                     
854                       // We can have up to two OTP commands in flight, hence we size this to be 2 deep.
855                       // The partitions can unconditionally sink requested data.
856                       prim_fifo_sync #(
857                         .Width(vbits(NumAgents)),
858                         .Depth(2)
859                       ) u_otp_rsp_fifo (
860                         .clk_i,
861                         .rst_ni,
862                         .clr_i    ( 1'b0               ),
863                         .wvalid_i ( otp_rsp_fifo_valid ),
864                         .wready_o ( otp_rsp_fifo_ready ),
865                         .wdata_i  ( otp_arb_idx        ),
866                         .rvalid_o ( otp_fifo_valid     ),
867                         .rready_i ( otp_rvalid         ),
868                         .rdata_o  ( otp_part_idx       ),
869                         .depth_o  (                    ),
870                         .full_o   (                    ),
871                         .err_o    (                    )
872                       );
873                     
874                       // Steer response back to the partition where this request originated.
875                       always_comb begin : p_rvalid
876        1/1              part_otp_rvalid = '0;
           Tests:       T1 T2 T3 
877        1/1              part_otp_rvalid[otp_part_idx] = otp_rvalid & otp_fifo_valid;
           Tests:       T1 T2 T3 
878                       end
879                     
880                       // Note that this must be true by construction.
881                       `ASSERT(OtpRespFifoUnderflow_A, otp_rvalid |-> otp_fifo_valid)
882                     
883                       /////////////////////////////////////////
884                       // Scrambling Datapath and Arbitration //
885                       /////////////////////////////////////////
886                     
887                       // Note: as opposed to the OTP arbitration above, we do not perform cycle-wise arbitration, but
888                       // transaction-wise arbitration. This is implemented using a RR arbiter that acts as a mutex.
889                       // I.e., each agent (e.g. the DAI or a partition) can request a lock on the mutex. Once granted,
890                       // the partition can keep the lock as long as needed for the transaction to complete. The
891                       // partition must yield its lock by deasserting the request signal for the arbiter to proceed.
892                       // Since this scheme does not have built-in preemtion, it must be ensured that the agents
893                       // eventually release their locks for this to be fair.
894                       //
895                       // See also https://docs.opentitan.org/hw/ip/otp_ctrl/doc/index.html#block-diagram for details.
896                       typedef struct packed {
897                         otp_scrmbl_cmd_e             cmd;
898                         digest_mode_e                mode;
899                         logic [ConstSelWidth-1:0]    sel;
900                         logic [ScrmblBlockWidth-1:0] data;
901                         logic                        valid;
902                       } scrmbl_bundle_t;
903                     
904                       logic [NumAgents-1:0]        part_scrmbl_mtx_req, part_scrmbl_mtx_gnt;
905                       scrmbl_bundle_t              part_scrmbl_req_bundle [NumAgents];
906                       scrmbl_bundle_t              scrmbl_req_bundle;
907                       logic [vbits(NumAgents)-1:0] scrmbl_mtx_idx;
908                       logic                        scrmbl_mtx_valid;
909                     
910                       // Note that arbiter decisions do not change when backpressured.
911                       // Hence, the idx_o signal is guaranteed to remain stable until ack'ed.
912                       prim_arbiter_tree #(
913                         .N(NumAgents),
914                         .DW($bits(scrmbl_bundle_t))
915                       ) u_scrmbl_mtx (
916                         .clk_i,
917                         .rst_ni,
918                         .req_chk_i ( 1'b0                   ), // REQ is allowed to go low again without ACK even
919                                                                // during normal operation.
920                         .req_i     ( part_scrmbl_mtx_req    ),
921                         .data_i    ( part_scrmbl_req_bundle ),
922                         .gnt_o     (                        ),
923                         .idx_o     ( scrmbl_mtx_idx         ),
924                         .valid_o   ( scrmbl_mtx_valid       ),
925                         .data_o    ( scrmbl_req_bundle      ),
926                         .ready_i   ( 1'b0                   )
927                       );
928                     
929                       // Since the ready_i signal of the arbiter is statically set to 1'b0 above, we are always in a
930                       // "backpressure" situation, where the RR arbiter will automatically advance the internal RR state
931                       // to give the current winner max priority in subsequent cycles in order to keep the decision
932                       // stable. Rearbitration occurs once the winning agent deasserts its request.
933                       always_comb begin : p_mutex
934        1/1              part_scrmbl_mtx_gnt = '0;
           Tests:       T1 T2 T3 
935        1/1              part_scrmbl_mtx_gnt[scrmbl_mtx_idx] = scrmbl_mtx_valid;
           Tests:       T1 T2 T3 
936                       end
937                     
938                       logic [ScrmblBlockWidth-1:0] part_scrmbl_rsp_data;
939                       logic scrmbl_arb_req_ready, scrmbl_arb_rsp_valid;
940                       logic [NumAgents-1:0] part_scrmbl_req_ready, part_scrmbl_rsp_valid;
941                     
942                       // SEC_CM: SECRET.MEM.SCRAMBLE
943                       // SEC_CM: PART.MEM.DIGEST
944                       otp_ctrl_scrmbl u_otp_ctrl_scrmbl (
945                         .clk_i,
946                         .rst_ni,
947                         .cmd_i         ( scrmbl_req_bundle.cmd       ),
948                         .mode_i        ( scrmbl_req_bundle.mode      ),
949                         .sel_i         ( scrmbl_req_bundle.sel       ),
950                         .data_i        ( scrmbl_req_bundle.data      ),
951                         .valid_i       ( scrmbl_req_bundle.valid     ),
952                         .ready_o       ( scrmbl_arb_req_ready        ),
953                         .data_o        ( part_scrmbl_rsp_data        ),
954                         .valid_o       ( scrmbl_arb_rsp_valid        ),
955                         .escalate_en_i ( lc_escalate_en[NumAgents+1] ),
956                         .fsm_err_o     ( scrmbl_fsm_err              )
957                       );
958                     
959                       // steer back responses
960                       always_comb begin : p_scmrbl_resp
961        1/1              part_scrmbl_req_ready = '0;
           Tests:       T1 T2 T3 
962        1/1              part_scrmbl_rsp_valid = '0;
           Tests:       T1 T2 T3 
963        1/1              part_scrmbl_req_ready[scrmbl_mtx_idx] = scrmbl_arb_req_ready;
           Tests:       T1 T2 T3 
964        1/1              part_scrmbl_rsp_valid[scrmbl_mtx_idx] = scrmbl_arb_rsp_valid;
           Tests:       T1 T2 T3 
965                       end
966                     
967                       /////////////////////////////
968                       // Direct Access Interface //
969                       /////////////////////////////
970                     
971                       logic                           part_init_req;
972                       logic [NumPart-1:0]             part_init_done;
973                       part_access_t [NumPart-1:0]     part_access_dai;
974                     
975                       // The init request comes from the power manager, which lives in the AON clock domain.
976                       logic pwr_otp_req_synced;
977                       prim_flop_2sync #(
978                         .Width(1)
979                       ) u_otp_init_sync (
980                         .clk_i,
981                         .rst_ni,
982                         .d_i ( pwr_otp_i.otp_init ),
983                         .q_o ( pwr_otp_req_synced )
984                       );
985                     
986                       // Register this signal as it has to cross a clock boundary.
987                       logic pwr_otp_rsp_d, pwr_otp_rsp_q;
988        1/1            assign pwr_otp_o.otp_done = pwr_otp_rsp_q;
           Tests:       T1 T2 T3 
989                     
990                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_init_reg
991        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
992        1/1                pwr_otp_rsp_q <= 1'b0;
           Tests:       T1 T2 T3 
993                         end else begin
994        1/1                pwr_otp_rsp_q <= pwr_otp_rsp_d;
           Tests:       T1 T2 T3 
995                         end
996                       end
997                     
998                       otp_ctrl_dai u_otp_ctrl_dai (
999                         .clk_i,
1000                        .rst_ni,
1001                        .init_req_i       ( pwr_otp_req_synced                    ),
1002                        .init_done_o      ( pwr_otp_rsp_d                         ),
1003                        .part_init_req_o  ( part_init_req                         ),
1004                        .part_init_done_i ( part_init_done                        ),
1005                        .escalate_en_i    ( lc_escalate_en[DaiIdx]                ),
1006                        .error_o          ( part_error[DaiIdx]                    ),
1007                        .fsm_err_o        ( part_fsm_err[DaiIdx]                  ),
1008                        .part_access_i    ( part_access_dai                       ),
1009                        .dai_addr_i       ( dai_addr                              ),
1010                        .dai_cmd_i        ( dai_cmd                               ),
1011                        .dai_req_i        ( dai_req                               ),
1012                        .dai_wdata_i      ( dai_wdata                             ),
1013                        .dai_idle_o       ( dai_idle                              ),
1014                        .dai_prog_idle_o  ( dai_prog_idle                         ),
1015                        .dai_cmd_done_o   ( otp_operation_done                    ),
1016                        .dai_rdata_o      ( dai_rdata                             ),
1017                        .otp_req_o        ( part_otp_arb_req[DaiIdx]              ),
1018                        .otp_cmd_o        ( part_otp_arb_bundle[DaiIdx].cmd       ),
1019                        .otp_size_o       ( part_otp_arb_bundle[DaiIdx].size      ),
1020                        .otp_wdata_o      ( part_otp_arb_bundle[DaiIdx].wdata     ),
1021                        .otp_addr_o       ( part_otp_arb_bundle[DaiIdx].addr      ),
1022                        .otp_gnt_i        ( part_otp_arb_gnt[DaiIdx]              ),
1023                        .otp_rvalid_i     ( part_otp_rvalid[DaiIdx]               ),
1024                        .otp_rdata_i      ( part_otp_rdata                        ),
1025                        .otp_err_i        ( part_otp_err                          ),
1026                        .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[DaiIdx]           ),
1027                        .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[DaiIdx]           ),
1028                        .scrmbl_cmd_o     ( part_scrmbl_req_bundle[DaiIdx].cmd    ),
1029                        .scrmbl_mode_o    ( part_scrmbl_req_bundle[DaiIdx].mode   ),
1030                        .scrmbl_sel_o     ( part_scrmbl_req_bundle[DaiIdx].sel    ),
1031                        .scrmbl_data_o    ( part_scrmbl_req_bundle[DaiIdx].data   ),
1032                        .scrmbl_valid_o   ( part_scrmbl_req_bundle[DaiIdx].valid  ),
1033                        .scrmbl_ready_i   ( part_scrmbl_req_ready[DaiIdx]         ),
1034                        .scrmbl_valid_i   ( part_scrmbl_rsp_valid[DaiIdx]         ),
1035                        .scrmbl_data_i    ( part_scrmbl_rsp_data                  )
1036                      );
1037                    
1038                      ////////////////////////////////////
1039                      // Lifecycle Transition Interface //
1040                      ////////////////////////////////////
1041                    
1042                      logic [PartInfo[LifeCycleIdx].size-1:0][7:0] lc_otp_program_data;
1043       1/1            assign lc_otp_program_data[LcStateOffset-LifeCycleOffset +: LcStateSize] =
           Tests:       T2 T4 T9 
1044                          lc_otp_program_i.state;
1045       1/1            assign lc_otp_program_data[LcTransitionCntOffset-LifeCycleOffset +: LcTransitionCntSize] =
           Tests:       T2 T4 T9 
1046                          lc_otp_program_i.count;
1047                    
1048                      otp_ctrl_lci #(
1049                        .Info(PartInfo[LifeCycleIdx])
1050                      ) u_otp_ctrl_lci (
1051                        .clk_i,
1052                        .rst_ni,
1053                        .lci_en_i         ( pwr_otp_o.otp_done                ),
1054                        .escalate_en_i    ( lc_escalate_en[LciIdx]            ),
1055                        .error_o          ( part_error[LciIdx]                ),
1056                        .fsm_err_o        ( part_fsm_err[LciIdx]              ),
1057                        .lci_prog_idle_o  ( lci_prog_idle                     ),
1058                        .lc_req_i         ( lc_otp_program_i.req              ),
1059                        .lc_data_i        ( lc_otp_program_data               ),
1060                        .lc_ack_o         ( lc_otp_program_o.ack              ),
1061                        .lc_err_o         ( lc_otp_program_o.err              ),
1062                        .otp_req_o        ( part_otp_arb_req[LciIdx]          ),
1063                        .otp_cmd_o        ( part_otp_arb_bundle[LciIdx].cmd   ),
1064                        .otp_size_o       ( part_otp_arb_bundle[LciIdx].size  ),
1065                        .otp_wdata_o      ( part_otp_arb_bundle[LciIdx].wdata ),
1066                        .otp_addr_o       ( part_otp_arb_bundle[LciIdx].addr  ),
1067                        .otp_gnt_i        ( part_otp_arb_gnt[LciIdx]          ),
1068                        .otp_rvalid_i     ( part_otp_rvalid[LciIdx]           ),
1069                        .otp_rdata_i      ( part_otp_rdata                    ),
1070                        .otp_err_i        ( part_otp_err                      )
1071                      );
1072                    
1073                      // Tie off unused connections.
1074                      assign part_scrmbl_mtx_req[LciIdx]    = '0;
1075                      assign part_scrmbl_req_bundle[LciIdx] = '0;
1076                    
1077                      // This stops lint from complaining about unused signals.
1078                      logic unused_lci_scrmbl_sigs;
1079       0/1     ==>    assign unused_lci_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[LciIdx],
1080                                                        part_scrmbl_req_ready[LciIdx],
1081                                                        part_scrmbl_rsp_valid[LciIdx]};
1082                    
1083                      ////////////////////////////////////
1084                      // Key Derivation Interface (KDI) //
1085                      ////////////////////////////////////
1086                    
1087                      logic scrmbl_key_seed_valid;
1088                      logic [SramKeySeedWidth-1:0] sram_data_key_seed;
1089                      logic [FlashKeySeedWidth-1:0] flash_data_key_seed, flash_addr_key_seed;
1090                    
1091                      otp_ctrl_kdi #(
1092                        .RndCnstScrmblKeyInit(RndCnstScrmblKeyInit)
1093                      ) u_otp_ctrl_kdi (
1094                        .clk_i,
1095                        .rst_ni,
1096                        .kdi_en_i                ( pwr_otp_o.otp_done      ),
1097                        .escalate_en_i           ( lc_escalate_en[KdiIdx]  ),
1098                        .fsm_err_o               ( part_fsm_err[KdiIdx]    ),
1099                        .scrmbl_key_seed_valid_i ( scrmbl_key_seed_valid   ),
1100                        .flash_data_key_seed_i   ( flash_data_key_seed     ),
1101                        .flash_addr_key_seed_i   ( flash_addr_key_seed     ),
1102                        .sram_data_key_seed_i    ( sram_data_key_seed      ),
1103                        .edn_req_o               ( key_edn_req             ),
1104                        .edn_ack_i               ( key_edn_ack             ),
1105                        .edn_data_i              ( edn_data                ),
1106                        .flash_otp_key_i,
1107                        .flash_otp_key_o,
1108                        .sram_otp_key_i,
1109                        .sram_otp_key_o,
1110                        .otbn_otp_key_i,
1111                        .otbn_otp_key_o,
1112                        .scrmbl_mtx_req_o        ( part_scrmbl_mtx_req[KdiIdx]          ),
1113                        .scrmbl_mtx_gnt_i        ( part_scrmbl_mtx_gnt[KdiIdx]          ),
1114                        .scrmbl_cmd_o            ( part_scrmbl_req_bundle[KdiIdx].cmd   ),
1115                        .scrmbl_mode_o           ( part_scrmbl_req_bundle[KdiIdx].mode  ),
1116                        .scrmbl_sel_o            ( part_scrmbl_req_bundle[KdiIdx].sel   ),
1117                        .scrmbl_data_o           ( part_scrmbl_req_bundle[KdiIdx].data  ),
1118                        .scrmbl_valid_o          ( part_scrmbl_req_bundle[KdiIdx].valid ),
1119                        .scrmbl_ready_i          ( part_scrmbl_req_ready[KdiIdx]        ),
1120                        .scrmbl_valid_i          ( part_scrmbl_rsp_valid[KdiIdx]        ),
1121                        .scrmbl_data_i           ( part_scrmbl_rsp_data                 )
1122                      );
1123                    
1124                      // Tie off OTP bus access, since this is not needed.
1125                      assign part_otp_arb_req[KdiIdx] = 1'b0;
1126                      assign part_otp_arb_bundle[KdiIdx] = '0;
1127                    
1128                      // This stops lint from complaining about unused signals.
1129                      logic unused_kdi_otp_sigs;
1130       0/1     ==>    assign unused_kdi_otp_sigs = ^{part_otp_arb_gnt[KdiIdx],
1131                                                     part_otp_rvalid[KdiIdx]};
1132                    
1133                      /////////////////////////
1134                      // Partition Instances //
1135                      /////////////////////////
1136                    
1137                      logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data;
1138                    
1139                      for (genvar k = 0; k < NumPart; k ++) begin : gen_partitions
1140                        ////////////////////////////////////////////////////////////////////////////////////////////////
1141                        if (PartInfo[k].variant == Unbuffered) begin : gen_unbuffered
1142                          otp_ctrl_part_unbuf #(
1143                            .Info(PartInfo[k])
1144                          ) u_part_unbuf (
1145                            .clk_i,
1146                            .rst_ni,
1147                            .init_req_i    ( part_init_req                ),
1148                            .init_done_o   ( part_init_done[k]            ),
1149                            .escalate_en_i ( lc_escalate_en[k]            ),
1150                            .error_o       ( part_error[k]                ),
1151                            .fsm_err_o     ( part_fsm_err[k]              ),
1152                            .access_i      ( part_access[k]               ),
1153                            .access_o      ( part_access_dai[k]           ),
1154                            .digest_o      ( part_digest[k]               ),
1155                            .tlul_req_i    ( part_tlul_req[k]             ),
1156                            .tlul_gnt_o    ( part_tlul_gnt[k]             ),
1157                            .tlul_addr_i   ( part_tlul_addr               ),
1158                            .tlul_rerror_o ( part_tlul_rerror[k]          ),
1159                            .tlul_rvalid_o ( part_tlul_rvalid[k]          ),
1160                            .tlul_rdata_o  ( part_tlul_rdata[k]           ),
1161                            .otp_req_o     ( part_otp_arb_req[k]          ),
1162                            .otp_cmd_o     ( part_otp_arb_bundle[k].cmd   ),
1163                            .otp_size_o    ( part_otp_arb_bundle[k].size  ),
1164                            .otp_wdata_o   ( part_otp_arb_bundle[k].wdata ),
1165                            .otp_addr_o    ( part_otp_arb_bundle[k].addr  ),
1166                            .otp_gnt_i     ( part_otp_arb_gnt[k]          ),
1167                            .otp_rvalid_i  ( part_otp_rvalid[k]           ),
1168                            .otp_rdata_i   ( part_otp_rdata               ),
1169                            .otp_err_i     ( part_otp_err                 )
1170                          );
1171                    
1172                          // Tie off unused connections.
1173                          assign part_scrmbl_mtx_req[k]    = '0;
1174                          assign part_scrmbl_req_bundle[k] = '0;
1175                          // These checks do not exist in this partition type,
1176                          // so we always acknowledge the request.
1177                          assign integ_chk_ack[k]          = 1'b1;
1178                          assign cnsty_chk_ack[k]          = 1'b1;
1179                    
1180                          // No buffered data to expose.
1181                          assign part_buf_data[PartInfo[k].offset +: PartInfo[k].size] = '0;
1182                    
1183                          // This stops lint from complaining about unused signals.
1184                          logic unused_part_scrmbl_sigs;
1185       5/5                assign unused_part_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[k],
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
1186                                                             part_scrmbl_req_ready[k],
1187                                                             part_scrmbl_rsp_valid[k],
1188                                                             integ_chk_req[k],
1189                                                             cnsty_chk_req[k]};
1190                    
1191                          // Alert assertion for sparse FSM.
1192                          `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartUnbufFsmCheck_A,
1193                              u_part_unbuf.u_state_regs, alert_tx_o[1])
1194                        ////////////////////////////////////////////////////////////////////////////////////////////////
1195                        end else if (PartInfo[k].variant == Buffered) begin : gen_buffered
1196                          otp_ctrl_part_buf #(
1197                            .Info(PartInfo[k]),
1198                            .DataDefault(PartInvDefault[PartInfo[k].offset*8 +: PartInfo[k].size*8])
1199                          ) u_part_buf (
1200                            .clk_i,
1201                            .rst_ni,
1202                            .init_req_i        ( part_init_req                   ),
1203                            .init_done_o       ( part_init_done[k]               ),
1204                            .integ_chk_req_i   ( integ_chk_req[k]                ),
1205                            .integ_chk_ack_o   ( integ_chk_ack[k]                ),
1206                            .cnsty_chk_req_i   ( cnsty_chk_req[k]                ),
1207                            .cnsty_chk_ack_o   ( cnsty_chk_ack[k]                ),
1208                            .escalate_en_i     ( lc_escalate_en[k]               ),
1209                            // Only supported by life cycle partition (see further below).
1210                            .check_byp_en_i    ( lc_ctrl_pkg::Off                ),
1211                            .error_o           ( part_error[k]                   ),
1212                            .fsm_err_o         ( part_fsm_err[k]                 ),
1213                            .access_i          ( part_access[k]                  ),
1214                            .access_o          ( part_access_dai[k]              ),
1215                            .digest_o          ( part_digest[k]                  ),
1216                            .data_o            ( part_buf_data[PartInfo[k].offset +: PartInfo[k].size] ),
1217                            .otp_req_o         ( part_otp_arb_req[k]             ),
1218                            .otp_cmd_o         ( part_otp_arb_bundle[k].cmd      ),
1219                            .otp_size_o        ( part_otp_arb_bundle[k].size     ),
1220                            .otp_wdata_o       ( part_otp_arb_bundle[k].wdata    ),
1221                            .otp_addr_o        ( part_otp_arb_bundle[k].addr     ),
1222                            .otp_gnt_i         ( part_otp_arb_gnt[k]             ),
1223                            .otp_rvalid_i      ( part_otp_rvalid[k]              ),
1224                            .otp_rdata_i       ( part_otp_rdata                  ),
1225                            .otp_err_i         ( part_otp_err                    ),
1226                            .scrmbl_mtx_req_o  ( part_scrmbl_mtx_req[k]          ),
1227                            .scrmbl_mtx_gnt_i  ( part_scrmbl_mtx_gnt[k]          ),
1228                            .scrmbl_cmd_o      ( part_scrmbl_req_bundle[k].cmd   ),
1229                            .scrmbl_mode_o     ( part_scrmbl_req_bundle[k].mode  ),
1230                            .scrmbl_sel_o      ( part_scrmbl_req_bundle[k].sel   ),
1231                            .scrmbl_data_o     ( part_scrmbl_req_bundle[k].data  ),
1232                            .scrmbl_valid_o    ( part_scrmbl_req_bundle[k].valid ),
1233                            .scrmbl_ready_i    ( part_scrmbl_req_ready[k]        ),
1234                            .scrmbl_valid_i    ( part_scrmbl_rsp_valid[k]        ),
1235                            .scrmbl_data_i     ( part_scrmbl_rsp_data            )
1236                          );
1237                    
1238                          // Buffered partitions are not accessible via the TL-UL window.
1239                          logic unused_part_tlul_sigs;
1240       0/5     ==>        assign unused_part_tlul_sigs = ^part_tlul_req[k];
1241                          assign part_tlul_gnt[k]    = 1'b0;
1242                          assign part_tlul_rerror[k] = '0;
1243                          assign part_tlul_rvalid[k] = 1'b0;
1244                          assign part_tlul_rdata[k]  = '0;
1245                    
1246                          // Alert assertion for sparse FSM.
1247                          `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartBufFsmCheck_A,
1248                              u_part_buf.u_state_regs, alert_tx_o[1])
1249                          `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntPartBufCheck_A,
1250                              u_part_buf.u_prim_count, alert_tx_o[1])
1251                        ////////////////////////////////////////////////////////////////////////////////////////////////
1252                        end else if (PartInfo[k].variant == LifeCycle) begin : gen_lifecycle
1253                          otp_ctrl_part_buf #(
1254                            .Info(PartInfo[k]),
1255                            .DataDefault(PartInvDefault[PartInfo[k].offset*8 +: PartInfo[k].size*8])
1256                          ) u_part_buf (
1257                            .clk_i,
1258                            .rst_ni,
1259                            .init_req_i        ( part_init_req                   ),
1260                            .init_done_o       ( part_init_done[k]               ),
1261                            .integ_chk_req_i   ( integ_chk_req[k]                ),
1262                            .integ_chk_ack_o   ( integ_chk_ack[k]                ),
1263                            .cnsty_chk_req_i   ( cnsty_chk_req[k]                ),
1264                            .cnsty_chk_ack_o   ( cnsty_chk_ack[k]                ),
1265                            .escalate_en_i     ( lc_escalate_en[k]               ),
1266                            // This is only supported by the life cycle partition. We need to prevent this partition
1267                            // from escalating once the life cycle state in memory is being updated (and hence not
1268                            // consistent with the values in the buffer regs anymore).
1269                            .check_byp_en_i    ( lc_check_byp_en                 ),
1270                            .error_o           ( part_error[k]                   ),
1271                            .fsm_err_o         ( part_fsm_err[k]                 ),
1272                            .access_i          ( part_access[k]                  ),
1273                            .access_o          ( part_access_dai[k]              ),
1274                            .digest_o          ( part_digest[k]                  ),
1275                            .data_o            ( part_buf_data[PartInfo[k].offset +: PartInfo[k].size] ),
1276                            .otp_req_o         ( part_otp_arb_req[k]             ),
1277                            .otp_cmd_o         ( part_otp_arb_bundle[k].cmd      ),
1278                            .otp_size_o        ( part_otp_arb_bundle[k].size     ),
1279                            .otp_wdata_o       ( part_otp_arb_bundle[k].wdata    ),
1280                            .otp_addr_o        ( part_otp_arb_bundle[k].addr     ),
1281                            .otp_gnt_i         ( part_otp_arb_gnt[k]             ),
1282                            .otp_rvalid_i      ( part_otp_rvalid[k]              ),
1283                            .otp_rdata_i       ( part_otp_rdata                  ),
1284                            .otp_err_i         ( part_otp_err                    ),
1285                            // The LC partition does not need any scrambling features.
1286                            .scrmbl_mtx_req_o  (                                 ),
1287                            .scrmbl_mtx_gnt_i  ( 1'b0                            ),
1288                            .scrmbl_cmd_o      (                                 ),
1289                            .scrmbl_mode_o     (                                 ),
1290                            .scrmbl_sel_o      (                                 ),
1291                            .scrmbl_data_o     (                                 ),
1292                            .scrmbl_valid_o    (                                 ),
1293                            .scrmbl_ready_i    ( 1'b0                            ),
1294                            .scrmbl_valid_i    ( 1'b0                            ),
1295                            .scrmbl_data_i     ( '0                              )
1296                          );
1297                    
1298                          // Buffered partitions are not accessible via the TL-UL window.
1299                          logic unused_part_tlul_sigs;
1300       0/1     ==>        assign unused_part_tlul_sigs = ^part_tlul_req[k];
1301                          assign part_tlul_gnt[k]    = 1'b0;
1302                          assign part_tlul_rerror[k] = '0;
1303                          assign part_tlul_rvalid[k] = 1'b0;
1304                          assign part_tlul_rdata[k]  = '0;
1305                    
1306                          // Tie off unused connections.
1307                          assign part_scrmbl_mtx_req[k]    = '0;
1308                          assign part_scrmbl_req_bundle[k] = '0;
1309                    
1310                          // This stops lint from complaining about unused signals.
1311                          logic unused_part_scrmbl_sigs;
1312       0/1     ==>        assign unused_part_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[k],
1313                                                             part_scrmbl_req_ready[k],
1314                                                             part_scrmbl_rsp_valid[k]};
1315                          // Alert assertion for sparse FSM.
1316                          `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartLcFsmCheck_A,
1317                              u_part_buf.u_state_regs, alert_tx_o[1])
1318                          `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntPartLcCheck_A,
1319                              u_part_buf.u_prim_count, alert_tx_o[1])
1320                        ////////////////////////////////////////////////////////////////////////////////////////////////
1321                        end else begin : gen_invalid
1322                          // This is invalid and should break elaboration
1323                          assert_static_in_generate_invalid assert_static_in_generate_invalid();
1324                        end
1325                        ////////////////////////////////////////////////////////////////////////////////////////////////
1326                      end
1327                    
1328                      //////////////////////////////////
1329                      // Buffered Data Output Mapping //
1330                      //////////////////////////////////
1331                    
1332                      // Output complete hardware config partition.
1333                      // Actual mapping to other IPs is done via the intersignal topgen feature,
1334                      // selection of fields can be done using the otp_hw_cfg_t struct fields.
1335                      otp_broadcast_t otp_broadcast;
1336       1/1            assign otp_broadcast = named_broadcast_assign(part_init_done, part_buf_data);
           Tests:       T1 T2 T3 
1337                    
1338                      // Make sure the broadcast valid is flopped before sending it out.
1339                      lc_ctrl_pkg::lc_tx_t otp_broadcast_valid_q;
1340                      prim_lc_sender u_prim_lc_sender_otp_broadcast_valid (
1341                        .clk_i,
1342                        .rst_ni,
1343                        .lc_en_i(otp_broadcast.valid),
1344                        .lc_en_o(otp_broadcast_valid_q)
1345                      );
1346                    
1347                      always_comb begin : p_otp_broadcast_valid
1348       1/1              otp_broadcast_o       = otp_broadcast;
           Tests:       T1 T2 T3 
1349       1/1              otp_broadcast_o.valid = otp_broadcast_valid_q;
           Tests:       T1 T2 T3 
1350                      end
1351                    
1352                      // Root keys and seeds.
1353                      // This uses a generated function to assign all collateral that is marked with "iskeymgr" in
1354                      // the memory map. Note that in this case the type is static and represents a superset of all
1355                      // options so that we can maintain a stable interface with keymgr (otherwise keymgr will have
1356                      // to be templated as well. Unused key material will be tied off to '0. The keymgr has to be
1357                      // parameterized accordingly (via SV parameters) to consume the correct key material.
1358                      //
1359                      // The key material valid signals are set to true if the corresponding digest is nonzero and the
1360                      // partition is initialized. On top of that, the entire output is gated by lc_seed_hw_rd_en.
1361                      otp_keymgr_key_t otp_keymgr_key;
1362       1/1            assign otp_keymgr_key = named_keymgr_key_assign(part_digest,
           Tests:       T1 T2 T3 
1363                                                                      part_buf_data,
1364                                                                      lc_seed_hw_rd_en);
1365                    
1366                      // Note regarding these breakouts: named_keymgr_key_assign will tie off unused key material /
1367                      // valid signals to '0. This is the case for instance in system configurations that keep the seed
1368                      // material in the flash instead of OTP.
1369                      logic creator_root_key_share0_valid_d, creator_root_key_share0_valid_q;
1370                      logic creator_root_key_share1_valid_d, creator_root_key_share1_valid_q;
1371                      logic creator_seed_valid_d, creator_seed_valid_q;
1372                      logic owner_seed_valid_d, owner_seed_valid_q;
1373                      prim_flop #(
1374                        .Width(4)
1375                      ) u_keygmr_key_valid (
1376                        .clk_i,
1377                        .rst_ni,
1378                        .d_i ({creator_root_key_share0_valid_d,
1379                               creator_root_key_share1_valid_d,
1380                               creator_seed_valid_d,
1381                               owner_seed_valid_d}),
1382                        .q_o ({creator_root_key_share0_valid_q,
1383                               creator_root_key_share1_valid_q,
1384                               creator_seed_valid_q,
1385                               owner_seed_valid_q})
1386                      );
1387                    
1388                      always_comb begin : p_otp_keymgr_key_valid
1389                        // Valid reg inputs
1390       1/1              creator_root_key_share0_valid_d = otp_keymgr_key.creator_root_key_share0_valid;
           Tests:       T1 T2 T3 
1391       1/1              creator_root_key_share1_valid_d = otp_keymgr_key.creator_root_key_share1_valid;
           Tests:       T1 T2 T3 
1392       1/1              creator_seed_valid_d            = otp_keymgr_key.creator_seed_valid;
           Tests:       T1 T2 T3 
1393       1/1              owner_seed_valid_d              = otp_keymgr_key.owner_seed_valid;
           Tests:       T1 T2 T3 
1394                        // Output to keymgr
1395       1/1              otp_keymgr_key_o                               = otp_keymgr_key;
           Tests:       T1 T2 T3 
1396       1/1              otp_keymgr_key_o.creator_root_key_share0_valid = creator_root_key_share0_valid_q;
           Tests:       T1 T2 T3 
1397       1/1              otp_keymgr_key_o.creator_root_key_share1_valid = creator_root_key_share1_valid_q;
           Tests:       T1 T2 T3 
1398       1/1              otp_keymgr_key_o.creator_seed_valid            = creator_seed_valid_q;
           Tests:       T1 T2 T3 
1399       1/1              otp_keymgr_key_o.owner_seed_valid              = owner_seed_valid_q;
           Tests:       T1 T2 T3 
1400                      end
1401                    
1402                      // Check that the lc_seed_hw_rd_en remains stable, once the key material is valid.
1403                      `ASSERT(LcSeedHwRdEnStable0_A,
1404                        $rose(creator_root_key_share0_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$],
1405                        clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating
1406                      )
1407                      `ASSERT(LcSeedHwRdEnStable1_A,
1408                        $rose(creator_root_key_share1_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$],
1409                        clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating
1410                      )
1411                      `ASSERT(LcSeedHwRdEnStable2_A,
1412                        $rose(creator_seed_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$],
1413                        clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating
1414                      )
1415                      `ASSERT(LcSeedHwRdEnStable3_A,
1416                        $rose(owner_seed_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$],
1417                        clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating
1418                      )
1419                    
1420                      // Scrambling Keys
1421       1/1            assign scrmbl_key_seed_valid = part_digest[Secret1Idx] != '0;
           Tests:       T1 T2 T3 
1422       1/1            assign sram_data_key_seed    = part_buf_data[SramDataKeySeedOffset +:
           Tests:       T1 T2 T3 
1423                                                                   SramDataKeySeedSize];
1424       1/1            assign flash_data_key_seed   = part_buf_data[FlashDataKeySeedOffset +:
           Tests:       T1 T2 T3 
1425                                                                   FlashDataKeySeedSize];
1426       1/1            assign flash_addr_key_seed   = part_buf_data[FlashAddrKeySeedOffset +:
           Tests:       T1 T2 T3 
1427                                                                   FlashAddrKeySeedSize];
1428                    
1429                      // Test unlock and exit tokens and RMA token
1430       1/1            assign otp_lc_data_o.test_exit_token   = part_buf_data[TestExitTokenOffset +:
           Tests:       T1 T2 T3 
1431                                                                             TestExitTokenSize];
1432       1/1            assign otp_lc_data_o.test_unlock_token = part_buf_data[TestUnlockTokenOffset +:
           Tests:       T1 T2 T3 
1433                                                                             TestUnlockTokenSize];
1434       1/1            assign otp_lc_data_o.rma_token         = part_buf_data[RmaTokenOffset +:
           Tests:       T1 T2 T3 
1435                                                                             RmaTokenSize];
1436                    
1437                      lc_ctrl_pkg::lc_tx_t test_tokens_valid, rma_token_valid, secrets_valid;
1438                      // The test tokens have been provisioned.
1439       1/1            assign test_tokens_valid = (part_digest[Secret0Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
           Tests:       T1 T2 T3 
1440                      // The rma token has been provisioned.
1441       1/1            assign rma_token_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
           Tests:       T1 T2 T3 
1442                      // The device is personalized if the root key has been provisioned and locked.
1443       1/1            assign secrets_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
           Tests:       T1 T2 T3 
1444                    
1445                      // Buffer these constants in order to ensure that synthesis does not try to optimize the encoding.
1446                      // SEC_CM: TOKEN_VALID.CTRL.MUBI
1447                      prim_lc_sender #(
1448                        .AsyncOn(0)
1449                      ) u_prim_lc_sender_test_tokens_valid (
1450                        .clk_i,
1451                        .rst_ni,
1452                        .lc_en_i(test_tokens_valid),
1453                        .lc_en_o(otp_lc_data_o.test_tokens_valid)
1454                      );
1455                    
1456                      prim_lc_sender #(
1457                        .AsyncOn(0)
1458                      ) u_prim_lc_sender_rma_token_valid (
1459                        .clk_i,
1460                        .rst_ni,
1461                        .lc_en_i(rma_token_valid),
1462                        .lc_en_o(otp_lc_data_o.rma_token_valid)
1463                      );
1464                    
1465                      prim_lc_sender #(
1466                        .AsyncOn(0)
1467                      ) u_prim_lc_sender_secrets_valid (
1468                        .clk_i,
1469                        .rst_ni,
1470                        .lc_en_i(secrets_valid),
1471                        .lc_en_o(otp_lc_data_o.secrets_valid)
1472                      );
1473                    
1474                      // Lifecycle state
1475       1/1            assign otp_lc_data_o.state = lc_ctrl_state_pkg::lc_state_e'(part_buf_data[LcStateOffset +:
           Tests:       T1 T2 T3 
1476                                                                                                LcStateSize]);
1477       1/1            assign otp_lc_data_o.count = lc_ctrl_state_pkg::lc_cnt_e'(part_buf_data[LcTransitionCntOffset +:
           Tests:       T1 T2 T3 
1478                                                                                              LcTransitionCntSize]);
1479                    
1480                      // Assert life cycle state valid signal only when all partitions have initialized.
1481       1/1            assign otp_lc_data_o.valid    = &part_init_done;
           Tests:       T1 T2 T3 
1482                      // Signal whether there are any errors in the life cycle partition (both correctable and
1483                      // uncorrectable ones). This bit is made available via the JTAG TAP, which is useful for
1484                      // production testing in RAW life cycle state where the OTP regs are not accessible.
1485       1/1            assign otp_lc_data_o.error    = |part_error[LifeCycleIdx];
           Tests:       T1 T2 T3 
1486                    
1487                      // Not all bits of part_buf_data are used here.
1488                      logic unused_buf_data;
1489       1/1            assign unused_buf_data = ^part_buf_data;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	105	100	95.24
Logical	105	100	95.24
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00110110000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b10001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T2,T3,T4

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11001111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[8].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[9].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       253
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd))
             -------------------1------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR
1	1	Covered	T14,T15,T16

 LINE       288
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       297
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T2,T3,T4

 LINE       298
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T2,T3,T4

 LINE       382
 EXPRESSION ((reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q))) ? 1'b0 : direct_access_regwen_q)
             -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       382
 SUB-EXPRESSION (reg2hw.direct_access_regwen.qe && ((!reg2hw.direct_access_regwen.q)))
                 ---------------1--------------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       386
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Excluded		VC_COV_UNR
1	0	0	Excluded		VC_COV_UNR

 LINE       403
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       436
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Excluded		VC_COV_UNR

 LINE       445
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       449
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T68,T55

 LINE       469
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T44,T35
1	0	Covered	T3,T68,T55

 LINE       478
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T3,T44,T68
0	0	1	0	Covered	T26,T27,T28
0	1	0	0	Covered	T26,T27,T28
1	0	0	0	Covered	T35,T51,T55

 LINE       527
 EXPRESSION (direct_access_regwen_q & dai_idle)
             -----------1----------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       593
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T17,T18

 LINE       640
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T9,T5

 LINE       642
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T9,T5

 LINE       765
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       766
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       767
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       877
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       1421
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T97,T24

 LINE       1439
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T44,T97

 LINE       1439
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T44,T97

 LINE       1441
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T97

 LINE       1441
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T97

 LINE       1443
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T97

 LINE       1443
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T97

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	149	142	95.30
Total Bits	9984	9714	97.30
Total Bits 0->1	4992	4857	97.30
Total Bits 1->0	4992	4857	97.30

Ports	149	142	95.30
Port Bits	9984	9714	97.30
Port Bits 0->1	4992	4857	97.30
Port Bits 1->0	4992	4857	97.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
edn_o.edn_req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
edn_i.edn_fips	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
edn_i.edn_ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
core_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T24,T55	Yes	T2,T24,T55	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T4,T9,T35	Yes	T4,T9,T35	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T9,T12,T94	Yes	T1,T9,T10	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T9,T10,T12	Yes	T9,T12,T94	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T1,T9,T12	Yes	T9,T10,T12	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T9,T12,T94	Yes	T1,T9,T12	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T2,T4,T9	Yes	T1,T2,T4	INPUT
prim_tl_i.a_valid	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
prim_tl_o.a_ready	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
prim_tl_o.d_error	Yes	Yes	T11,T17,T18	Yes	T19,T20,T21	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T4,*T9	Yes	T2,T4,T9	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T11,T17,T18	Yes	T19,T20,T21	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T2,*T4,*T9	Yes	T2,T4,T9	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	OUTPUT
intr_otp_error_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T11,T17	Yes	T3,T11,T17	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T11,T17	Yes	T3,T11,T17	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T11,T17,T18	Yes	T11,T17,T18	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T4,T12,T97	Yes	T2,T9,T5	INPUT
pwr_otp_i.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[383:0]	Yes	Yes	T186,T230,T236	Yes	T237,T238,T239	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T14,T238,T239	Yes	T184,T186,T236	INPUT
lc_otp_program_i.req	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
lc_otp_program_o.ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
lc_otp_program_o.err	Yes	Yes	T184,T186,T230	Yes	T184,T186,T230	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T4,T9,T35	Yes	T4,T35,T51	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T4,T9,T35	Yes	T4,T9,T35	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T2,T3,T4	Yes	T4,T9,T5	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T3,T4,T97	Yes	T2,T4,T9	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T9,T94,T100	Yes	T9,T94,T100	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T4,T97,T51	Yes	T2,T4,T97	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T4,T44,T97	Yes	T4,T44,T97	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T4,T97,T51	Yes	T2,T4,T97	OUTPUT
otp_lc_data_o.count[1:0]	No	No		No		OUTPUT
otp_lc_data_o.count[4:2]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[5]	No	No		No		OUTPUT
otp_lc_data_o.count[10:6]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[11]	No	No		No		OUTPUT
otp_lc_data_o.count[12]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[13]	No	No		No		OUTPUT
otp_lc_data_o.count[16:14]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[18:17]	No	No		No		OUTPUT
otp_lc_data_o.count[44:19]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[45]	No	No		No		OUTPUT
otp_lc_data_o.count[46]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[47]	No	No		No		OUTPUT
otp_lc_data_o.count[53:48]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[54]	No	No		No		OUTPUT
otp_lc_data_o.count[55]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[56]	No	No		No		OUTPUT
otp_lc_data_o.count[57]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[58]	No	No		No		OUTPUT
otp_lc_data_o.count[70:59]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[71]	No	No		No		OUTPUT
otp_lc_data_o.count[74:72]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[75]	No	No		No		OUTPUT
otp_lc_data_o.count[79:76]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[80]	No	No		No		OUTPUT
otp_lc_data_o.count[89:81]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[90]	No	No		No		OUTPUT
otp_lc_data_o.count[104:91]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[105]	No	No		No		OUTPUT
otp_lc_data_o.count[125:106]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[126]	No	No		No		OUTPUT
otp_lc_data_o.count[140:127]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[141]	No	No		No		OUTPUT
otp_lc_data_o.count[142]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[148:144]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[149]	No	No		No		OUTPUT
otp_lc_data_o.count[152:150]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[153]	No	No		No		OUTPUT
otp_lc_data_o.count[162:154]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T97	OUTPUT
otp_lc_data_o.count[163]	No	No		No		OUTPUT
otp_lc_data_o.count[164]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[174:166]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T97	OUTPUT
otp_lc_data_o.count[175]	No	No		No		OUTPUT
otp_lc_data_o.count[181:176]	Yes	Yes	T4,*T97,*T51	Yes	T4,T97,T35	OUTPUT
otp_lc_data_o.count[183:182]	No	No		No		OUTPUT
otp_lc_data_o.count[187:184]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[188]	No	No		No		OUTPUT
otp_lc_data_o.count[197:189]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[198]	No	No		No		OUTPUT
otp_lc_data_o.count[201:199]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[202]	No	No		No		OUTPUT
otp_lc_data_o.count[233:203]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[234]	No	No		No		OUTPUT
otp_lc_data_o.count[263:235]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[264]	No	No		No		OUTPUT
otp_lc_data_o.count[270:265]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[271]	No	No		No		OUTPUT
otp_lc_data_o.count[280:272]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[281]	No	No		No		OUTPUT
otp_lc_data_o.count[290:282]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[291]	No	No		No		OUTPUT
otp_lc_data_o.count[303:292]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[304]	No	No		No		OUTPUT
otp_lc_data_o.count[306:305]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[307]	No	No		No		OUTPUT
otp_lc_data_o.count[308]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[309]	No	No		No		OUTPUT
otp_lc_data_o.count[317:310]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[319:318]	No	No		No		OUTPUT
otp_lc_data_o.count[333:320]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[334]	No	No		No		OUTPUT
otp_lc_data_o.count[355:335]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[357:356]	No	No		No		OUTPUT
otp_lc_data_o.count[359:358]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[360]	No	No		No		OUTPUT
otp_lc_data_o.count[367:361]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.count[369:368]	No	No		No		OUTPUT
otp_lc_data_o.count[380:370]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.count[381]	No	No		No		OUTPUT
otp_lc_data_o.count[383:382]	Yes	Yes	T4,T5,T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[2:0]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[3]	No	No		No		OUTPUT
otp_lc_data_o.state[12:4]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[15:14]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[17:16]	No	No		No		OUTPUT
otp_lc_data_o.state[28:18]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[29]	No	No		No		OUTPUT
otp_lc_data_o.state[36:30]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[37]	No	No		No		OUTPUT
otp_lc_data_o.state[38]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[39]	No	No		No		OUTPUT
otp_lc_data_o.state[47:40]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[48]	No	No		No		OUTPUT
otp_lc_data_o.state[61:49]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[62]	No	No		No		OUTPUT
otp_lc_data_o.state[69:63]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[70]	No	No		No		OUTPUT
otp_lc_data_o.state[76:71]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[77]	No	No		No		OUTPUT
otp_lc_data_o.state[84:78]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[85]	No	No		No		OUTPUT
otp_lc_data_o.state[88:86]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[89]	No	No		No		OUTPUT
otp_lc_data_o.state[92:90]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[94:93]	No	No		No		OUTPUT
otp_lc_data_o.state[97:95]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[98]	No	No		No		OUTPUT
otp_lc_data_o.state[106:99]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[107]	No	No		No		OUTPUT
otp_lc_data_o.state[108]	Yes	Yes	*T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[109]	No	No		No		OUTPUT
otp_lc_data_o.state[111:110]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[112]	No	No		No		OUTPUT
otp_lc_data_o.state[124:113]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[125]	No	No		No		OUTPUT
otp_lc_data_o.state[138:126]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[139]	No	No		No		OUTPUT
otp_lc_data_o.state[143:140]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[144]	No	No		No		OUTPUT
otp_lc_data_o.state[152:145]	Yes	Yes	T4,T5,*T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[153]	No	No		No		OUTPUT
otp_lc_data_o.state[155:154]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[156]	No	No		No		OUTPUT
otp_lc_data_o.state[161:157]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[163:162]	No	No		No		OUTPUT
otp_lc_data_o.state[183:164]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[184]	No	No		No		OUTPUT
otp_lc_data_o.state[188:185]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[189]	No	No		No		OUTPUT
otp_lc_data_o.state[198:190]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[199]	No	No		No		OUTPUT
otp_lc_data_o.state[203:200]	Yes	Yes	T4,T5,T51	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[204]	No	No		No		OUTPUT
otp_lc_data_o.state[215:205]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[216]	No	No		No		OUTPUT
otp_lc_data_o.state[218:217]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[220:219]	No	No		No		OUTPUT
otp_lc_data_o.state[235:221]	Yes	Yes	T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[236]	No	No		No		OUTPUT
otp_lc_data_o.state[252:237]	Yes	Yes	T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[253]	No	No		No		OUTPUT
otp_lc_data_o.state[269:254]	Yes	Yes	T4,*T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[270]	No	No		No		OUTPUT
otp_lc_data_o.state[274:271]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[275]	No	No		No		OUTPUT
otp_lc_data_o.state[278:276]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[279]	No	No		No		OUTPUT
otp_lc_data_o.state[283:280]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[284]	No	No		No		OUTPUT
otp_lc_data_o.state[287:285]	Yes	Yes	T4,T5,*T97	Yes	T4,T5,T12	OUTPUT
otp_lc_data_o.state[288]	No	No		No		OUTPUT
otp_lc_data_o.state[307:289]	Yes	Yes	T4,*T98,*T133	Yes	T4,T35,T98	OUTPUT
otp_lc_data_o.state[308]	No	No		No		OUTPUT
otp_lc_data_o.state[315:309]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[316]	No	No		No		OUTPUT
otp_lc_data_o.state[317]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.state[318]	No	No		No		OUTPUT
otp_lc_data_o.state[319]	Yes	Yes	T4,T133,T19	Yes	T4,T133,T19	OUTPUT
otp_lc_data_o.error	Yes	Yes	T3,T9,T44	Yes	T3,T9,T44	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_keymgr_key_o.owner_seed_valid	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.owner_seed[255:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed_valid	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_seed[255:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_keymgr_key_o.creator_root_key_share1_valid	Yes	Yes	T4,T97,T51	Yes	T2,T4,T97	OUTPUT
otp_keymgr_key_o.creator_root_key_share1[255:0]	Yes	Yes	T51,T240,T241	Yes	T240,T238,T242	OUTPUT
otp_keymgr_key_o.creator_root_key_share0_valid	Yes	Yes	T4,T97,T51	Yes	T2,T4,T97	OUTPUT
otp_keymgr_key_o.creator_root_key_share0[255:0]	Yes	Yes	T3,T12,T97	Yes	T3,T10,T12	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_otp_key_i.data_req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
sram_otp_key_i[1].req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
sram_otp_key_i[2].req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
sram_otp_key_i[3].req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[3].seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
sram_otp_key_o[3].nonce[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[3].key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
sram_otp_key_o[3].ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T4,T97,T51	Yes	T4,T97,T24	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
otp_broadcast_o.hw_cfg0_data.device_id[255:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg0_data.manuf_state[255:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	OUTPUT
otp_broadcast_o.hw_cfg1_data.unallocated[39:0]	Yes	Yes	T5,T97,T95	Yes	T2,T5,T97	OUTPUT
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:0]	Yes	Yes	T44,T97,T131	Yes	T44,T97,T131	OUTPUT
otp_broadcast_o.valid[3:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T3,T4,T9	Yes	T2,T4,T5	INPUT
scan_rst_ni	Yes	Yes	T3,T4,T44	Yes	T4,T9,T12	INPUT
scanmode_i[3:0]	Yes	Yes	T4,T5,T97	Yes	T3,T4,T97	INPUT
cio_test_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0]	Yes	Yes	T19,T20,T21	Yes	T11,T17,T18	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		28	27	96.43
TERNARY	382	2	1	50.00
TERNARY	1439	2	2	100.00
TERNARY	1441	2	2	100.00
TERNARY	1443	2	2	100.00
IF	287	2	2	100.00
IF	308	2	2	100.00
IF	334	2	2	100.00
IF	341	2	2	100.00
IF	407	2	2	100.00
IF	448	2	2	100.00
IF	469	2	2	100.00
IF	472	2	2	100.00
IF	499	2	2	100.00
IF	991	2	2	100.00

382          assign direct_access_regwen_d = (reg2hw.direct_access_regwen.qe &&
                                                                               
383                                           !reg2hw.direct_access_regwen.q) ? 1'b0 : direct_access_regwen_q;
                                                                              -1-  
                                                                              ==>  
                                                                              ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

1439         assign test_tokens_valid = (part_digest[Secret0Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
                                                                        -1-  
                                                                        ==>  
                                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T44,T97
0	Covered	T1,T2,T3

1441         assign rma_token_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
                                                                      -1-  
                                                                      ==>  
                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T97
0	Covered	T1,T2,T3

1443         assign secrets_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off;
                                                                    -1-  
                                                                    ==>  
                                                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T97
0	Covered	T1,T2,T3

287            if (tlul_req) begin
               -1-  
288              if (tlul_part_sel_oh != '0) begin
                 -2-  
289                part_tlul_req[tlul_part_idx] = 1'b1;
                   ==>
290              end else begin
291                // Error out in the next cycle if address was out of bounds.
292                tlul_oob_err_d = 1'b1;
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
293              end
294            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Covered	T2,T3,T4
1	0	Excluded		VC_COV_UNR
0	-	Covered	T1,T2,T3

308            if (!rst_ni) begin
               -1-  
309              tlul_oob_err_q <= 1'b0;
                 ==>
310            end else begin
311              tlul_oob_err_q <= tlul_oob_err_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

334            if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en)) begin
               -1-  
335              for (int k = 0; k < NumPart; k++) begin
                 ==>
336                if (PartInfo[k].iskeymgr_creator) begin
337                  part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}};
338                end
339              end
340            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

341            if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en)) begin
               -1-  
342              for (int k = 0; k < NumPart; k++) begin
                 ==>
343                if (PartInfo[k].iskeymgr_owner) begin
344                  part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}};
345                end
346              end
347            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

407            if (!rst_ni) begin
               -1-  
408              otp_idle_q <= 1'b0;
                 ==>
409              // The regwen bit has to reset to 1 so that CSR accesses are enabled by default.
410              direct_access_regwen_q  <= 1'b1;
411            end else begin
412              otp_idle_q <= otp_idle_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

448              if (PartInfo[k].integrity) begin
                 -1-  
449                fatal_macro_error_d |= part_error[k] == MacroEccUncorrError;
                   ==>
450              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

469              if (fatal_macro_error_q || fatal_check_error_q) begin
                 -1-  
470                lc_escalate_en[k] = lc_ctrl_pkg::On;
                   ==>
471              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T44
0	Covered	T1,T2,T3

472              if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k])) begin
                 -1-  
473                lc_escalate_en_any = 1'b1;
                   ==>
474              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T44
0	Covered	T1,T2,T3

499            if (!rst_ni) begin
               -1-  
500              fatal_macro_error_q     <= '0;
                 ==>
501              fatal_check_error_q     <= '0;
502              fatal_bus_integ_error_q <= '0;
503              interrupt_triggers_q    <= '0;
504            end else begin
505              fatal_macro_error_q     <= fatal_macro_error_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

991            if (!rst_ni) begin
               -1-  
992              pwr_otp_rsp_q <= 1'b0;
                 ==>
993            end else begin
994              pwr_otp_rsp_q <= pwr_otp_rsp_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	71	71	100.00	69	97.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	71	71	100.00	69	97.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	84443599	83613730	0	0
CoreTlOutKnown_A	84443599	83613730	0	0
CreatorRootKeyShare0Size_A	1114	1114	0	0
CreatorRootKeyShare1Size_A	1114	1114	0	0
ErrorCodeWidth_A	1114	1114	0	0
FlashAddrKeySeedSize_A	1114	1114	0	0
FlashDataKeySeedSize_A	1114	1114	0	0
FlashOtpKeyRspKnown_A	84443599	83613730	0	0
FpvSecCmCntCnstyCheck_A	84443599	50	0	0
FpvSecCmCntDaiCheck_A	84443599	50	0	0
FpvSecCmCntIntegCheck_A	84443599	50	0	0
FpvSecCmCntKdiEntropyCheck_A	84443599	50	0	0
FpvSecCmCntKdiSeedCheck_A	84443599	50	0	0
FpvSecCmCntLciCheck_A	84443599	50	0	0
FpvSecCmCntScrmblCheck_A	84443599	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	84443599	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	84443599	50	0	0
FpvSecCmCtrlLciFsmCheck_A	84443599	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	84443599	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	84443599	50	0	0
FpvSecCmDoubleLfsrCheck_A	84443599	50	0	0
FpvSecCmRegWeOnehotCheck_A	84443599	50	0	0
FpvSecCmTlLcGateFsm_A	84443599	50	0	0
IntrOtpErrorKnown_A	84443599	83613730	0	0
IntrOtpOperationDoneKnown_A	84443599	83613730	0	0
LcOtpProgramRspKnown_A	84443599	83613730	0	0
LcSeedHwRdEnStable0_A	84443599	2120	0	0
LcSeedHwRdEnStable1_A	84443599	2120	0	0
LcSeedHwRdEnStable2_A	84443599	0	0	0
LcSeedHwRdEnStable3_A	84443599	0	0	0
LcStateSize_A	1114	1114	0	0
LcTransitionCntSize_A	1114	1114	0	0
OtpAstPwrSeqKnown_A	84443599	83613730	0	0
OtpBroadcastKnown_A	84443599	83613730	0	0
OtpErrorCode0_A	1114	1114	0	0
OtpErrorCode1_A	1114	1114	0	0
OtpErrorCode2_A	1114	1114	0	0
OtpErrorCode3_A	1114	1114	0	0
OtpErrorCode4_A	1114	1114	0	0
OtpIfWidth_A	1114	1114	0	0
OtpKeymgrKeyKnown_A	84443599	83613730	0	0
OtpLcDataKnown_A	84443599	83613730	0	0
OtpOtgnKeyKnown_A	84443599	83613730	0	0
OtpRespFifoUnderflow_A	84443599	1162017	0	0
OtpSramKeyKnown_A	84443599	83613730	0	0
PartSelMustBeOnehot_A	84443599	83613730	0	0
PrimTlOutKnown_A	84443599	83613730	0	0
PwrOtpInitRspKnown_A	84443599	83613730	0	0
RmaTokenSize_A	1114	1114	0	0
SramDataKeySeedSize_A	1114	1114	0	0
TestExitTokenSize_A	1114	1114	0	0
TestUnlockTokenSize_A	1114	1114	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A	84443599	50	0	0
gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	84443599	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	84443599	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A	84443599	50	0	0
gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	84443599	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	84443599	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	84443599	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

LcSeedHwRdEnStable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	2120	0	0
T2	12798	1	0	0
T3	10127	0	0	0
T4	55214	6	0	0
T5	18048	0	0	0
T9	22622	0	0	0
T10	59751	0	0	0
T11	4514	0	0	0
T12	12039	0	0	0
T13	47890	0	0	0
T17	4541	0	0	0
T19	0	4	0	0
T51	0	3	0	0
T95	0	5	0	0
T97	0	2	0	0
T98	0	5	0	0
T124	0	8	0	0
T130	0	2	0	0
T131	0	2	0	0

LcSeedHwRdEnStable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	2120	0	0
T2	12798	1	0	0
T3	10127	0	0	0
T4	55214	6	0	0
T5	18048	0	0	0
T9	22622	0	0	0
T10	59751	0	0	0
T11	4514	0	0	0
T12	12039	0	0	0
T13	47890	0	0	0
T17	4541	0	0	0
T19	0	4	0	0
T51	0	3	0	0
T95	0	5	0	0
T97	0	2	0	0
T98	0	5	0	0
T124	0	8	0	0
T130	0	2	0	0
T131	0	2	0	0

LcSeedHwRdEnStable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	0	0	0

LcSeedHwRdEnStable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	0	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpBroadcastKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	1162017	0	0
T1	5120	111	0	0
T2	12798	235	0	0
T3	10127	171	0	0
T4	55214	2350	0	0
T5	18048	266	0	0
T9	22622	151	0	0
T10	59751	1356	0	0
T11	4514	55	0	0
T12	12039	299	0	0
T13	47890	949	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	83613730	0	0
T1	5120	5042	0	0
T2	12798	12610	0	0
T3	10127	9822	0	0
T4	55214	54147	0	0
T5	18048	17835	0	0
T9	22622	22337	0	0
T10	59751	59694	0	0
T11	4514	4458	0	0
T12	12039	11780	0	0
T13	47890	47829	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114	1114	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[10].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[3].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[4].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[7].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[8].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_partitions[9].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84443599	50	0	0
T26	945939	10	0	0
T27	104876	10	0	0
T28	0	10	0	0
T155	43413	0	0	0
T223	12268	0	0	0
T232	102811	0	0	0
T243	0	10	0	0
T244	0	10	0	0
T245	103222	0	0	0
T246	712056	0	0	0
T247	5834	0	0	0
T248	8598	0	0	0
T249	9746	0	0	0