Line Coverage for Module :
otp_ctrl_scrmbl
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 120 | 110 | 91.67 |
| ALWAYS | 141 | 10 | 0 | 0.00 |
| CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 209 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 215 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
| ALWAYS | 302 | 75 | 75 | 100.00 |
| ALWAYS | 476 | 3 | 3 | 100.00 |
| ALWAYS | 479 | 21 | 21 | 100.00 |
140 always_comb begin : p_luts
141 0/1 ==> otp_enc_key_lut = '0;
142 0/1 ==> otp_dec_key_lut = '0;
143 0/1 ==> digest_const_lut = '0;
144 0/1 ==> digest_iv_lut = '0;
145
146 0/1 ==> for (int k = 0; k < NumScrmblKeys; k++) begin
147 localparam logic [4:0] NumRounds = 5'(unsigned'(NumPresentRounds));
148 0/1 ==> otp_enc_key_lut[k] = rnd_cnst_key_anchor[k];
149 // Due to the PRESENT key schedule, we have to step the key schedule function by
150 // NumPresentRounds forwards to get the decryption key.
151 0/1 ==> otp_dec_key_lut[k] =
152 prim_cipher_pkg::present_get_dec_key128(rnd_cnst_key_anchor[k], NumRounds);
153 end
154
155 0/1 ==> for (int k = 0; k < NumDigestSets; k++) begin
156 0/1 ==> digest_const_lut[k] = rnd_cnst_digest_anchor[k];
157 0/1 ==> digest_iv_lut[k] = rnd_cnst_digest_iv_anchor[k];
158 end
159 end
160 `ASSERT_KNOWN(EncKeyLutKnown_A, otp_enc_key_lut)
161 `ASSERT_KNOWN(DecKeyLutKnown_A, otp_dec_key_lut)
162 `ASSERT_KNOWN(DigestConstLutKnown_A, digest_const_lut)
163 `ASSERT_KNOWN(DigestIvLutKnown_A, digest_iv_lut)
164
165 //////////////
166 // Datapath //
167 //////////////
168
169 logic [4:0] idx_state_d, idx_state_q;
170 logic [ScrmblKeyWidth-1:0] key_state_d, key_state_q;
171 logic [ScrmblBlockWidth-1:0] data_state_d, data_state_q, data_shadow_q;
172 logic [ScrmblBlockWidth-1:0] digest_state_d, digest_state_q;
173 logic [ScrmblBlockWidth-1:0] enc_data_out, enc_data_out_xor, dec_data_out;
174 logic [ScrmblKeyWidth-1:0] dec_key_out, enc_key_out;
175 logic [4:0] dec_idx_out, enc_idx_out;
176 logic [ScrmblKeyWidth-1:0] otp_digest_const_mux, otp_enc_key_mux, otp_dec_key_mux;
177 logic [ScrmblBlockWidth-1:0] otp_digest_iv_mux;
178
179 typedef enum logic [2:0] {SelEncDataOut,
180 SelDecDataOut,
181 SelDigestState,
182 SelEncDataOutXor,
183 SelDataInput} data_state_sel_e;
184
185 typedef enum logic [2:0] {SelDecKeyOut,
186 SelEncKeyOut,
187 SelDecKeyInit,
188 SelEncKeyInit,
189 SelDigestConst,
190 SelDigestInput,
191 SelDigestChained} key_state_sel_e;
192
193 logic digest_init;
194 data_state_sel_e data_state_sel;
195 key_state_sel_e key_state_sel;
196 logic data_state_en, data_shadow_copy, data_shadow_load, digest_state_en, key_state_en;
197 digest_mode_e digest_mode_d, digest_mode_q;
198
199 1/1 assign otp_enc_key_mux = otp_enc_key_lut[ScrmblKeySelWidth'(sel_i)];
Tests: T1 T2 T3
200 1/1 assign otp_dec_key_mux = otp_dec_key_lut[ScrmblKeySelWidth'(sel_i)];
Tests: T1 T2 T3
201 1/1 assign otp_digest_const_mux = digest_const_lut[DigestSetSelWidth'(sel_i)];
Tests: T1 T2 T3
202 1/1 assign otp_digest_iv_mux = digest_iv_lut[DigestSetSelWidth'(sel_i)];
Tests: T1 T2 T3
203
204 // Make sure we always select a valid key / digest constant.
205 `ASSERT(CheckNumEncKeys_A, key_state_sel == SelEncKeyInit |-> sel_i < NumScrmblKeys)
206 `ASSERT(CheckNumDecKeys_A, key_state_sel == SelDecKeyInit |-> sel_i < NumScrmblKeys)
207 `ASSERT(CheckNumDigest1_A, key_state_sel == SelDigestConst |-> sel_i < NumDigestSets)
208
209 1/1 assign data_state_d = (data_state_sel == SelEncDataOut) ? enc_data_out :
Tests: T1 T2 T3
210 (data_state_sel == SelDecDataOut) ? dec_data_out :
211 (data_state_sel == SelDigestState) ? digest_state_q :
212 (data_state_sel == SelEncDataOutXor) ? enc_data_out_xor :
213 data_i;
214
215 1/1 assign key_state_d = (key_state_sel == SelDecKeyOut) ? dec_key_out :
Tests: T1 T2 T3
216 (key_state_sel == SelEncKeyOut) ? enc_key_out :
217 (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux :
218 (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux :
219 (key_state_sel == SelDigestConst) ? otp_digest_const_mux :
220 (key_state_sel == SelDigestChained) ? {data_state_q, data_shadow_q} :
221 {data_i, data_shadow_q};
222
223 // Initialize the round index state with 1 in all cases, except for the decrypt operation.
224 1/1 assign idx_state_d = (key_state_sel == SelDecKeyOut) ? dec_idx_out :
Tests: T1 T2 T3
225 (key_state_sel == SelEncKeyOut) ? enc_idx_out :
226 (key_state_sel == SelDecKeyInit) ? unsigned'(5'(NumPresentRounds)) :
227 5'd1;
228
229 // The XOR is for the Davies-Mayer one-way function construction.
230 1/1 assign enc_data_out_xor = enc_data_out ^ digest_state_q;
Tests: T1 T2 T3
231 1/1 assign digest_state_d = (digest_init) ? otp_digest_iv_mux : enc_data_out_xor;
Tests: T1 T2 T3
232
233 logic valid_q; //valid_d defined below
234 1/1 assign data_o = (valid_q) ? data_state_q : 0;
Tests: T1 T2 T3
235
236 /////////
237 // FSM //
238 /////////
239
240 // SEC_CM: SCRMBL.FSM.SPARSE
241 // Encoding generated with:
242 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \
243 // -s 2193087944 --language=sv
244 //
245 // Hamming distance histogram:
246 //
247 // 0: --
248 // 1: --
249 // 2: --
250 // 3: --
251 // 4: --
252 // 5: |||||||||||||||||||| (60.00%)
253 // 6: ||||||||||||| (40.00%)
254 // 7: --
255 // 8: --
256 // 9: --
257 //
258 // Minimum Hamming distance: 5
259 // Maximum Hamming distance: 6
260 // Minimum Hamming weight: 4
261 // Maximum Hamming weight: 7
262 //
263 localparam int StateWidth = 9;
264 typedef enum logic [StateWidth-1:0] {
265 IdleSt = 9'b100011001,
266 DecryptSt = 9'b101101111,
267 EncryptSt = 9'b010010111,
268 DigestSt = 9'b111000010,
269 ErrorSt = 9'b011111000
270 } state_e;
271
272 localparam int CntWidth = $clog2(NumPresentRounds+1);
273 localparam int unsigned LastPresentRoundInt = NumPresentRounds - 1;
274 localparam bit [CntWidth-1:0] LastPresentRound = LastPresentRoundInt[CntWidth-1:0];
275
276 state_e state_d, state_q;
277 logic [CntWidth-1:0] cnt;
278 logic cnt_clr, cnt_en, cnt_err;
279 logic valid_d; //valid_q defined above
280
281 1/1 assign valid_o = valid_q;
Tests: T1 T2 T3
282
283 // SEC_CM: SCRMBL.CTR.REDUN
284 prim_count #(
285 .Width(CntWidth)
286 ) u_prim_count (
287 .clk_i,
288 .rst_ni,
289 .clr_i(cnt_clr),
290 .set_i(1'b0),
291 .set_cnt_i('0),
292 .incr_en_i(cnt_en),
293 .decr_en_i(1'b0),
294 .step_i(CntWidth'(1)),
295 .commit_i(1'b1),
296 .cnt_o(cnt),
297 .cnt_after_commit_o(),
298 .err_o(cnt_err)
299 );
300
301 always_comb begin : p_fsm
302 1/1 state_d = state_q;
Tests: T1 T2 T3
303 1/1 digest_mode_d = digest_mode_q;
Tests: T1 T2 T3
304 1/1 data_state_sel = SelDataInput;
Tests: T1 T2 T3
305 1/1 key_state_sel = SelDigestInput;
Tests: T1 T2 T3
306 1/1 digest_init = 1'b0;
Tests: T1 T2 T3
307 1/1 data_state_en = 1'b0;
Tests: T1 T2 T3
308 1/1 data_shadow_copy = 1'b0;
Tests: T1 T2 T3
309 1/1 data_shadow_load = 1'b0;
Tests: T1 T2 T3
310 1/1 key_state_en = 1'b0;
Tests: T1 T2 T3
311 1/1 digest_state_en = 1'b0;
Tests: T1 T2 T3
312 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
313 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
314 1/1 valid_d = 1'b0;
Tests: T1 T2 T3
315 1/1 ready_o = 1'b0;
Tests: T1 T2 T3
316 1/1 fsm_err_o = 1'b0;
Tests: T1 T2 T3
317
318 1/1 unique case (state_q)
Tests: T1 T2 T3
319 ///////////////////////////////////////////////////////////////////
320 // Idle State: decode command and
321 // load working regs accordingly
322 IdleSt: begin
323 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
324 1/1 ready_o = 1'b1;
Tests: T1 T2 T3
325
326 1/1 if (valid_i) begin
Tests: T1 T2 T3
327 1/1 unique case (cmd_i)
Tests: T1 T2 T3
328 Decrypt: begin
329 1/1 state_d = DecryptSt;
Tests: T1 T2 T3
330 1/1 key_state_sel = SelDecKeyInit;
Tests: T1 T2 T3
331 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
332 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
333 end
334 Encrypt: begin
335 1/1 state_d = EncryptSt;
Tests: T1 T2 T3
336 1/1 key_state_sel = SelEncKeyInit;
Tests: T1 T2 T3
337 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
338 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
339 end
340 LoadShadow: begin
341 1/1 if (digest_mode_q == ChainedMode) begin
Tests: T1 T2 T3
342 1/1 data_shadow_copy = 1'b1;
Tests: T1 T2 T3
343 end else begin
344 1/1 data_shadow_load = 1'b1;
Tests: T1 T2 T3
345 end
346 end
347 Digest: begin
348 1/1 state_d = DigestSt;
Tests: T1 T2 T3
349 1/1 data_state_sel = SelDigestState;
Tests: T1 T2 T3
350 1/1 key_state_sel = (digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput;
Tests: T1 T2 T3
351 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
352 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
353 end
354 DigestInit: begin
355 1/1 digest_mode_d = mode_i;
Tests: T1 T2 T3
356 1/1 digest_init = 1'b1;
Tests: T1 T2 T3
357 1/1 digest_state_en = 1'b1;
Tests: T1 T2 T3
358 end
359 DigestFinalize: begin
360 1/1 state_d = DigestSt;
Tests: T1 T2 T3
361 1/1 data_state_sel = SelDigestState;
Tests: T1 T2 T3
362 1/1 key_state_sel = SelDigestConst;
Tests: T1 T2 T3
363 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
364 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
365 1/1 digest_mode_d = StandardMode;
Tests: T1 T2 T3
366 end
367 default: ; // ignore
368 endcase // cmd_i
369 end
MISSING_ELSE
370 end
371 ///////////////////////////////////////////////////////////////////
372 // Perform decrypt rounds.
373 DecryptSt: begin
374 1/1 data_state_sel = SelDecDataOut;
Tests: T1 T2 T3
375 1/1 key_state_sel = SelDecKeyOut;
Tests: T1 T2 T3
376 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
377 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
378 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
379 1/1 if (cnt == LastPresentRound) begin
Tests: T1 T2 T3
380 1/1 state_d = IdleSt;
Tests: T1 T2 T3
381 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
382 end
MISSING_ELSE
383 end
384 ///////////////////////////////////////////////////////////////////
385 // Perform encrypt rounds.
386 EncryptSt: begin
387 1/1 data_state_sel = SelEncDataOut;
Tests: T1 T2 T3
388 1/1 key_state_sel = SelEncKeyOut;
Tests: T1 T2 T3
389 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
390 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
391 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
392 1/1 if (cnt == LastPresentRound) begin
Tests: T1 T2 T3
393 1/1 state_d = IdleSt;
Tests: T1 T2 T3
394 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
395 end
MISSING_ELSE
396 end
397 ///////////////////////////////////////////////////////////////////
398 // The digest is calculated with a Merkle-Damgard construction that
399 // employs the PRESENT encryption datapath.
400 DigestSt: begin
401 1/1 data_state_sel = SelEncDataOut;
Tests: T1 T2 T3
402 1/1 key_state_sel = SelEncKeyOut;
Tests: T1 T2 T3
403 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
404 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
405 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
406 1/1 if (cnt == LastPresentRound) begin
Tests: T1 T2 T3
407 1/1 state_d = IdleSt;
Tests: T1 T2 T3
408 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
409 // Apply XOR for Davies-Meyer construction.
410 1/1 data_state_sel = SelEncDataOutXor;
Tests: T1 T2 T3
411 // Backup digest state for next round of updates. We can't keep this state in the
412 // data state register as a digest may be calculated together with encryption
413 // operations in an interleaved way.
414 1/1 digest_state_en = 1'b1;
Tests: T1 T2 T3
415 end
MISSING_ELSE
416 end
417 ///////////////////////////////////////////////////////////////////
418 // Terminal error state. This raises an alert.
419 ErrorSt: begin
420 1/1 fsm_err_o = 1'b1;
Tests: T9 T94 T96
421 end
422 ///////////////////////////////////////////////////////////////////
423 // This should never happen, hence we directly jump into the
424 // error state, where an alert will be triggered.
425 default: begin
426 state_d = ErrorSt;
427 fsm_err_o = 1'b1;
428 end
429 ///////////////////////////////////////////////////////////////////
430 endcase // state_q
431
432 // Unconditionally jump into the terminal error state in case of escalation.
433 // SEC_CM: SCRMBL.FSM.LOCAL_ESC, SCRMBL.FSM.GLOBAL_ESC
434 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin
Tests: T1 T2 T3
435 1/1 state_d = ErrorSt;
Tests: T9 T94 T96
436 1/1 fsm_err_o = 1'b1;
Tests: T9 T94 T96
437 end
MISSING_ELSE
438 end
439
440 /////////////////////////////
441 // PRESENT DEC/ENC Modules //
442 /////////////////////////////
443
444 prim_present #(
445 .KeyWidth(128),
446 .NumRounds(NumPresentRounds),
447 .NumPhysRounds(1)
448 ) u_prim_present_enc (
449 .data_i ( data_state_q ),
450 .key_i ( key_state_q ),
451 .idx_i ( idx_state_q ),
452 .data_o ( enc_data_out ),
453 .key_o ( enc_key_out ),
454 .idx_o ( enc_idx_out )
455 );
456
457 prim_present #(
458 .KeyWidth(128),
459 // We are using an iterative full-round implementation here.
460 .NumRounds(NumPresentRounds),
461 .NumPhysRounds(1),
462 .Decrypt(1)
463 ) u_prim_present_dec (
464 .data_i ( data_state_q ),
465 .key_i ( key_state_q ),
466 .idx_i ( idx_state_q ),
467 .data_o ( dec_data_out ),
468 .key_o ( dec_key_out ),
469 .idx_o ( dec_idx_out )
470 );
471
472 ///////////////
473 // Registers //
474 ///////////////
475
476 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt):
476.1 `ifdef SIMULATION
476.2 prim_sparse_fsm_flop #(
476.3 .StateEnumT(state_e),
476.4 .Width($bits(state_e)),
476.5 .ResetValue($bits(state_e)'(IdleSt)),
476.6 .EnableAlertTriggerSVA(1),
476.7 .CustomForceName("state_q")
476.8 ) u_state_regs (
476.9 .clk_i ( clk_i ),
476.10 .rst_ni ( rst_ni ),
476.11 .state_i ( state_d ),
476.12 .state_o ( )
476.13 );
476.14 always_ff @(posedge clk_i or negedge rst_ni) begin
476.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
476.16 1/1 state_q <= IdleSt;
Tests: T1 T2 T3
476.17 end else begin
476.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
476.19 end
476.20 end
476.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
476.22 else begin
476.23 `ifdef UVM
476.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
476.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv", 476, "", 1);
476.26 `else
476.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
476.28 `PRIM_STRINGIFY(u_state_regs_A));
476.29 `endif
476.30 end
476.31 `else
476.32 prim_sparse_fsm_flop #(
476.33 .StateEnumT(state_e),
476.34 .Width($bits(state_e)),
476.35 .ResetValue($bits(state_e)'(IdleSt)),
476.36 .EnableAlertTriggerSVA(1)
476.37 ) u_state_regs (
476.38 .clk_i ( `PRIM_FLOP_CLK ),
476.39 .rst_ni ( `PRIM_FLOP_RST ),
476.40 .state_i ( state_d ),
476.41 .state_o ( state_q )
476.42 );
476.43 `endif477
478 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
479 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
480 1/1 key_state_q <= '0;
Tests: T1 T2 T3
481 1/1 idx_state_q <= '0;
Tests: T1 T2 T3
482 1/1 data_state_q <= '0;
Tests: T1 T2 T3
483 1/1 data_shadow_q <= '0;
Tests: T1 T2 T3
484 1/1 digest_state_q <= '0;
Tests: T1 T2 T3
485 1/1 valid_q <= 1'b0;
Tests: T1 T2 T3
486 1/1 digest_mode_q <= StandardMode;
Tests: T1 T2 T3
487 end else begin
488 1/1 valid_q <= valid_d;
Tests: T1 T2 T3
489 1/1 digest_mode_q <= digest_mode_d;
Tests: T1 T2 T3
490
491 // enable regs
492 1/1 if (key_state_en) begin
Tests: T1 T2 T3
493 1/1 key_state_q <= key_state_d;
Tests: T1 T2 T3
494 1/1 idx_state_q <= idx_state_d;
Tests: T1 T2 T3
495 end
MISSING_ELSE
496 1/1 if (data_state_en) begin
Tests: T1 T2 T3
497 1/1 data_state_q <= data_state_d;
Tests: T1 T2 T3
498 end
MISSING_ELSE
499 1/1 if (data_shadow_copy) begin
Tests: T1 T2 T3
500 1/1 data_shadow_q <= data_state_q;
Tests: T1 T2 T3
501 1/1 end else if (data_shadow_load) begin
Tests: T1 T2 T3
502 1/1 data_shadow_q <= data_state_d;
Tests: T1 T2 T3
503 end
MISSING_ELSE
504 1/1 if (digest_state_en) begin
Tests: T1 T2 T3
505 1/1 digest_state_q <= digest_state_d;
Tests: T1 T2 T3
506 end
MISSING_ELSE
Cond Coverage for Module :
otp_ctrl_scrmbl
| Total | Covered | Percent |
|---|
| Conditions | 68 | 68 | 100.00 |
| Logical | 68 | 68 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 209
EXPRESSION
Number Term
1 (data_state_sel == SelEncDataOut) ? enc_data_out : ((data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION (data_state_sel == SelEncDataOut)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION
Number Term
1 (data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION (data_state_sel == SelDecDataOut)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION (data_state_sel == SelDigestState)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)
------------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION (data_state_sel == SelEncDataOutXor)
------------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
EXPRESSION
Number Term
1 (key_state_sel == SelDecKeyOut) ? dec_key_out : ((key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION
Number Term
1 (key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION
Number Term
1 (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION
Number Term
1 (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelEncKeyInit)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION
Number Term
1 (key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelDigestConst)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelDigestChained)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
EXPRESSION
Number Term
1 (key_state_sel == SelDecKeyOut) ? dec_idx_out : ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1))
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 231
EXPRESSION (digest_init ? otp_digest_iv_mux : enc_data_out_xor)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 234
EXPRESSION (valid_q ? data_state_q : 0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 341
EXPRESSION (digest_mode_q == ChainedMode)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 350
EXPRESSION ((digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 350
SUB-EXPRESSION (digest_mode_q == ChainedMode)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 379
EXPRESSION (cnt == LastPresentRound)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 392
EXPRESSION (cnt == LastPresentRound)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 406
EXPRESSION (cnt == LastPresentRound)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
otp_ctrl_scrmbl
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
5 |
5 |
100.00 |
(Not included in score) |
| Transitions |
10 |
10 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DecryptSt |
329 |
Covered |
T1,T2,T3 |
| DigestSt |
348 |
Covered |
T1,T2,T3 |
| EncryptSt |
335 |
Covered |
T1,T2,T3 |
| ErrorSt |
435 |
Covered |
T9,T94,T96 |
| IdleSt |
380 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| DecryptSt->ErrorSt |
435 |
Covered |
T100,T156,T284 |
| DecryptSt->IdleSt |
380 |
Covered |
T1,T2,T3 |
| DigestSt->ErrorSt |
435 |
Covered |
T173,T105,T148 |
| DigestSt->IdleSt |
407 |
Covered |
T1,T2,T3 |
| EncryptSt->ErrorSt |
435 |
Covered |
T153,T16,T155 |
| EncryptSt->IdleSt |
393 |
Covered |
T1,T2,T3 |
| IdleSt->DecryptSt |
329 |
Covered |
T1,T2,T3 |
| IdleSt->DigestSt |
348 |
Covered |
T1,T2,T3 |
| IdleSt->EncryptSt |
335 |
Covered |
T1,T2,T3 |
| IdleSt->ErrorSt |
435 |
Covered |
T9,T94,T96 |
Branch Coverage for Module :
otp_ctrl_scrmbl
| Line No. | Total | Covered | Percent |
| Branches |
|
52 |
51 |
98.08 |
| TERNARY |
209 |
5 |
5 |
100.00 |
| TERNARY |
215 |
7 |
7 |
100.00 |
| TERNARY |
224 |
4 |
4 |
100.00 |
| TERNARY |
231 |
2 |
2 |
100.00 |
| TERNARY |
234 |
2 |
2 |
100.00 |
| CASE |
318 |
18 |
17 |
94.44 |
| IF |
434 |
2 |
2 |
100.00 |
| IF |
476 |
2 |
2 |
100.00 |
| IF |
479 |
10 |
10 |
100.00 |
209 assign data_state_d = (data_state_sel == SelEncDataOut) ? enc_data_out :
-1-
==>
210 (data_state_sel == SelDecDataOut) ? dec_data_out :
-2-
==>
211 (data_state_sel == SelDigestState) ? digest_state_q :
-3-
==>
212 (data_state_sel == SelEncDataOutXor) ? enc_data_out_xor :
-4-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
215 assign key_state_d = (key_state_sel == SelDecKeyOut) ? dec_key_out :
-1-
==>
216 (key_state_sel == SelEncKeyOut) ? enc_key_out :
-2-
==>
217 (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux :
-3-
==>
218 (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux :
-4-
==>
219 (key_state_sel == SelDigestConst) ? otp_digest_const_mux :
-5-
==>
220 (key_state_sel == SelDigestChained) ? {data_state_q, data_shadow_q} :
-6-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
224 assign idx_state_d = (key_state_sel == SelDecKeyOut) ? dec_idx_out :
-1-
==>
225 (key_state_sel == SelEncKeyOut) ? enc_idx_out :
-2-
==>
226 (key_state_sel == SelDecKeyInit) ? unsigned'(5'(NumPresentRounds)) :
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
231 assign digest_state_d = (digest_init) ? otp_digest_iv_mux : enc_data_out_xor;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
234 assign data_o = (valid_q) ? data_state_q : 0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
318 unique case (state_q)
-1-
319 ///////////////////////////////////////////////////////////////////
320 // Idle State: decode command and
321 // load working regs accordingly
322 IdleSt: begin
323 cnt_clr = 1'b1;
324 ready_o = 1'b1;
325
326 if (valid_i) begin
-2-
327 unique case (cmd_i)
-3-
328 Decrypt: begin
329 state_d = DecryptSt;
==>
330 key_state_sel = SelDecKeyInit;
331 data_state_en = 1'b1;
332 key_state_en = 1'b1;
333 end
334 Encrypt: begin
335 state_d = EncryptSt;
==>
336 key_state_sel = SelEncKeyInit;
337 data_state_en = 1'b1;
338 key_state_en = 1'b1;
339 end
340 LoadShadow: begin
341 if (digest_mode_q == ChainedMode) begin
-4-
342 data_shadow_copy = 1'b1;
==>
343 end else begin
344 data_shadow_load = 1'b1;
==>
345 end
346 end
347 Digest: begin
348 state_d = DigestSt;
349 data_state_sel = SelDigestState;
350 key_state_sel = (digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput;
-5-
==>
==>
351 data_state_en = 1'b1;
352 key_state_en = 1'b1;
353 end
354 DigestInit: begin
355 digest_mode_d = mode_i;
==>
356 digest_init = 1'b1;
357 digest_state_en = 1'b1;
358 end
359 DigestFinalize: begin
360 state_d = DigestSt;
==>
361 data_state_sel = SelDigestState;
362 key_state_sel = SelDigestConst;
363 data_state_en = 1'b1;
364 key_state_en = 1'b1;
365 digest_mode_d = StandardMode;
366 end
367 default: ; // ignore
==>
368 endcase // cmd_i
369 end
MISSING_ELSE
==>
370 end
371 ///////////////////////////////////////////////////////////////////
372 // Perform decrypt rounds.
373 DecryptSt: begin
374 data_state_sel = SelDecDataOut;
375 key_state_sel = SelDecKeyOut;
376 data_state_en = 1'b1;
377 key_state_en = 1'b1;
378 cnt_en = 1'b1;
379 if (cnt == LastPresentRound) begin
-6-
380 state_d = IdleSt;
==>
381 valid_d = 1'b1;
382 end
MISSING_ELSE
==>
383 end
384 ///////////////////////////////////////////////////////////////////
385 // Perform encrypt rounds.
386 EncryptSt: begin
387 data_state_sel = SelEncDataOut;
388 key_state_sel = SelEncKeyOut;
389 data_state_en = 1'b1;
390 key_state_en = 1'b1;
391 cnt_en = 1'b1;
392 if (cnt == LastPresentRound) begin
-7-
393 state_d = IdleSt;
==>
394 valid_d = 1'b1;
395 end
MISSING_ELSE
==>
396 end
397 ///////////////////////////////////////////////////////////////////
398 // The digest is calculated with a Merkle-Damgard construction that
399 // employs the PRESENT encryption datapath.
400 DigestSt: begin
401 data_state_sel = SelEncDataOut;
402 key_state_sel = SelEncKeyOut;
403 data_state_en = 1'b1;
404 key_state_en = 1'b1;
405 cnt_en = 1'b1;
406 if (cnt == LastPresentRound) begin
-8-
407 state_d = IdleSt;
==>
408 valid_d = 1'b1;
409 // Apply XOR for Davies-Meyer construction.
410 data_state_sel = SelEncDataOutXor;
411 // Backup digest state for next round of updates. We can't keep this state in the
412 // data state register as a digest may be calculated together with encryption
413 // operations in an interleaved way.
414 digest_state_en = 1'b1;
415 end
MISSING_ELSE
==>
416 end
417 ///////////////////////////////////////////////////////////////////
418 // Terminal error state. This raises an alert.
419 ErrorSt: begin
420 fsm_err_o = 1'b1;
==>
421 end
422 ///////////////////////////////////////////////////////////////////
423 // This should never happen, hence we directly jump into the
424 // error state, where an alert will be triggered.
425 default: begin
426 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
Decrypt |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
1 |
Encrypt |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
1 |
LoadShadow |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
1 |
LoadShadow |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
1 |
Digest |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
1 |
Digest |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
1 |
DigestInit |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
1 |
DigestFinalize |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| IdleSt |
1 |
default |
- |
- |
- |
- |
- |
Not Covered |
|
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| DecryptSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T1,T2,T3 |
| DecryptSt |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
| EncryptSt |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T3 |
| EncryptSt |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T1,T2,T3 |
| DigestSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
| DigestSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T94,T96 |
| default |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T27,T28 |
434 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin
-1-
435 state_d = ErrorSt;
==>
436 fsm_err_o = 1'b1;
437 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T9,T94,T96 |
| 0 |
Covered |
T1,T2,T3 |
476 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
479 if (!rst_ni) begin
-1-
480 key_state_q <= '0;
==>
481 idx_state_q <= '0;
482 data_state_q <= '0;
483 data_shadow_q <= '0;
484 digest_state_q <= '0;
485 valid_q <= 1'b0;
486 digest_mode_q <= StandardMode;
487 end else begin
488 valid_q <= valid_d;
489 digest_mode_q <= digest_mode_d;
490
491 // enable regs
492 if (key_state_en) begin
-2-
493 key_state_q <= key_state_d;
==>
494 idx_state_q <= idx_state_d;
495 end
MISSING_ELSE
==>
496 if (data_state_en) begin
-3-
497 data_state_q <= data_state_d;
==>
498 end
MISSING_ELSE
==>
499 if (data_shadow_copy) begin
-4-
500 data_shadow_q <= data_state_q;
==>
501 end else if (data_shadow_load) begin
-5-
502 data_shadow_q <= data_state_d;
==>
503 end
MISSING_ELSE
==>
504 if (digest_state_en) begin
-6-
505 digest_state_q <= digest_state_d;
==>
506 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
0 |
0 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
otp_ctrl_scrmbl
Assertion Details
CheckNumDecKeys_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
232989 |
0 |
0 |
| T1 |
5120 |
24 |
0 |
0 |
| T2 |
12798 |
56 |
0 |
0 |
| T3 |
10127 |
59 |
0 |
0 |
| T4 |
55214 |
250 |
0 |
0 |
| T5 |
18048 |
75 |
0 |
0 |
| T9 |
22622 |
51 |
0 |
0 |
| T10 |
59751 |
48 |
0 |
0 |
| T11 |
4514 |
24 |
0 |
0 |
| T12 |
12039 |
77 |
0 |
0 |
| T13 |
47890 |
72 |
0 |
0 |
CheckNumDigest1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
112303 |
0 |
0 |
| T1 |
5120 |
7 |
0 |
0 |
| T2 |
12798 |
27 |
0 |
0 |
| T3 |
10127 |
8 |
0 |
0 |
| T4 |
55214 |
114 |
0 |
0 |
| T5 |
18048 |
34 |
0 |
0 |
| T9 |
22622 |
15 |
0 |
0 |
| T10 |
59751 |
5 |
0 |
0 |
| T11 |
4514 |
5 |
0 |
0 |
| T12 |
12039 |
15 |
0 |
0 |
| T13 |
47890 |
5 |
0 |
0 |
CheckNumEncKeys_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
244026 |
0 |
0 |
| T1 |
5120 |
24 |
0 |
0 |
| T2 |
12798 |
53 |
0 |
0 |
| T3 |
10127 |
40 |
0 |
0 |
| T4 |
55214 |
237 |
0 |
0 |
| T5 |
18048 |
100 |
0 |
0 |
| T9 |
22622 |
76 |
0 |
0 |
| T10 |
59751 |
48 |
0 |
0 |
| T11 |
4514 |
24 |
0 |
0 |
| T12 |
12039 |
62 |
0 |
0 |
| T13 |
47890 |
24 |
0 |
0 |
DecKeyLutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
DigestConstLutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
DigestIvLutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
EncKeyLutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
NumMaxPresentRounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1114 |
1114 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 120 | 110 | 91.67 |
| ALWAYS | 141 | 10 | 0 | 0.00 |
| CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 209 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 215 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 231 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
| ALWAYS | 302 | 75 | 75 | 100.00 |
| ALWAYS | 476 | 3 | 3 | 100.00 |
| ALWAYS | 479 | 21 | 21 | 100.00 |
140 always_comb begin : p_luts
141 0/1 ==> otp_enc_key_lut = '0;
142 0/1 ==> otp_dec_key_lut = '0;
143 0/1 ==> digest_const_lut = '0;
144 0/1 ==> digest_iv_lut = '0;
145
146 0/1 ==> for (int k = 0; k < NumScrmblKeys; k++) begin
147 localparam logic [4:0] NumRounds = 5'(unsigned'(NumPresentRounds));
148 0/1 ==> otp_enc_key_lut[k] = rnd_cnst_key_anchor[k];
149 // Due to the PRESENT key schedule, we have to step the key schedule function by
150 // NumPresentRounds forwards to get the decryption key.
151 0/1 ==> otp_dec_key_lut[k] =
152 prim_cipher_pkg::present_get_dec_key128(rnd_cnst_key_anchor[k], NumRounds);
153 end
154
155 0/1 ==> for (int k = 0; k < NumDigestSets; k++) begin
156 0/1 ==> digest_const_lut[k] = rnd_cnst_digest_anchor[k];
157 0/1 ==> digest_iv_lut[k] = rnd_cnst_digest_iv_anchor[k];
158 end
159 end
160 `ASSERT_KNOWN(EncKeyLutKnown_A, otp_enc_key_lut)
161 `ASSERT_KNOWN(DecKeyLutKnown_A, otp_dec_key_lut)
162 `ASSERT_KNOWN(DigestConstLutKnown_A, digest_const_lut)
163 `ASSERT_KNOWN(DigestIvLutKnown_A, digest_iv_lut)
164
165 //////////////
166 // Datapath //
167 //////////////
168
169 logic [4:0] idx_state_d, idx_state_q;
170 logic [ScrmblKeyWidth-1:0] key_state_d, key_state_q;
171 logic [ScrmblBlockWidth-1:0] data_state_d, data_state_q, data_shadow_q;
172 logic [ScrmblBlockWidth-1:0] digest_state_d, digest_state_q;
173 logic [ScrmblBlockWidth-1:0] enc_data_out, enc_data_out_xor, dec_data_out;
174 logic [ScrmblKeyWidth-1:0] dec_key_out, enc_key_out;
175 logic [4:0] dec_idx_out, enc_idx_out;
176 logic [ScrmblKeyWidth-1:0] otp_digest_const_mux, otp_enc_key_mux, otp_dec_key_mux;
177 logic [ScrmblBlockWidth-1:0] otp_digest_iv_mux;
178
179 typedef enum logic [2:0] {SelEncDataOut,
180 SelDecDataOut,
181 SelDigestState,
182 SelEncDataOutXor,
183 SelDataInput} data_state_sel_e;
184
185 typedef enum logic [2:0] {SelDecKeyOut,
186 SelEncKeyOut,
187 SelDecKeyInit,
188 SelEncKeyInit,
189 SelDigestConst,
190 SelDigestInput,
191 SelDigestChained} key_state_sel_e;
192
193 logic digest_init;
194 data_state_sel_e data_state_sel;
195 key_state_sel_e key_state_sel;
196 logic data_state_en, data_shadow_copy, data_shadow_load, digest_state_en, key_state_en;
197 digest_mode_e digest_mode_d, digest_mode_q;
198
199 1/1 assign otp_enc_key_mux = otp_enc_key_lut[ScrmblKeySelWidth'(sel_i)];
Tests: T1 T2 T3
200 1/1 assign otp_dec_key_mux = otp_dec_key_lut[ScrmblKeySelWidth'(sel_i)];
Tests: T1 T2 T3
201 1/1 assign otp_digest_const_mux = digest_const_lut[DigestSetSelWidth'(sel_i)];
Tests: T1 T2 T3
202 1/1 assign otp_digest_iv_mux = digest_iv_lut[DigestSetSelWidth'(sel_i)];
Tests: T1 T2 T3
203
204 // Make sure we always select a valid key / digest constant.
205 `ASSERT(CheckNumEncKeys_A, key_state_sel == SelEncKeyInit |-> sel_i < NumScrmblKeys)
206 `ASSERT(CheckNumDecKeys_A, key_state_sel == SelDecKeyInit |-> sel_i < NumScrmblKeys)
207 `ASSERT(CheckNumDigest1_A, key_state_sel == SelDigestConst |-> sel_i < NumDigestSets)
208
209 1/1 assign data_state_d = (data_state_sel == SelEncDataOut) ? enc_data_out :
Tests: T1 T2 T3
210 (data_state_sel == SelDecDataOut) ? dec_data_out :
211 (data_state_sel == SelDigestState) ? digest_state_q :
212 (data_state_sel == SelEncDataOutXor) ? enc_data_out_xor :
213 data_i;
214
215 1/1 assign key_state_d = (key_state_sel == SelDecKeyOut) ? dec_key_out :
Tests: T1 T2 T3
216 (key_state_sel == SelEncKeyOut) ? enc_key_out :
217 (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux :
218 (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux :
219 (key_state_sel == SelDigestConst) ? otp_digest_const_mux :
220 (key_state_sel == SelDigestChained) ? {data_state_q, data_shadow_q} :
221 {data_i, data_shadow_q};
222
223 // Initialize the round index state with 1 in all cases, except for the decrypt operation.
224 1/1 assign idx_state_d = (key_state_sel == SelDecKeyOut) ? dec_idx_out :
Tests: T1 T2 T3
225 (key_state_sel == SelEncKeyOut) ? enc_idx_out :
226 (key_state_sel == SelDecKeyInit) ? unsigned'(5'(NumPresentRounds)) :
227 5'd1;
228
229 // The XOR is for the Davies-Mayer one-way function construction.
230 1/1 assign enc_data_out_xor = enc_data_out ^ digest_state_q;
Tests: T1 T2 T3
231 1/1 assign digest_state_d = (digest_init) ? otp_digest_iv_mux : enc_data_out_xor;
Tests: T1 T2 T3
232
233 logic valid_q; //valid_d defined below
234 1/1 assign data_o = (valid_q) ? data_state_q : 0;
Tests: T1 T2 T3
235
236 /////////
237 // FSM //
238 /////////
239
240 // SEC_CM: SCRMBL.FSM.SPARSE
241 // Encoding generated with:
242 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \
243 // -s 2193087944 --language=sv
244 //
245 // Hamming distance histogram:
246 //
247 // 0: --
248 // 1: --
249 // 2: --
250 // 3: --
251 // 4: --
252 // 5: |||||||||||||||||||| (60.00%)
253 // 6: ||||||||||||| (40.00%)
254 // 7: --
255 // 8: --
256 // 9: --
257 //
258 // Minimum Hamming distance: 5
259 // Maximum Hamming distance: 6
260 // Minimum Hamming weight: 4
261 // Maximum Hamming weight: 7
262 //
263 localparam int StateWidth = 9;
264 typedef enum logic [StateWidth-1:0] {
265 IdleSt = 9'b100011001,
266 DecryptSt = 9'b101101111,
267 EncryptSt = 9'b010010111,
268 DigestSt = 9'b111000010,
269 ErrorSt = 9'b011111000
270 } state_e;
271
272 localparam int CntWidth = $clog2(NumPresentRounds+1);
273 localparam int unsigned LastPresentRoundInt = NumPresentRounds - 1;
274 localparam bit [CntWidth-1:0] LastPresentRound = LastPresentRoundInt[CntWidth-1:0];
275
276 state_e state_d, state_q;
277 logic [CntWidth-1:0] cnt;
278 logic cnt_clr, cnt_en, cnt_err;
279 logic valid_d; //valid_q defined above
280
281 1/1 assign valid_o = valid_q;
Tests: T1 T2 T3
282
283 // SEC_CM: SCRMBL.CTR.REDUN
284 prim_count #(
285 .Width(CntWidth)
286 ) u_prim_count (
287 .clk_i,
288 .rst_ni,
289 .clr_i(cnt_clr),
290 .set_i(1'b0),
291 .set_cnt_i('0),
292 .incr_en_i(cnt_en),
293 .decr_en_i(1'b0),
294 .step_i(CntWidth'(1)),
295 .commit_i(1'b1),
296 .cnt_o(cnt),
297 .cnt_after_commit_o(),
298 .err_o(cnt_err)
299 );
300
301 always_comb begin : p_fsm
302 1/1 state_d = state_q;
Tests: T1 T2 T3
303 1/1 digest_mode_d = digest_mode_q;
Tests: T1 T2 T3
304 1/1 data_state_sel = SelDataInput;
Tests: T1 T2 T3
305 1/1 key_state_sel = SelDigestInput;
Tests: T1 T2 T3
306 1/1 digest_init = 1'b0;
Tests: T1 T2 T3
307 1/1 data_state_en = 1'b0;
Tests: T1 T2 T3
308 1/1 data_shadow_copy = 1'b0;
Tests: T1 T2 T3
309 1/1 data_shadow_load = 1'b0;
Tests: T1 T2 T3
310 1/1 key_state_en = 1'b0;
Tests: T1 T2 T3
311 1/1 digest_state_en = 1'b0;
Tests: T1 T2 T3
312 1/1 cnt_en = 1'b0;
Tests: T1 T2 T3
313 1/1 cnt_clr = 1'b0;
Tests: T1 T2 T3
314 1/1 valid_d = 1'b0;
Tests: T1 T2 T3
315 1/1 ready_o = 1'b0;
Tests: T1 T2 T3
316 1/1 fsm_err_o = 1'b0;
Tests: T1 T2 T3
317
318 1/1 unique case (state_q)
Tests: T1 T2 T3
319 ///////////////////////////////////////////////////////////////////
320 // Idle State: decode command and
321 // load working regs accordingly
322 IdleSt: begin
323 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
324 1/1 ready_o = 1'b1;
Tests: T1 T2 T3
325
326 1/1 if (valid_i) begin
Tests: T1 T2 T3
327 1/1 unique case (cmd_i)
Tests: T1 T2 T3
328 Decrypt: begin
329 1/1 state_d = DecryptSt;
Tests: T1 T2 T3
330 1/1 key_state_sel = SelDecKeyInit;
Tests: T1 T2 T3
331 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
332 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
333 end
334 Encrypt: begin
335 1/1 state_d = EncryptSt;
Tests: T1 T2 T3
336 1/1 key_state_sel = SelEncKeyInit;
Tests: T1 T2 T3
337 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
338 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
339 end
340 LoadShadow: begin
341 1/1 if (digest_mode_q == ChainedMode) begin
Tests: T1 T2 T3
342 1/1 data_shadow_copy = 1'b1;
Tests: T1 T2 T3
343 end else begin
344 1/1 data_shadow_load = 1'b1;
Tests: T1 T2 T3
345 end
346 end
347 Digest: begin
348 1/1 state_d = DigestSt;
Tests: T1 T2 T3
349 1/1 data_state_sel = SelDigestState;
Tests: T1 T2 T3
350 1/1 key_state_sel = (digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput;
Tests: T1 T2 T3
351 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
352 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
353 end
354 DigestInit: begin
355 1/1 digest_mode_d = mode_i;
Tests: T1 T2 T3
356 1/1 digest_init = 1'b1;
Tests: T1 T2 T3
357 1/1 digest_state_en = 1'b1;
Tests: T1 T2 T3
358 end
359 DigestFinalize: begin
360 1/1 state_d = DigestSt;
Tests: T1 T2 T3
361 1/1 data_state_sel = SelDigestState;
Tests: T1 T2 T3
362 1/1 key_state_sel = SelDigestConst;
Tests: T1 T2 T3
363 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
364 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
365 1/1 digest_mode_d = StandardMode;
Tests: T1 T2 T3
366 end
367 default: ; // ignore
Exclude Annotation: VC_COV_UNR
368 endcase // cmd_i
369 end
MISSING_ELSE
370 end
371 ///////////////////////////////////////////////////////////////////
372 // Perform decrypt rounds.
373 DecryptSt: begin
374 1/1 data_state_sel = SelDecDataOut;
Tests: T1 T2 T3
375 1/1 key_state_sel = SelDecKeyOut;
Tests: T1 T2 T3
376 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
377 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
378 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
379 1/1 if (cnt == LastPresentRound) begin
Tests: T1 T2 T3
380 1/1 state_d = IdleSt;
Tests: T1 T2 T3
381 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
382 end
MISSING_ELSE
383 end
384 ///////////////////////////////////////////////////////////////////
385 // Perform encrypt rounds.
386 EncryptSt: begin
387 1/1 data_state_sel = SelEncDataOut;
Tests: T1 T2 T3
388 1/1 key_state_sel = SelEncKeyOut;
Tests: T1 T2 T3
389 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
390 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
391 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
392 1/1 if (cnt == LastPresentRound) begin
Tests: T1 T2 T3
393 1/1 state_d = IdleSt;
Tests: T1 T2 T3
394 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
395 end
MISSING_ELSE
396 end
397 ///////////////////////////////////////////////////////////////////
398 // The digest is calculated with a Merkle-Damgard construction that
399 // employs the PRESENT encryption datapath.
400 DigestSt: begin
401 1/1 data_state_sel = SelEncDataOut;
Tests: T1 T2 T3
402 1/1 key_state_sel = SelEncKeyOut;
Tests: T1 T2 T3
403 1/1 data_state_en = 1'b1;
Tests: T1 T2 T3
404 1/1 key_state_en = 1'b1;
Tests: T1 T2 T3
405 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
406 1/1 if (cnt == LastPresentRound) begin
Tests: T1 T2 T3
407 1/1 state_d = IdleSt;
Tests: T1 T2 T3
408 1/1 valid_d = 1'b1;
Tests: T1 T2 T3
409 // Apply XOR for Davies-Meyer construction.
410 1/1 data_state_sel = SelEncDataOutXor;
Tests: T1 T2 T3
411 // Backup digest state for next round of updates. We can't keep this state in the
412 // data state register as a digest may be calculated together with encryption
413 // operations in an interleaved way.
414 1/1 digest_state_en = 1'b1;
Tests: T1 T2 T3
415 end
MISSING_ELSE
416 end
417 ///////////////////////////////////////////////////////////////////
418 // Terminal error state. This raises an alert.
419 ErrorSt: begin
420 1/1 fsm_err_o = 1'b1;
Tests: T9 T94 T96
421 end
422 ///////////////////////////////////////////////////////////////////
423 // This should never happen, hence we directly jump into the
424 // error state, where an alert will be triggered.
425 default: begin
426 state_d = ErrorSt;
427 fsm_err_o = 1'b1;
428 end
429 ///////////////////////////////////////////////////////////////////
430 endcase // state_q
431
432 // Unconditionally jump into the terminal error state in case of escalation.
433 // SEC_CM: SCRMBL.FSM.LOCAL_ESC, SCRMBL.FSM.GLOBAL_ESC
434 1/1 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin
Tests: T1 T2 T3
435 1/1 state_d = ErrorSt;
Tests: T9 T94 T96
436 1/1 fsm_err_o = 1'b1;
Tests: T9 T94 T96
437 end
MISSING_ELSE
438 end
439
440 /////////////////////////////
441 // PRESENT DEC/ENC Modules //
442 /////////////////////////////
443
444 prim_present #(
445 .KeyWidth(128),
446 .NumRounds(NumPresentRounds),
447 .NumPhysRounds(1)
448 ) u_prim_present_enc (
449 .data_i ( data_state_q ),
450 .key_i ( key_state_q ),
451 .idx_i ( idx_state_q ),
452 .data_o ( enc_data_out ),
453 .key_o ( enc_key_out ),
454 .idx_o ( enc_idx_out )
455 );
456
457 prim_present #(
458 .KeyWidth(128),
459 // We are using an iterative full-round implementation here.
460 .NumRounds(NumPresentRounds),
461 .NumPhysRounds(1),
462 .Decrypt(1)
463 ) u_prim_present_dec (
464 .data_i ( data_state_q ),
465 .key_i ( key_state_q ),
466 .idx_i ( idx_state_q ),
467 .data_o ( dec_data_out ),
468 .key_o ( dec_key_out ),
469 .idx_o ( dec_idx_out )
470 );
471
472 ///////////////
473 // Registers //
474 ///////////////
475
476 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt)
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt):
476.1 `ifdef SIMULATION
476.2 prim_sparse_fsm_flop #(
476.3 .StateEnumT(state_e),
476.4 .Width($bits(state_e)),
476.5 .ResetValue($bits(state_e)'(IdleSt)),
476.6 .EnableAlertTriggerSVA(1),
476.7 .CustomForceName("state_q")
476.8 ) u_state_regs (
476.9 .clk_i ( clk_i ),
476.10 .rst_ni ( rst_ni ),
476.11 .state_i ( state_d ),
476.12 .state_o ( )
476.13 );
476.14 always_ff @(posedge clk_i or negedge rst_ni) begin
476.15 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
476.16 1/1 state_q <= IdleSt;
Tests: T1 T2 T3
476.17 end else begin
476.18 1/1 state_q <= state_d;
Tests: T1 T2 T3
476.19 end
476.20 end
476.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))
476.22 else begin
476.23 `ifdef UVM
476.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE,
476.25 "../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv", 476, "", 1);
476.26 `else
476.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,
476.28 `PRIM_STRINGIFY(u_state_regs_A));
476.29 `endif
476.30 end
476.31 `else
476.32 prim_sparse_fsm_flop #(
476.33 .StateEnumT(state_e),
476.34 .Width($bits(state_e)),
476.35 .ResetValue($bits(state_e)'(IdleSt)),
476.36 .EnableAlertTriggerSVA(1)
476.37 ) u_state_regs (
476.38 .clk_i ( `PRIM_FLOP_CLK ),
476.39 .rst_ni ( `PRIM_FLOP_RST ),
476.40 .state_i ( state_d ),
476.41 .state_o ( state_q )
476.42 );
476.43 `endif477
478 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
479 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
480 1/1 key_state_q <= '0;
Tests: T1 T2 T3
481 1/1 idx_state_q <= '0;
Tests: T1 T2 T3
482 1/1 data_state_q <= '0;
Tests: T1 T2 T3
483 1/1 data_shadow_q <= '0;
Tests: T1 T2 T3
484 1/1 digest_state_q <= '0;
Tests: T1 T2 T3
485 1/1 valid_q <= 1'b0;
Tests: T1 T2 T3
486 1/1 digest_mode_q <= StandardMode;
Tests: T1 T2 T3
487 end else begin
488 1/1 valid_q <= valid_d;
Tests: T1 T2 T3
489 1/1 digest_mode_q <= digest_mode_d;
Tests: T1 T2 T3
490
491 // enable regs
492 1/1 if (key_state_en) begin
Tests: T1 T2 T3
493 1/1 key_state_q <= key_state_d;
Tests: T1 T2 T3
494 1/1 idx_state_q <= idx_state_d;
Tests: T1 T2 T3
495 end
MISSING_ELSE
496 1/1 if (data_state_en) begin
Tests: T1 T2 T3
497 1/1 data_state_q <= data_state_d;
Tests: T1 T2 T3
498 end
MISSING_ELSE
499 1/1 if (data_shadow_copy) begin
Tests: T1 T2 T3
500 1/1 data_shadow_q <= data_state_q;
Tests: T1 T2 T3
501 1/1 end else if (data_shadow_load) begin
Tests: T1 T2 T3
502 1/1 data_shadow_q <= data_state_d;
Tests: T1 T2 T3
503 end
MISSING_ELSE
504 1/1 if (digest_state_en) begin
Tests: T1 T2 T3
505 1/1 digest_state_q <= digest_state_d;
Tests: T1 T2 T3
506 end
MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl
| Total | Covered | Percent |
|---|
| Conditions | 68 | 68 | 100.00 |
| Logical | 68 | 68 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 209
EXPRESSION
Number Term
1 (data_state_sel == SelEncDataOut) ? enc_data_out : ((data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION (data_state_sel == SelEncDataOut)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION
Number Term
1 (data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION (data_state_sel == SelDecDataOut)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION (data_state_sel == SelDigestState)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)
------------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 209
SUB-EXPRESSION (data_state_sel == SelEncDataOutXor)
------------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
EXPRESSION
Number Term
1 (key_state_sel == SelDecKeyOut) ? dec_key_out : ((key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION
Number Term
1 (key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION
Number Term
1 (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION
Number Term
1 (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelEncKeyInit)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION
Number Term
1 (key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelDigestConst)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 215
SUB-EXPRESSION (key_state_sel == SelDigestChained)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
EXPRESSION
Number Term
1 (key_state_sel == SelDecKeyOut) ? dec_idx_out : ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1))
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 231
EXPRESSION (digest_init ? otp_digest_iv_mux : enc_data_out_xor)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 234
EXPRESSION (valid_q ? data_state_q : 0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 341
EXPRESSION (digest_mode_q == ChainedMode)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 350
EXPRESSION ((digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 350
SUB-EXPRESSION (digest_mode_q == ChainedMode)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 379
EXPRESSION (cnt == LastPresentRound)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 392
EXPRESSION (cnt == LastPresentRound)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 406
EXPRESSION (cnt == LastPresentRound)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
5 |
5 |
100.00 |
(Not included in score) |
| Transitions |
10 |
10 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DecryptSt |
329 |
Covered |
T1,T2,T3 |
| DigestSt |
348 |
Covered |
T1,T2,T3 |
| EncryptSt |
335 |
Covered |
T1,T2,T3 |
| ErrorSt |
435 |
Covered |
T9,T94,T96 |
| IdleSt |
380 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| DecryptSt->ErrorSt |
435 |
Covered |
T100,T156,T284 |
| DecryptSt->IdleSt |
380 |
Covered |
T1,T2,T3 |
| DigestSt->ErrorSt |
435 |
Covered |
T173,T105,T148 |
| DigestSt->IdleSt |
407 |
Covered |
T1,T2,T3 |
| EncryptSt->ErrorSt |
435 |
Covered |
T153,T16,T155 |
| EncryptSt->IdleSt |
393 |
Covered |
T1,T2,T3 |
| IdleSt->DecryptSt |
329 |
Covered |
T1,T2,T3 |
| IdleSt->DigestSt |
348 |
Covered |
T1,T2,T3 |
| IdleSt->EncryptSt |
335 |
Covered |
T1,T2,T3 |
| IdleSt->ErrorSt |
435 |
Covered |
T9,T94,T96 |
Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl
| Line No. | Total | Covered | Percent |
| Branches |
|
51 |
51 |
100.00 |
| TERNARY |
209 |
5 |
5 |
100.00 |
| TERNARY |
215 |
7 |
7 |
100.00 |
| TERNARY |
224 |
4 |
4 |
100.00 |
| TERNARY |
231 |
2 |
2 |
100.00 |
| TERNARY |
234 |
2 |
2 |
100.00 |
| CASE |
318 |
17 |
17 |
100.00 |
| IF |
434 |
2 |
2 |
100.00 |
| IF |
476 |
2 |
2 |
100.00 |
| IF |
479 |
10 |
10 |
100.00 |
209 assign data_state_d = (data_state_sel == SelEncDataOut) ? enc_data_out :
-1-
==>
210 (data_state_sel == SelDecDataOut) ? dec_data_out :
-2-
==>
211 (data_state_sel == SelDigestState) ? digest_state_q :
-3-
==>
212 (data_state_sel == SelEncDataOutXor) ? enc_data_out_xor :
-4-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
215 assign key_state_d = (key_state_sel == SelDecKeyOut) ? dec_key_out :
-1-
==>
216 (key_state_sel == SelEncKeyOut) ? enc_key_out :
-2-
==>
217 (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux :
-3-
==>
218 (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux :
-4-
==>
219 (key_state_sel == SelDigestConst) ? otp_digest_const_mux :
-5-
==>
220 (key_state_sel == SelDigestChained) ? {data_state_q, data_shadow_q} :
-6-
==>
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
224 assign idx_state_d = (key_state_sel == SelDecKeyOut) ? dec_idx_out :
-1-
==>
225 (key_state_sel == SelEncKeyOut) ? enc_idx_out :
-2-
==>
226 (key_state_sel == SelDecKeyInit) ? unsigned'(5'(NumPresentRounds)) :
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
231 assign digest_state_d = (digest_init) ? otp_digest_iv_mux : enc_data_out_xor;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
234 assign data_o = (valid_q) ? data_state_q : 0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
318 unique case (state_q)
-1-
319 ///////////////////////////////////////////////////////////////////
320 // Idle State: decode command and
321 // load working regs accordingly
322 IdleSt: begin
323 cnt_clr = 1'b1;
324 ready_o = 1'b1;
325
326 if (valid_i) begin
-2-
327 unique case (cmd_i)
-3-
328 Decrypt: begin
329 state_d = DecryptSt;
==>
330 key_state_sel = SelDecKeyInit;
331 data_state_en = 1'b1;
332 key_state_en = 1'b1;
333 end
334 Encrypt: begin
335 state_d = EncryptSt;
==>
336 key_state_sel = SelEncKeyInit;
337 data_state_en = 1'b1;
338 key_state_en = 1'b1;
339 end
340 LoadShadow: begin
341 if (digest_mode_q == ChainedMode) begin
-4-
342 data_shadow_copy = 1'b1;
==>
343 end else begin
344 data_shadow_load = 1'b1;
==>
345 end
346 end
347 Digest: begin
348 state_d = DigestSt;
349 data_state_sel = SelDigestState;
350 key_state_sel = (digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput;
-5-
==>
==>
351 data_state_en = 1'b1;
352 key_state_en = 1'b1;
353 end
354 DigestInit: begin
355 digest_mode_d = mode_i;
==>
356 digest_init = 1'b1;
357 digest_state_en = 1'b1;
358 end
359 DigestFinalize: begin
360 state_d = DigestSt;
==>
361 data_state_sel = SelDigestState;
362 key_state_sel = SelDigestConst;
363 data_state_en = 1'b1;
364 key_state_en = 1'b1;
365 digest_mode_d = StandardMode;
366 end
367 default: ; // ignore
==> (Excluded)
Exclude Annotation: VC_COV_UNR
368 endcase // cmd_i
369 end
MISSING_ELSE
==>
370 end
371 ///////////////////////////////////////////////////////////////////
372 // Perform decrypt rounds.
373 DecryptSt: begin
374 data_state_sel = SelDecDataOut;
375 key_state_sel = SelDecKeyOut;
376 data_state_en = 1'b1;
377 key_state_en = 1'b1;
378 cnt_en = 1'b1;
379 if (cnt == LastPresentRound) begin
-6-
380 state_d = IdleSt;
==>
381 valid_d = 1'b1;
382 end
MISSING_ELSE
==>
383 end
384 ///////////////////////////////////////////////////////////////////
385 // Perform encrypt rounds.
386 EncryptSt: begin
387 data_state_sel = SelEncDataOut;
388 key_state_sel = SelEncKeyOut;
389 data_state_en = 1'b1;
390 key_state_en = 1'b1;
391 cnt_en = 1'b1;
392 if (cnt == LastPresentRound) begin
-7-
393 state_d = IdleSt;
==>
394 valid_d = 1'b1;
395 end
MISSING_ELSE
==>
396 end
397 ///////////////////////////////////////////////////////////////////
398 // The digest is calculated with a Merkle-Damgard construction that
399 // employs the PRESENT encryption datapath.
400 DigestSt: begin
401 data_state_sel = SelEncDataOut;
402 key_state_sel = SelEncKeyOut;
403 data_state_en = 1'b1;
404 key_state_en = 1'b1;
405 cnt_en = 1'b1;
406 if (cnt == LastPresentRound) begin
-8-
407 state_d = IdleSt;
==>
408 valid_d = 1'b1;
409 // Apply XOR for Davies-Meyer construction.
410 data_state_sel = SelEncDataOutXor;
411 // Backup digest state for next round of updates. We can't keep this state in the
412 // data state register as a digest may be calculated together with encryption
413 // operations in an interleaved way.
414 digest_state_en = 1'b1;
415 end
MISSING_ELSE
==>
416 end
417 ///////////////////////////////////////////////////////////////////
418 // Terminal error state. This raises an alert.
419 ErrorSt: begin
420 fsm_err_o = 1'b1;
==>
421 end
422 ///////////////////////////////////////////////////////////////////
423 // This should never happen, hence we directly jump into the
424 // error state, where an alert will be triggered.
425 default: begin
426 state_d = ErrorSt;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
| IdleSt |
1 |
Decrypt |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
1 |
Encrypt |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
1 |
LoadShadow |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
1 |
LoadShadow |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
1 |
Digest |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
1 |
Digest |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
1 |
DigestInit |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
1 |
DigestFinalize |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| IdleSt |
1 |
default |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| DecryptSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T1,T2,T3 |
|
| DecryptSt |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
|
| EncryptSt |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T3 |
|
| EncryptSt |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T1,T2,T3 |
|
| DigestSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
|
| DigestSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
|
| ErrorSt |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T94,T96 |
|
| default |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26,T27,T28 |
|
434 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin
-1-
435 state_d = ErrorSt;
==>
436 fsm_err_o = 1'b1;
437 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T9,T94,T96 |
| 0 |
Covered |
T1,T2,T3 |
476 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
479 if (!rst_ni) begin
-1-
480 key_state_q <= '0;
==>
481 idx_state_q <= '0;
482 data_state_q <= '0;
483 data_shadow_q <= '0;
484 digest_state_q <= '0;
485 valid_q <= 1'b0;
486 digest_mode_q <= StandardMode;
487 end else begin
488 valid_q <= valid_d;
489 digest_mode_q <= digest_mode_d;
490
491 // enable regs
492 if (key_state_en) begin
-2-
493 key_state_q <= key_state_d;
==>
494 idx_state_q <= idx_state_d;
495 end
MISSING_ELSE
==>
496 if (data_state_en) begin
-3-
497 data_state_q <= data_state_d;
==>
498 end
MISSING_ELSE
==>
499 if (data_shadow_copy) begin
-4-
500 data_shadow_q <= data_state_q;
==>
501 end else if (data_shadow_load) begin
-5-
502 data_shadow_q <= data_state_d;
==>
503 end
MISSING_ELSE
==>
504 if (digest_state_en) begin
-6-
505 digest_state_q <= digest_state_d;
==>
506 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
0 |
0 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl
Assertion Details
CheckNumDecKeys_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
232989 |
0 |
0 |
| T1 |
5120 |
24 |
0 |
0 |
| T2 |
12798 |
56 |
0 |
0 |
| T3 |
10127 |
59 |
0 |
0 |
| T4 |
55214 |
250 |
0 |
0 |
| T5 |
18048 |
75 |
0 |
0 |
| T9 |
22622 |
51 |
0 |
0 |
| T10 |
59751 |
48 |
0 |
0 |
| T11 |
4514 |
24 |
0 |
0 |
| T12 |
12039 |
77 |
0 |
0 |
| T13 |
47890 |
72 |
0 |
0 |
CheckNumDigest1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
112303 |
0 |
0 |
| T1 |
5120 |
7 |
0 |
0 |
| T2 |
12798 |
27 |
0 |
0 |
| T3 |
10127 |
8 |
0 |
0 |
| T4 |
55214 |
114 |
0 |
0 |
| T5 |
18048 |
34 |
0 |
0 |
| T9 |
22622 |
15 |
0 |
0 |
| T10 |
59751 |
5 |
0 |
0 |
| T11 |
4514 |
5 |
0 |
0 |
| T12 |
12039 |
15 |
0 |
0 |
| T13 |
47890 |
5 |
0 |
0 |
CheckNumEncKeys_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
244026 |
0 |
0 |
| T1 |
5120 |
24 |
0 |
0 |
| T2 |
12798 |
53 |
0 |
0 |
| T3 |
10127 |
40 |
0 |
0 |
| T4 |
55214 |
237 |
0 |
0 |
| T5 |
18048 |
100 |
0 |
0 |
| T9 |
22622 |
76 |
0 |
0 |
| T10 |
59751 |
48 |
0 |
0 |
| T11 |
4514 |
24 |
0 |
0 |
| T12 |
12039 |
62 |
0 |
0 |
| T13 |
47890 |
24 |
0 |
0 |
DecKeyLutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
DigestConstLutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
DigestIvLutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
EncKeyLutKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |
NumMaxPresentRounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1114 |
1114 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84443599 |
83613730 |
0 |
0 |
| T1 |
5120 |
5042 |
0 |
0 |
| T2 |
12798 |
12610 |
0 |
0 |
| T3 |
10127 |
9822 |
0 |
0 |
| T4 |
55214 |
54147 |
0 |
0 |
| T5 |
18048 |
17835 |
0 |
0 |
| T9 |
22622 |
22337 |
0 |
0 |
| T10 |
59751 |
59694 |
0 |
0 |
| T11 |
4514 |
4458 |
0 |
0 |
| T12 |
12039 |
11780 |
0 |
0 |
| T13 |
47890 |
47829 |
0 |
0 |