Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4172638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2326591

1

T1

10

T2

184

T3

1088

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5512780	1			T1	4		T2	459		T3	3660
values[0x0]	470930	1			T1	3		T2	93		T3	135
values[0x1]	515519	1			T1	12		T2	101		T3	128

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3084257	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3414972

1

T1

12

T2

300

T3

1854

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21944	1			T3	16		T4	9		T6	15
valid_sources[0x01]	21312	1			T3	14		T4	7		T6	16
valid_sources[0x02]	20475	1			T3	18		T4	37		T6	19
valid_sources[0x03]	20478	1			T3	6		T4	5		T6	11
valid_sources[0x04]	21286	1			T1	1		T3	7		T4	9
valid_sources[0x05]	31700	1			T3	26		T4	34		T6	17
valid_sources[0x06]	35437	1			T3	6		T4	9		T6	8
valid_sources[0x07]	20444	1			T3	20		T6	12		T22	29
valid_sources[0x08]	33916	1			T3	25		T4	23		T6	17
valid_sources[0x09]	22331	1			T3	18		T4	14		T6	16
valid_sources[0x0a]	24540	1			T3	17		T4	16		T6	21
valid_sources[0x0b]	25820	1			T2	60		T3	12		T4	8
valid_sources[0x0c]	20487	1			T3	6		T4	8		T6	15
valid_sources[0x0d]	21217	1			T3	27		T4	27		T6	11
valid_sources[0x0e]	20194	1			T3	15		T4	8		T6	11
valid_sources[0x0f]	22056	1			T3	13		T4	5		T6	11
valid_sources[0x10]	20218	1			T3	13		T4	2		T6	18
valid_sources[0x11]	22665	1			T3	8		T4	4		T6	14
valid_sources[0x12]	20857	1			T3	14		T4	9		T6	15
valid_sources[0x13]	20580	1			T3	12		T4	7		T6	15
valid_sources[0x14]	24788	1			T3	20		T4	1		T6	19
valid_sources[0x15]	23353	1			T3	13		T4	28		T6	15
valid_sources[0x16]	19710	1			T1	3		T3	9		T4	17
valid_sources[0x17]	21258	1			T3	10		T4	12		T6	13
valid_sources[0x18]	20115	1			T3	13		T4	14		T6	9
valid_sources[0x19]	20709	1			T3	12		T4	22		T6	11
valid_sources[0x1a]	26122	1			T3	16		T4	9		T6	8
valid_sources[0x1b]	29093	1			T3	17		T4	9		T6	14
valid_sources[0x1c]	20461	1			T3	3		T4	10		T6	18
valid_sources[0x1d]	22854	1			T3	13		T4	6		T6	22
valid_sources[0x1e]	21588	1			T3	16		T4	6		T6	16
valid_sources[0x1f]	28779	1			T3	9		T4	12		T6	20
valid_sources[0x20]	19977	1			T3	24		T4	9		T6	9
valid_sources[0x21]	22222	1			T3	47		T4	9		T6	22
valid_sources[0x22]	27173	1			T3	17		T6	11		T22	24
valid_sources[0x23]	20627	1			T3	9		T4	16		T6	19
valid_sources[0x24]	19990	1			T3	19		T4	3		T6	12
valid_sources[0x25]	20566	1			T3	3		T4	17		T6	14
valid_sources[0x26]	37631	1			T3	14		T4	4		T6	16
valid_sources[0x27]	19966	1			T3	9		T4	6		T6	8
valid_sources[0x28]	19990	1			T3	20		T4	8		T6	15
valid_sources[0x29]	20261	1			T3	29		T6	11		T22	40
valid_sources[0x2a]	23574	1			T3	7		T4	8		T6	14
valid_sources[0x2b]	26291	1			T3	19		T4	24		T6	17
valid_sources[0x2c]	33041	1			T3	7		T4	41		T6	19
valid_sources[0x2d]	21774	1			T3	21		T4	11		T6	8
valid_sources[0x2e]	29538	1			T3	14		T4	9		T6	17
valid_sources[0x2f]	20513	1			T3	30		T4	6		T6	10
valid_sources[0x30]	28843	1			T3	14		T4	12		T6	4
valid_sources[0x31]	31272	1			T3	10		T4	4		T6	16
valid_sources[0x32]	29050	1			T3	6		T4	16		T6	12
valid_sources[0x33]	20511	1			T3	15		T4	6		T6	13
valid_sources[0x34]	21042	1			T3	14		T4	6		T6	14
valid_sources[0x35]	27662	1			T3	18		T4	22		T6	21
valid_sources[0x36]	24934	1			T3	12		T4	8		T6	16
valid_sources[0x37]	20157	1			T3	5		T6	17		T22	13
valid_sources[0x38]	21923	1			T3	19		T4	5		T6	5
valid_sources[0x39]	20048	1			T3	13		T4	9		T6	13
valid_sources[0x3a]	23100	1			T3	21		T4	27		T6	20
valid_sources[0x3b]	20971	1			T3	21		T4	6		T6	15
valid_sources[0x3c]	20462	1			T3	14		T4	9		T6	20
valid_sources[0x3d]	20807	1			T3	15		T4	5		T6	14
valid_sources[0x3e]	25074	1			T3	20		T4	7		T6	14
valid_sources[0x3f]	21254	1			T3	35		T4	16		T6	21
valid_sources[0x40]	22178	1			T3	7		T4	16		T6	13
valid_sources[0x41]	20233	1			T3	15		T4	10		T6	13
valid_sources[0x42]	19810	1			T3	10		T4	19		T6	11
valid_sources[0x43]	21589	1			T1	7		T3	15		T4	3
valid_sources[0x44]	25569	1			T3	27		T4	2		T6	10
valid_sources[0x45]	20318	1			T3	15		T4	6		T6	20
valid_sources[0x46]	24659	1			T3	21		T4	4		T6	14
valid_sources[0x47]	22005	1			T2	93		T3	15		T6	15
valid_sources[0x48]	34263	1			T3	16		T4	8		T6	14
valid_sources[0x49]	19619	1			T3	13		T4	9		T6	15
valid_sources[0x4a]	23332	1			T2	15		T3	11		T4	20
valid_sources[0x4b]	34221	1			T3	16		T4	12		T6	6
valid_sources[0x4c]	20749	1			T3	14		T4	3		T6	16
valid_sources[0x4d]	29831	1			T3	29		T4	8		T6	12
valid_sources[0x4e]	20497	1			T3	10		T4	19		T6	17
valid_sources[0x4f]	20840	1			T3	17		T4	11		T6	16
valid_sources[0x50]	27478	1			T3	12		T4	6		T6	14
valid_sources[0x51]	21903	1			T3	14		T4	11		T6	16
valid_sources[0x52]	21189	1			T3	24		T4	1		T6	15
valid_sources[0x53]	21483	1			T3	12		T4	15		T6	11
valid_sources[0x54]	21274	1			T3	25		T4	14		T6	5
valid_sources[0x55]	20934	1			T3	7		T4	7		T6	21
valid_sources[0x56]	23240	1			T3	25		T4	6		T6	10
valid_sources[0x57]	23879	1			T3	4		T4	19		T6	21
valid_sources[0x58]	21032	1			T3	11		T4	9		T6	12
valid_sources[0x59]	36669	1			T3	11		T4	4		T6	11
valid_sources[0x5a]	21445	1			T3	8		T4	16		T6	14
valid_sources[0x5b]	21490	1			T3	10		T4	5		T6	17
valid_sources[0x5c]	78117	1			T3	4		T4	2		T6	8
valid_sources[0x5d]	21747	1			T3	6		T4	28		T6	9
valid_sources[0x5e]	30346	1			T3	3		T4	11		T6	18
valid_sources[0x5f]	31812	1			T3	13		T4	7		T6	8
valid_sources[0x60]	20906	1			T3	18		T4	15		T6	6
valid_sources[0x61]	23095	1			T3	17		T4	8		T6	15
valid_sources[0x62]	23095	1			T3	20		T6	17		T22	8
valid_sources[0x63]	23095	1			T3	10		T4	6		T6	14
valid_sources[0x64]	20100	1			T3	15		T4	1		T6	13
valid_sources[0x65]	21145	1			T3	10		T4	7		T6	6
valid_sources[0x66]	23926	1			T2	22		T3	11		T4	10
valid_sources[0x67]	22489	1			T3	29		T4	8		T6	19
valid_sources[0x68]	22545	1			T3	20		T4	18		T6	14
valid_sources[0x69]	21427	1			T3	19		T4	5		T6	9
valid_sources[0x6a]	20166	1			T3	14		T4	12		T6	13
valid_sources[0x6b]	37127	1			T3	15		T4	8		T6	15
valid_sources[0x6c]	19678	1			T3	19		T4	10		T6	22
valid_sources[0x6d]	20780	1			T3	10		T4	10		T6	17
valid_sources[0x6e]	33555	1			T3	18		T4	16		T6	11
valid_sources[0x6f]	23076	1			T2	24		T3	14		T4	11
valid_sources[0x70]	20265	1			T3	24		T6	20		T22	22
valid_sources[0x71]	21587	1			T2	8		T3	20		T4	8
valid_sources[0x72]	23302	1			T3	19		T4	17		T6	15
valid_sources[0x73]	29458	1			T3	5		T4	10		T6	8
valid_sources[0x74]	21924	1			T2	17		T3	12		T6	10
valid_sources[0x75]	33755	1			T3	30		T4	16		T6	10
valid_sources[0x76]	24516	1			T3	7		T4	7		T6	17
valid_sources[0x77]	20306	1			T3	27		T4	1		T6	19
valid_sources[0x78]	34653	1			T3	3		T4	3		T6	16
valid_sources[0x79]	20930	1			T3	18		T4	23		T6	16
valid_sources[0x7a]	20220	1			T3	14		T4	11		T6	25
valid_sources[0x7b]	25576	1			T3	4		T4	12		T6	15
valid_sources[0x7c]	23697	1			T3	14		T4	4		T6	13
valid_sources[0x7d]	28235	1			T3	9		T4	6		T6	14
valid_sources[0x7e]	32749	1			T3	11		T4	2		T6	7
valid_sources[0x7f]	39440	1			T3	15		T6	10		T22	31
valid_sources[0x80]	21177	1			T3	13		T4	9		T6	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1870597

1

T1

3

T2

102

T3

976

values[0x0]

all_enables

biggest_size

257971

1

T1

1

T2

47

T3

68

values[0x1]

all_enables

biggest_size

198023

1

T1

6

T2

35

T3

44

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	22352	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

404175

1

T3

40

T4

40

T6

180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142162	1			T3	20		T4	20		T6	90
values[0x0]	138937	1			T3	11		T4	8		T6	45
values[0x1]	145428	1			T3	9		T4	12		T6	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

413860

1

T3

40

T4

40

T6

180

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2640	1			T85	1		T121	1		T125	1
valid_sources[0x01]	1679	1			T85	1		T121	3		T116	2
valid_sources[0x02]	1734	1			T3	1		T90	1		T116	5
valid_sources[0x03]	1357	1			T119	1		T115	1		T10	7
valid_sources[0x04]	1781	1			T85	1		T9	1		T36	1
valid_sources[0x05]	1590	1			T24	3		T36	1		T97	2
valid_sources[0x06]	1634	1			T36	1		T116	4		T123	1
valid_sources[0x07]	1644	1			T97	5		T124	1		T118	1
valid_sources[0x08]	1673	1			T10	6		T127	1		T116	1
valid_sources[0x09]	1507	1			T85	1		T121	1		T88	1
valid_sources[0x0a]	1507	1			T115	1		T36	3		T123	2
valid_sources[0x0b]	1632	1			T90	1		T36	1		T123	1
valid_sources[0x0c]	1795	1			T9	2		T90	1		T115	1
valid_sources[0x0d]	1744	1			T4	1		T90	2		T115	3
valid_sources[0x0e]	1926	1			T10	1		T140	1		T145	7
valid_sources[0x0f]	1688	1			T92	2		T115	1		T36	1
valid_sources[0x10]	1531	1			T121	1		T126	8		T127	1
valid_sources[0x11]	1657	1			T126	1		T90	1		T10	1
valid_sources[0x12]	1422	1			T3	1		T9	1		T10	1
valid_sources[0x13]	1665	1			T85	1		T121	2		T90	1
valid_sources[0x14]	1448	1			T9	1		T116	2		T122	1
valid_sources[0x15]	1605	1			T88	6		T115	1		T36	1
valid_sources[0x16]	2043	1			T3	1		T15	6		T10	4
valid_sources[0x17]	2167	1			T4	2		T118	4		T140	1
valid_sources[0x18]	1717	1			T15	18		T114	1		T121	1
valid_sources[0x19]	1530	1			T115	2		T36	3		T127	2
valid_sources[0x1a]	1501	1			T125	1		T88	14		T116	1
valid_sources[0x1b]	1489	1			T4	1		T121	1		T115	1
valid_sources[0x1c]	1588	1			T36	1		T116	1		T249	2
valid_sources[0x1d]	1332	1			T36	1		T97	1		T283	1
valid_sources[0x1e]	1270	1			T9	4		T127	1		T116	4
valid_sources[0x1f]	1632	1			T4	5		T85	1		T36	3
valid_sources[0x20]	1462	1			T4	3		T90	3		T140	1
valid_sources[0x21]	1813	1			T121	2		T90	1		T115	1
valid_sources[0x22]	1458	1			T121	1		T115	2		T10	1
valid_sources[0x23]	1431	1			T121	1		T123	1		T249	2
valid_sources[0x24]	1418	1			T115	2		T116	1		T201	2
valid_sources[0x25]	2683	1			T121	1		T115	1		T36	1
valid_sources[0x26]	1656	1			T92	3		T36	1		T123	2
valid_sources[0x27]	1521	1			T85	1		T88	4		T36	2
valid_sources[0x28]	2050	1			T121	1		T90	1		T123	1
valid_sources[0x29]	1662	1			T85	1		T88	1		T9	2
valid_sources[0x2a]	1429	1			T125	2		T88	3		T9	1
valid_sources[0x2b]	1960	1			T121	1		T10	1		T36	1
valid_sources[0x2c]	1684	1			T125	1		T90	1		T10	3
valid_sources[0x2d]	1708	1			T3	1		T88	1		T90	1
valid_sources[0x2e]	1981	1			T119	2		T85	1		T9	1
valid_sources[0x2f]	1591	1			T92	3		T88	1		T10	7
valid_sources[0x30]	1418	1			T119	1		T90	2		T36	1
valid_sources[0x31]	1306	1			T90	1		T36	1		T116	2
valid_sources[0x32]	1509	1			T121	1		T90	1		T116	1
valid_sources[0x33]	2201	1			T85	1		T10	1		T124	4
valid_sources[0x34]	1734	1			T121	1		T88	5		T9	1
valid_sources[0x35]	1664	1			T85	1		T90	1		T36	7
valid_sources[0x36]	1505	1			T115	1		T10	3		T36	2
valid_sources[0x37]	1629	1			T90	1		T127	1		T249	9
valid_sources[0x38]	1825	1			T27	1		T201	3		T34	3
valid_sources[0x39]	1550	1			T125	1		T9	1		T90	3
valid_sources[0x3a]	1484	1			T3	1		T85	1		T88	3
valid_sources[0x3b]	1885	1			T85	1		T88	1		T90	2
valid_sources[0x3c]	1469	1			T24	3		T92	3		T85	1
valid_sources[0x3d]	1571	1			T3	1		T85	2		T121	1
valid_sources[0x3e]	1372	1			T127	2		T97	1		T169	2
valid_sources[0x3f]	1493	1			T3	1		T125	1		T36	2
valid_sources[0x40]	1813	1			T121	1		T115	1		T124	1
valid_sources[0x41]	1348	1			T121	1		T115	1		T118	1
valid_sources[0x42]	1926	1			T121	1		T125	5		T90	1
valid_sources[0x43]	1584	1			T15	5		T85	1		T10	1
valid_sources[0x44]	1467	1			T88	1		T115	2		T249	6
valid_sources[0x45]	1717	1			T119	1		T85	1		T88	3
valid_sources[0x46]	1403	1			T85	1		T121	1		T9	3
valid_sources[0x47]	1582	1			T15	39		T92	1		T85	2
valid_sources[0x48]	1761	1			T85	1		T121	1		T125	2
valid_sources[0x49]	1950	1			T4	1		T88	2		T90	1
valid_sources[0x4a]	1339	1			T36	1		T97	2		T118	2
valid_sources[0x4b]	1425	1			T85	3		T36	2		T118	1
valid_sources[0x4c]	1545	1			T3	1		T88	4		T9	1
valid_sources[0x4d]	1783	1			T88	2		T115	1		T36	2
valid_sources[0x4e]	1745	1			T115	1		T36	2		T127	1
valid_sources[0x4f]	1629	1			T9	1		T90	2		T36	2
valid_sources[0x50]	1704	1			T119	1		T121	1		T115	1
valid_sources[0x51]	1631	1			T25	2		T121	2		T125	1
valid_sources[0x52]	1649	1			T93	1		T10	2		T36	3
valid_sources[0x53]	1807	1			T85	1		T10	1		T122	1
valid_sources[0x54]	1582	1			T3	2		T121	1		T123	2
valid_sources[0x55]	1688	1			T119	1		T121	1		T88	8
valid_sources[0x56]	1442	1			T14	9		T121	1		T10	3
valid_sources[0x57]	1627	1			T125	2		T93	3		T97	13
valid_sources[0x58]	1469	1			T119	2		T90	2		T36	1
valid_sources[0x59]	1648	1			T92	12		T121	2		T115	1
valid_sources[0x5a]	1587	1			T24	3		T85	1		T9	1
valid_sources[0x5b]	2076	1			T85	1		T10	1		T36	1
valid_sources[0x5c]	1668	1			T3	1		T15	38		T85	1
valid_sources[0x5d]	1343	1			T116	1		T154	1		T203	6
valid_sources[0x5e]	1641	1			T4	4		T88	4		T115	1
valid_sources[0x5f]	1873	1			T85	2		T121	1		T36	1
valid_sources[0x60]	1737	1			T4	1		T121	1		T90	1
valid_sources[0x61]	1772	1			T90	1		T115	1		T93	1
valid_sources[0x62]	1526	1			T3	2		T4	1		T10	1
valid_sources[0x63]	1626	1			T119	1		T90	1		T115	3
valid_sources[0x64]	1359	1			T4	1		T14	2		T85	1
valid_sources[0x65]	2080	1			T85	1		T9	1		T36	1
valid_sources[0x66]	1694	1			T85	2		T88	3		T36	1
valid_sources[0x67]	1939	1			T88	2		T9	1		T10	8
valid_sources[0x68]	1480	1			T3	1		T24	1		T88	1
valid_sources[0x69]	1304	1			T85	1		T88	2		T36	2
valid_sources[0x6a]	1530	1			T90	1		T116	3		T249	6
valid_sources[0x6b]	2651	1			T121	1		T10	3		T116	1
valid_sources[0x6c]	1338	1			T4	1		T90	1		T115	1
valid_sources[0x6d]	1620	1			T24	2		T123	3		T249	1
valid_sources[0x6e]	1463	1			T3	1		T15	31		T9	1
valid_sources[0x6f]	1810	1			T88	1		T115	1		T127	1
valid_sources[0x70]	1542	1			T121	1		T90	1		T36	2
valid_sources[0x71]	1573	1			T85	3		T90	2		T97	7
valid_sources[0x72]	1426	1			T121	1		T125	2		T9	3
valid_sources[0x73]	1419	1			T92	1		T85	1		T115	1
valid_sources[0x74]	1725	1			T4	1		T90	2		T115	1
valid_sources[0x75]	1590	1			T85	3		T125	2		T126	5
valid_sources[0x76]	1622	1			T121	1		T9	1		T115	1
valid_sources[0x77]	1799	1			T3	1		T115	2		T97	2
valid_sources[0x78]	1788	1			T10	3		T249	2		T118	1
valid_sources[0x79]	1596	1			T25	3		T88	3		T115	1
valid_sources[0x7a]	1825	1			T121	1		T93	1		T36	2
valid_sources[0x7b]	1720	1			T90	1		T36	2		T127	1
valid_sources[0x7c]	1553	1			T121	1		T115	1		T36	1
valid_sources[0x7d]	1556	1			T90	1		T144	2		T281	1
valid_sources[0x7e]	1571	1			T85	3		T121	1		T90	1
valid_sources[0x7f]	1784	1			T85	1		T122	2		T123	1
valid_sources[0x80]	1709	1			T121	1		T10	3		T36	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

129969

1

T3

20

T4

20

T6

90

values[0x0]

all_enables

biggest_size

137623

1

T3

11

T4

8

T6

45

values[0x1]

all_enables

biggest_size

136583

1

T3

9

T4

12

T6

45