Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4744858

1

T1

9

T2

469

T3

2835

full_word

2361175

1

T1

10

T2

184

T3

1088

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7105743	1			T1	19		T2	653		T3	3923
auto[TlIntgErrCmd]	93	1			T288	2		T289	4		T290	5
auto[TlIntgErrData]	100	1			T288	3		T289	2		T290	3
auto[TlIntgErrBoth]	97	1			T288	5		T289	4		T290	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5555380

1

T1

4

T2

459

T3

3660

auto[1]

1550653

1

T1

15

T2

194

T3

263

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3680383	1			T1	1		T2	357		T3	2684
auto[TlIntgErrNone]	partial	auto[1]	1064212	1			T1	8		T2	112		T3	151
auto[TlIntgErrNone]	full_word	auto[0]	1874871	1			T1	3		T2	102		T3	976
auto[TlIntgErrNone]	full_word	auto[1]	486277	1			T1	7		T2	82		T3	112
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T289	2		T290	3		T297	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T288	2		T289	2		T290	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T391	1		T397	1		T398	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T298	1		T299	1		T391	2
auto[TlIntgErrData]	partial	auto[0]	42	1			T288	1		T289	1		T290	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T288	2		T289	1		T290	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T297	1		T399	1		T400	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T392	1		T400	2		T397	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T288	1		T289	1		T290	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T288	4		T289	3		T290	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T391	1		T394	1		T398	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T298	1		T299	1		T391	1