Module Definition
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Module : otp_ctrl_core_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.otp_ctrl_core_csr_assert 100.00 100.00


Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.99 94.16 95.24 96.94 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 99828645 265795 0 0
check_regwen_rd_A 99828645 1697 0 0
check_timeout_rd_A 99828645 836 0 0
check_trigger_regwen_rd_A 99828645 1772 0 0
consistency_check_period_rd_A 99828645 1744 0 0
creator_sw_cfg_read_lock_rd_A 99828645 791 0 0
direct_access_address_rd_A 99828645 162 0 0
direct_access_wdata_0_rd_A 99828645 19 0 0
direct_access_wdata_1_rd_A 99828645 29 0 0
integrity_check_period_rd_A 99828645 1688 0 0
intr_enable_rd_A 99828645 2417 0 0
owner_sw_cfg_read_lock_rd_A 99828645 843 0 0
rot_creator_auth_codesign_read_lock_rd_A 99828645 852 0 0
rot_creator_auth_state_read_lock_rd_A 99828645 948 0 0
vendor_test_read_lock_rd_A 99828645 800 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 265795 0 0
T11 63462 1344 0 0
T12 0 7387 0 0
T13 0 5619 0 0
T16 0 1706 0 0
T17 0 12903 0 0
T18 0 4906 0 0
T84 0 3888 0 0
T86 0 9608 0 0
T89 0 2099 0 0
T141 59216 0 0 0
T207 30490 0 0 0
T225 140389 0 0 0
T278 0 2893 0 0
T296 23638 0 0 0
T300 3809 0 0 0
T304 24442 0 0 0
T305 20691 0 0 0
T306 40823 0 0 0
T307 64343 0 0 0

check_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 1697 0 0
T16 100907 6 0 0
T52 10391 0 0 0
T87 0 15 0 0
T156 234430 0 0 0
T278 0 22 0 0
T279 0 24 0 0
T288 0 15 0 0
T295 0 6 0 0
T315 0 9 0 0
T340 0 17 0 0
T341 0 18 0 0
T342 0 23 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0

check_timeout_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 836 0 0
T16 100907 22 0 0
T52 10391 0 0 0
T87 0 21 0 0
T156 234430 0 0 0
T278 0 22 0 0
T279 0 21 0 0
T315 0 6 0 0
T331 0 53 0 0
T340 0 16 0 0
T341 0 17 0 0
T342 0 34 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0
T350 0 6 0 0

check_trigger_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 1772 0 0
T16 100907 10 0 0
T52 10391 0 0 0
T87 0 25 0 0
T156 234430 0 0 0
T278 0 10 0 0
T279 0 24 0 0
T288 0 20 0 0
T295 0 9 0 0
T315 0 6 0 0
T340 0 29 0 0
T341 0 18 0 0
T342 0 21 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0

consistency_check_period_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 1744 0 0
T16 100907 23 0 0
T52 10391 0 0 0
T87 0 12 0 0
T156 234430 0 0 0
T278 0 30 0 0
T279 0 8 0 0
T288 0 5 0 0
T295 0 10 0 0
T315 0 4 0 0
T340 0 29 0 0
T341 0 18 0 0
T342 0 15 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0

creator_sw_cfg_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 791 0 0
T16 100907 12 0 0
T52 10391 0 0 0
T87 0 31 0 0
T156 234430 0 0 0
T278 0 24 0 0
T279 0 14 0 0
T315 0 10 0 0
T331 0 77 0 0
T340 0 32 0 0
T341 0 10 0 0
T342 0 28 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0
T350 0 3 0 0

direct_access_address_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 162 0 0
T16 100907 12 0 0
T52 10391 0 0 0
T87 0 26 0 0
T156 234430 0 0 0
T278 0 18 0 0
T279 0 28 0 0
T315 0 5 0 0
T340 0 25 0 0
T341 0 16 0 0
T342 0 12 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0
T350 0 6 0 0
T351 0 7 0 0

direct_access_wdata_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 19 0 0
T31 11489 0 0 0
T234 26908 0 0 0
T245 504771 0 0 0
T278 187841 13 0 0
T340 0 1 0 0
T342 0 5 0 0
T352 172540 0 0 0
T353 5533 0 0 0
T354 12660 0 0 0
T355 40373 0 0 0
T356 37587 0 0 0
T357 119045 0 0 0

direct_access_wdata_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 29 0 0
T87 0 4 0 0
T243 210046 0 0 0
T279 176439 5 0 0
T287 571107 0 0 0
T313 37261 0 0 0
T314 120647 0 0 0
T340 0 11 0 0
T342 0 9 0 0
T358 21659 0 0 0
T359 4537 0 0 0
T360 74310 0 0 0
T361 47263 0 0 0
T362 40043 0 0 0

integrity_check_period_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 1688 0 0
T16 100907 9 0 0
T52 10391 0 0 0
T87 0 31 0 0
T156 234430 0 0 0
T278 0 10 0 0
T279 0 30 0 0
T288 0 22 0 0
T295 0 13 0 0
T315 0 4 0 0
T340 0 36 0 0
T341 0 4 0 0
T342 0 29 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 2417 0 0
T16 0 36 0 0
T20 105064 0 0 0
T87 0 57 0 0
T255 123467 0 0 0
T256 256459 25 0 0
T268 0 27 0 0
T272 45088 0 0 0
T278 0 27 0 0
T279 0 53 0 0
T363 0 27 0 0
T364 0 13 0 0
T365 0 18 0 0
T366 0 9 0 0
T367 197894 0 0 0
T368 99867 0 0 0
T369 86444 0 0 0
T370 5184 0 0 0
T371 50605 0 0 0
T372 127769 0 0 0

owner_sw_cfg_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 843 0 0
T16 100907 9 0 0
T52 10391 0 0 0
T87 0 23 0 0
T156 234430 0 0 0
T278 0 33 0 0
T279 0 16 0 0
T315 0 3 0 0
T331 0 57 0 0
T340 0 16 0 0
T341 0 33 0 0
T342 0 17 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0
T350 0 3 0 0

rot_creator_auth_codesign_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 852 0 0
T16 100907 13 0 0
T52 10391 0 0 0
T87 0 15 0 0
T156 234430 0 0 0
T278 0 19 0 0
T279 0 27 0 0
T315 0 2 0 0
T331 0 26 0 0
T340 0 18 0 0
T341 0 29 0 0
T342 0 24 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0
T350 0 7 0 0

rot_creator_auth_state_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 948 0 0
T16 100907 21 0 0
T52 10391 0 0 0
T87 0 31 0 0
T156 234430 0 0 0
T278 0 41 0 0
T279 0 11 0 0
T315 0 4 0 0
T331 0 62 0 0
T340 0 44 0 0
T341 0 19 0 0
T342 0 31 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0
T350 0 3 0 0

vendor_test_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 99828645 800 0 0
T16 100907 3 0 0
T52 10391 0 0 0
T87 0 7 0 0
T156 234430 0 0 0
T278 0 21 0 0
T279 0 27 0 0
T315 0 6 0 0
T331 0 25 0 0
T340 0 21 0 0
T341 0 24 0 0
T342 0 31 0 0
T343 12994 0 0 0
T344 20949 0 0 0
T345 71130 0 0 0
T346 40479 0 0 0
T347 4707 0 0 0
T348 43488 0 0 0
T349 83355 0 0 0
T350 0 1 0 0

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