Module Definition
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Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.95 100.00 100.00 51.81 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.16 100.00 89.61 100.00 91.18 100.00 u_otp_ctrl_lfsr_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_double_lfsr[0].u_prim_buf_input 100.00 100.00
gen_double_lfsr[0].u_prim_buf_output 100.00 100.00
gen_double_lfsr[0].u_prim_lfsr 51.81 51.81
gen_double_lfsr[1].u_prim_buf_input 100.00 100.00
gen_double_lfsr[1].u_prim_buf_output 100.00 100.00
gen_double_lfsr[1].u_prim_lfsr 51.81 51.81


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_double_lfsr
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00

101 // Output the state from the first LFSR 102 1/1 assign state_o = lfsr_state[0][StateOutDw-1:0]; Tests: T1 T2 T3  103 1/1 assign err_o = lfsr_state[0] != lfsr_state[1]; Tests: T1 T2 T3 

Cond Coverage for Module : prim_double_lfsr
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       103
 EXPRESSION (lfsr_state[0] != lfsr_state[1])
            ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T20,T21

Assert Coverage for Module : prim_double_lfsr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1109 1109 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1109 1109 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0