| T1057 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.449620455 |
|
|
Oct 03 06:43:20 AM UTC 24 |
Oct 03 06:43:26 AM UTC 24 |
650690319 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.540658386 |
|
|
Oct 03 06:43:10 AM UTC 24 |
Oct 03 06:43:26 AM UTC 24 |
3369808703 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3183101313 |
|
|
Oct 03 06:43:20 AM UTC 24 |
Oct 03 06:43:26 AM UTC 24 |
176803908 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.2492584370 |
|
|
Oct 03 06:43:11 AM UTC 24 |
Oct 03 06:43:26 AM UTC 24 |
501172838 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.500840879 |
|
|
Oct 03 06:43:20 AM UTC 24 |
Oct 03 06:43:27 AM UTC 24 |
402501499 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3411397698 |
|
|
Oct 03 06:43:20 AM UTC 24 |
Oct 03 06:43:27 AM UTC 24 |
208310586 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.1874085014 |
|
|
Oct 03 06:43:15 AM UTC 24 |
Oct 03 06:43:27 AM UTC 24 |
416019716 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.4238413056 |
|
|
Oct 03 06:43:20 AM UTC 24 |
Oct 03 06:43:27 AM UTC 24 |
207301485 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2912034236 |
|
|
Oct 03 06:43:18 AM UTC 24 |
Oct 03 06:43:27 AM UTC 24 |
1898517752 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.1328217270 |
|
|
Oct 03 06:43:18 AM UTC 24 |
Oct 03 06:43:27 AM UTC 24 |
743065328 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.3419602807 |
|
|
Oct 03 06:43:23 AM UTC 24 |
Oct 03 06:43:28 AM UTC 24 |
121879108 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.393255874 |
|
|
Oct 03 06:43:23 AM UTC 24 |
Oct 03 06:43:28 AM UTC 24 |
452188531 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.152506965 |
|
|
Oct 03 06:43:23 AM UTC 24 |
Oct 03 06:43:28 AM UTC 24 |
392886771 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.3984944996 |
|
|
Oct 03 06:42:44 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
16046343884 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.1507929894 |
|
|
Oct 03 06:43:20 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
1912430146 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.274296147 |
|
|
Oct 03 06:43:13 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
4901408407 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.2692868756 |
|
|
Oct 03 06:43:23 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
147941415 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.504631765 |
|
|
Oct 03 06:43:20 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
2225433308 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.3932986466 |
|
|
Oct 03 06:43:23 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
198420829 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.1845019793 |
|
|
Oct 03 06:43:23 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
417980636 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.884782948 |
|
|
Oct 03 06:43:23 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
1994500841 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.3271794158 |
|
|
Oct 03 06:43:23 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
186137933 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.2790778186 |
|
|
Oct 03 06:43:18 AM UTC 24 |
Oct 03 06:43:29 AM UTC 24 |
2617156192 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.969783744 |
|
|
Oct 03 06:40:31 AM UTC 24 |
Oct 03 06:43:31 AM UTC 24 |
19111990512 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.1941333547 |
|
|
Oct 03 06:43:17 AM UTC 24 |
Oct 03 06:43:31 AM UTC 24 |
1049378927 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.3216789880 |
|
|
Oct 03 06:43:12 AM UTC 24 |
Oct 03 06:43:32 AM UTC 24 |
1396889269 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.3471096762 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:33 AM UTC 24 |
133555287 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.1996870933 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:33 AM UTC 24 |
173180172 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.327067425 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:33 AM UTC 24 |
113191780 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.2327901637 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:33 AM UTC 24 |
127081914 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.3322226727 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:33 AM UTC 24 |
226039408 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3826713981 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
377961079 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.3243917640 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
86835372 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.4049392185 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
230040715 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.980571589 |
|
|
Oct 03 06:42:55 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
4570860002 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.3857138314 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
100609075 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.424660733 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
402187951 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.1233836259 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
1315218113 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2126154960 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
165253667 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.3220961601 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
212189711 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.2390091526 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
2691591145 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.3759789788 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:34 AM UTC 24 |
137315705 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.2945154494 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:35 AM UTC 24 |
555165805 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.486560115 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:35 AM UTC 24 |
264217056 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2051654017 |
|
|
Oct 03 06:43:29 AM UTC 24 |
Oct 03 06:43:35 AM UTC 24 |
2332617972 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.3363393330 |
|
|
Oct 03 06:43:28 AM UTC 24 |
Oct 03 06:43:35 AM UTC 24 |
2219107870 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.2749017402 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:35 AM UTC 24 |
166855786 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3768880419 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
125858753 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.1833499010 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
148772322 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3998553338 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
101958504 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.2906217627 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
356532824 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.2616614238 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
281369856 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3718069450 |
|
|
Oct 03 06:39:47 AM UTC 24 |
Oct 03 06:43:52 AM UTC 24 |
20932588972 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.1262264851 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
470937363 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.1409551583 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:45 AM UTC 24 |
1952103840 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.2984451078 |
|
|
Oct 03 06:39:27 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
34173783856 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.3368519279 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
124293263 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.925093372 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
198237800 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1367094630 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:36 AM UTC 24 |
151282126 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.828539130 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:37 AM UTC 24 |
335093279 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.817314449 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:37 AM UTC 24 |
321479677 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.2353426672 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:37 AM UTC 24 |
357028565 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.3918065791 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:37 AM UTC 24 |
511336018 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.1843369476 |
|
|
Oct 03 06:43:16 AM UTC 24 |
Oct 03 06:43:38 AM UTC 24 |
765988614 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.3649901789 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:52 AM UTC 24 |
105525180 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.352456779 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
168898118 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.4116525991 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
103732615 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.4174256912 |
|
|
Oct 03 06:41:47 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
8124584136 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.2778097365 |
|
|
Oct 03 06:43:34 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
108274168 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.1788105661 |
|
|
Oct 03 06:43:31 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
1905851844 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.760668965 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
492546182 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.250638520 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:52 AM UTC 24 |
362075865 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3284802234 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
248636836 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.4005441778 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
358701399 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.972618086 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:39 AM UTC 24 |
114884865 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.3649698973 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:40 AM UTC 24 |
143214799 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.499620455 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:40 AM UTC 24 |
130504870 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.1236933745 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:40 AM UTC 24 |
124385553 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.394813461 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
2419570261 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.3293903610 |
|
|
Oct 03 06:43:34 AM UTC 24 |
Oct 03 06:43:40 AM UTC 24 |
259263230 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.317189554 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:40 AM UTC 24 |
384779165 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.1856953260 |
|
|
Oct 03 06:43:34 AM UTC 24 |
Oct 03 06:43:40 AM UTC 24 |
586834508 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.2364201227 |
|
|
Oct 03 06:43:35 AM UTC 24 |
Oct 03 06:43:40 AM UTC 24 |
1791720031 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.3797007121 |
|
|
Oct 03 06:43:34 AM UTC 24 |
Oct 03 06:43:40 AM UTC 24 |
203432213 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.3514550557 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:42 AM UTC 24 |
275422432 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2357907283 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
122147264 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.4050232019 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
111736937 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2525886520 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
138750090 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.2107899267 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
258503185 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3244971493 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
428921017 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.4117427436 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
393505061 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.4058209302 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
304286013 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1179939441 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
274086826 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.3306194338 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
444844662 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.562415322 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
617234072 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.4210376299 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
397584641 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.1005869174 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
527433945 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.1524300212 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:43 AM UTC 24 |
119634012 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.3385639600 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:44 AM UTC 24 |
161795180 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.3957070444 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:44 AM UTC 24 |
387127619 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1714771756 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:44 AM UTC 24 |
311271535 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.644791512 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:44 AM UTC 24 |
276088014 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.1588503692 |
|
|
Oct 03 06:43:38 AM UTC 24 |
Oct 03 06:43:44 AM UTC 24 |
174559470 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.2738889042 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:44 AM UTC 24 |
1827978667 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.3108006795 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:45 AM UTC 24 |
556745668 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2630458906 |
|
|
Oct 03 06:43:39 AM UTC 24 |
Oct 03 06:43:45 AM UTC 24 |
2602245579 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1952815508 |
|
|
Oct 03 06:41:16 AM UTC 24 |
Oct 03 06:43:47 AM UTC 24 |
12252135018 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.2768228972 |
|
|
Oct 03 06:41:53 AM UTC 24 |
Oct 03 06:45:22 AM UTC 24 |
14503564487 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.2947262543 |
|
|
Oct 03 06:37:51 AM UTC 24 |
Oct 03 07:00:50 AM UTC 24 |
171395908585 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.700479555 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:50 AM UTC 24 |
527666846 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1490165002 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:50 AM UTC 24 |
47218298 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1315663681 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:50 AM UTC 24 |
142051776 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.3496902173 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:50 AM UTC 24 |
39772278 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2116631101 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:50 AM UTC 24 |
138059194 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2991946008 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:50 AM UTC 24 |
105092341 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2783527891 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:59 AM UTC 24 |
869978193 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.12425272 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:50 AM UTC 24 |
86385976 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1939642743 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:59 AM UTC 24 |
47893377 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3971603764 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:50 AM UTC 24 |
131587094 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3158119204 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
39501756 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.4068626699 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
75797609 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3848155094 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
81163409 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.636582484 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
390529633 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1972101107 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
51087387 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.4271699394 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
110482992 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3326040041 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
237841779 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.111507310 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
72734368 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1334903589 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
79800016 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2440784398 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
71592888 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1809088399 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
53119813 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4133891306 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
166023572 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.647601963 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:51 AM UTC 24 |
218077843 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.4076880877 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:43:52 AM UTC 24 |
1059290000 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1935433931 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:52 AM UTC 24 |
77049209 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3048172088 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:52 AM UTC 24 |
874243757 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3496783678 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:52 AM UTC 24 |
59202779 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3697314021 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:43:53 AM UTC 24 |
203471355 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2396114086 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:53 AM UTC 24 |
113995127 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.357493443 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:43:53 AM UTC 24 |
273479582 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.709911616 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:53 AM UTC 24 |
496510613 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.789568861 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
132917000 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.2065165453 |
|
|
Oct 03 06:43:51 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
40857343 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.235806321 |
|
|
Oct 03 06:43:51 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
67366963 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2479795112 |
|
|
Oct 03 06:43:51 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
547492301 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2320888187 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
1461445978 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3084859618 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
152637193 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1623744907 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
503677114 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.3634113477 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
40085360 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.24917625 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:54 AM UTC 24 |
49365260 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2741849152 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
189020861 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3676889988 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
660755515 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4154039998 |
|
|
Oct 03 06:43:51 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
64269356 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2154944558 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
410957471 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2845230500 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
905555653 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1747606228 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
274967289 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2549659389 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
319454584 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2512448910 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
79104738 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2899459326 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
140787693 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3028365159 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:55 AM UTC 24 |
1070469094 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3884206125 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:56 AM UTC 24 |
188792192 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.173244757 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:56 AM UTC 24 |
2580483336 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.934465277 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:43:57 AM UTC 24 |
675580705 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3332959793 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:57 AM UTC 24 |
149642556 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.2947304814 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:57 AM UTC 24 |
100522424 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.3017033650 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
74603026 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1722580790 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
83183640 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1254358769 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
70269110 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.3124687590 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
39352769 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.672755633 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
141527007 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1549485701 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
124531287 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3915751343 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
120684281 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1898124054 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
1785884237 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.571887446 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
47719696 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.3934907463 |
|
|
Oct 03 06:43:56 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
40512357 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.551107664 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
265491214 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3280946968 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:58 AM UTC 24 |
255168071 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1073127956 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:59 AM UTC 24 |
87840074 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.425026689 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:59 AM UTC 24 |
219194016 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1264848411 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:59 AM UTC 24 |
56860869 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3683534413 |
|
|
Oct 03 06:43:48 AM UTC 24 |
Oct 03 06:43:59 AM UTC 24 |
518529412 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1090622988 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:43:59 AM UTC 24 |
1630284945 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3302669604 |
|
|
Oct 03 06:43:49 AM UTC 24 |
Oct 03 06:44:00 AM UTC 24 |
10441951575 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3888100135 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:44:00 AM UTC 24 |
148274793 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.387994380 |
|
|
Oct 03 06:43:52 AM UTC 24 |
Oct 03 06:44:00 AM UTC 24 |
433396220 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3393570510 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:44:01 AM UTC 24 |
522601309 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2659113762 |
|
|
Oct 03 06:43:56 AM UTC 24 |
Oct 03 06:44:01 AM UTC 24 |
139602927 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.266169359 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:44:01 AM UTC 24 |
1555607776 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1867649809 |
|
|
Oct 03 06:43:59 AM UTC 24 |
Oct 03 06:44:02 AM UTC 24 |
155206200 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.33376793 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:02 AM UTC 24 |
40937825 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2386754644 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:02 AM UTC 24 |
84019259 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2557359742 |
|
|
Oct 03 06:43:59 AM UTC 24 |
Oct 03 06:44:02 AM UTC 24 |
47747436 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4208298773 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:03 AM UTC 24 |
44615919 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.831231670 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:03 AM UTC 24 |
37373858 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.925503432 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:03 AM UTC 24 |
137447590 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.3248650638 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:03 AM UTC 24 |
37379007 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1095885341 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:03 AM UTC 24 |
75862995 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3924382127 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:03 AM UTC 24 |
158834198 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.648767760 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:03 AM UTC 24 |
564712952 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.487495246 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:44:03 AM UTC 24 |
373327176 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.266291919 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
39189233 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3395359890 |
|
|
Oct 03 06:44:01 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
39014225 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.556351260 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
101844561 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.911350869 |
|
|
Oct 03 06:44:07 AM UTC 24 |
Oct 03 06:44:10 AM UTC 24 |
580672515 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1365555064 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
157953077 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1228690331 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
123029074 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2822786139 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
568620570 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3702644241 |
|
|
Oct 03 06:43:59 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
76419345 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.291478958 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
253078605 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3029835005 |
|
|
Oct 03 06:43:59 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
199587371 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.811319390 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
73759086 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3879579861 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:04 AM UTC 24 |
95200245 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.474294353 |
|
|
Oct 03 06:44:02 AM UTC 24 |
Oct 03 06:44:05 AM UTC 24 |
68916036 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.4038836176 |
|
|
Oct 03 06:44:02 AM UTC 24 |
Oct 03 06:44:05 AM UTC 24 |
116718348 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2216649683 |
|
|
Oct 03 06:44:02 AM UTC 24 |
Oct 03 06:44:05 AM UTC 24 |
40392355 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2182562041 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:05 AM UTC 24 |
270725034 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.877211566 |
|
|
Oct 03 06:44:08 AM UTC 24 |
Oct 03 06:44:11 AM UTC 24 |
43470259 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2758198128 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:05 AM UTC 24 |
359516995 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2499889058 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:05 AM UTC 24 |
108653483 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3212248737 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:44:05 AM UTC 24 |
2493130834 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3388011839 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
400938812 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.337702730 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
437618770 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.170697077 |
|
|
Oct 03 06:44:02 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
708250656 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2762447521 |
|
|
Oct 03 06:43:55 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
1386405474 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.626681500 |
|
|
Oct 03 06:44:03 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
580150361 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3849968984 |
|
|
Oct 03 06:44:02 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
96852079 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.3719675218 |
|
|
Oct 03 06:44:08 AM UTC 24 |
Oct 03 06:44:11 AM UTC 24 |
522822588 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2975076072 |
|
|
Oct 03 06:43:47 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
2500519088 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.46073996 |
|
|
Oct 03 06:44:03 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
137976672 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3681178952 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
111121040 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3371183918 |
|
|
Oct 03 06:44:02 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
368224850 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.1462020787 |
|
|
Oct 03 06:44:08 AM UTC 24 |
Oct 03 06:44:11 AM UTC 24 |
36871313 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.780147278 |
|
|
Oct 03 06:44:01 AM UTC 24 |
Oct 03 06:44:06 AM UTC 24 |
1285056504 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.192754563 |
|
|
Oct 03 06:44:03 AM UTC 24 |
Oct 03 06:44:07 AM UTC 24 |
236399820 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2224985591 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
100116021 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3298456755 |
|
|
Oct 03 06:44:03 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
250839834 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.2292628727 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
145618153 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.3441132336 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
40011518 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2618841368 |
|
|
Oct 03 06:44:00 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
1923539670 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3230132535 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
149398853 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3621108651 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
79193579 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1340020934 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
49928592 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1441367910 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
36236286 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3610529064 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
77071640 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.449023553 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
551679818 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.315561763 |
|
|
Oct 03 06:44:03 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
357106732 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1100740930 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:08 AM UTC 24 |
76993741 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2365686110 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:09 AM UTC 24 |
573440189 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.26012392 |
|
|
Oct 03 06:44:08 AM UTC 24 |
Oct 03 06:44:11 AM UTC 24 |
534759627 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2876030301 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:09 AM UTC 24 |
593621483 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1832867406 |
|
|
Oct 03 06:44:05 AM UTC 24 |
Oct 03 06:44:09 AM UTC 24 |
56358337 ps |