| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.91 | 93.58 | 96.65 | 95.54 | 91.81 | 97.35 | 96.23 | 93.21 |
| T1261 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.1968794412 | Oct 03 06:44:06 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 39413371 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1708017585 | Oct 03 06:44:06 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 40906406 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.519909209 | Oct 03 06:43:48 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 1508446616 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2824869473 | Oct 03 06:44:06 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 52178088 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.3880886372 | Oct 03 06:44:06 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 75285546 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.2237576056 | Oct 03 06:44:06 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 137152074 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3463867837 | Oct 03 06:44:07 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 42143173 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1389355288 | Oct 03 06:44:02 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 433783335 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1466582154 | Oct 03 06:44:06 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 566446658 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.4015386369 | Oct 03 06:44:06 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 41916902 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1950867366 | Oct 03 06:44:06 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 535756761 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1735094142 | Oct 03 06:44:07 AM UTC 24 | Oct 03 06:44:09 AM UTC 24 | 66385610 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.478246647 | Oct 03 06:44:07 AM UTC 24 | Oct 03 06:44:10 AM UTC 24 | 39736314 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3961964028 | Oct 03 06:44:07 AM UTC 24 | Oct 03 06:44:10 AM UTC 24 | 48262168 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.3593666074 | Oct 03 06:44:07 AM UTC 24 | Oct 03 06:44:10 AM UTC 24 | 136799244 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.3691575155 | Oct 03 06:44:07 AM UTC 24 | Oct 03 06:44:10 AM UTC 24 | 44111909 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.2434985816 | Oct 03 06:44:08 AM UTC 24 | Oct 03 06:44:11 AM UTC 24 | 602201849 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.3287091988 | Oct 03 06:44:08 AM UTC 24 | Oct 03 06:44:11 AM UTC 24 | 59982576 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3665616174 | Oct 03 06:44:00 AM UTC 24 | Oct 03 06:44:11 AM UTC 24 | 1258767926 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.707793046 | Oct 03 06:44:00 AM UTC 24 | Oct 03 06:44:12 AM UTC 24 | 2577465708 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3905076885 | Oct 03 06:44:00 AM UTC 24 | Oct 03 06:44:13 AM UTC 24 | 3046124747 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1484219309 | Oct 03 06:44:05 AM UTC 24 | Oct 03 06:44:13 AM UTC 24 | 731481394 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1175463762 | Oct 03 06:44:00 AM UTC 24 | Oct 03 06:44:13 AM UTC 24 | 2570534122 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3058361844 | Oct 03 06:43:52 AM UTC 24 | Oct 03 06:44:14 AM UTC 24 | 4563850055 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.851904511 | Oct 03 06:43:55 AM UTC 24 | Oct 03 06:44:15 AM UTC 24 | 4767113768 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3964914916 | Oct 03 06:44:03 AM UTC 24 | Oct 03 06:44:15 AM UTC 24 | 903462901 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.737131879 | Oct 03 06:43:55 AM UTC 24 | Oct 03 06:44:17 AM UTC 24 | 2917869547 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1349384131 | Oct 03 06:43:56 AM UTC 24 | Oct 03 06:44:17 AM UTC 24 | 10244592489 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.436032626 | Oct 03 06:44:00 AM UTC 24 | Oct 03 06:44:20 AM UTC 24 | 2565351065 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.845217140 | Oct 03 06:44:01 AM UTC 24 | Oct 03 06:44:23 AM UTC 24 | 18893387738 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1372277746 | Oct 03 06:44:05 AM UTC 24 | Oct 03 06:44:28 AM UTC 24 | 1556424435 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.657635312 | Oct 03 06:44:02 AM UTC 24 | Oct 03 06:44:30 AM UTC 24 | 18869393982 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.2978187800 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 302232964 ps |
| CPU time | 10.16 seconds |
| Started | Oct 03 06:29:01 AM UTC 24 |
| Finished | Oct 03 06:29:12 AM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978187800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2978187800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.72436872 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 911275952 ps |
| CPU time | 33.9 seconds |
| Started | Oct 03 06:28:57 AM UTC 24 |
| Finished | Oct 03 06:29:32 AM UTC 24 |
| Peak memory | 258148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72436872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.72436872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.260636896 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1128586172 ps |
| CPU time | 39.82 seconds |
| Started | Oct 03 06:30:02 AM UTC 24 |
| Finished | Oct 03 06:30:43 AM UTC 24 |
| Peak memory | 253944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260636896 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.260636896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.150118233 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3755827755 ps |
| CPU time | 160.78 seconds |
| Started | Oct 03 06:29:22 AM UTC 24 |
| Finished | Oct 03 06:32:06 AM UTC 24 |
| Peak memory | 285016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=150118233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.150118233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.1714963979 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2374087908 ps |
| CPU time | 36.05 seconds |
| Started | Oct 03 06:29:56 AM UTC 24 |
| Finished | Oct 03 06:30:33 AM UTC 24 |
| Peak memory | 254232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714963979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1714963979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.567232513 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 8421054008 ps |
| CPU time | 81.29 seconds |
| Started | Oct 03 06:29:43 AM UTC 24 |
| Finished | Oct 03 06:31:07 AM UTC 24 |
| Peak memory | 255824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567232513 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.567232513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.404699216 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5567774622 ps |
| CPU time | 111.23 seconds |
| Started | Oct 03 06:31:19 AM UTC 24 |
| Finished | Oct 03 06:33:13 AM UTC 24 |
| Peak memory | 258244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404699216 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.404699216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.4109538576 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 470637176 ps |
| CPU time | 12.46 seconds |
| Started | Oct 03 06:28:56 AM UTC 24 |
| Finished | Oct 03 06:29:09 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109538576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.4109538576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.1825097664 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 21983891891 ps |
| CPU time | 184.08 seconds |
| Started | Oct 03 06:30:25 AM UTC 24 |
| Finished | Oct 03 06:33:32 AM UTC 24 |
| Peak memory | 286312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825097664 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1825097664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.2217781994 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3069174880 ps |
| CPU time | 62.37 seconds |
| Started | Oct 03 06:28:56 AM UTC 24 |
| Finished | Oct 03 06:30:00 AM UTC 24 |
| Peak memory | 254024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217781994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2217781994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.301516986 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 103904711 ps |
| CPU time | 3.58 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:00 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301516986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.301516986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.2628203163 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 113104055239 ps |
| CPU time | 175.14 seconds |
| Started | Oct 03 06:30:23 AM UTC 24 |
| Finished | Oct 03 06:33:22 AM UTC 24 |
| Peak memory | 290892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628203163 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.2628203163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.2482162481 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1474379138 ps |
| CPU time | 23.07 seconds |
| Started | Oct 03 06:29:16 AM UTC 24 |
| Finished | Oct 03 06:29:41 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482162481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.2482162481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.1058880124 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 216160341 ps |
| CPU time | 5.47 seconds |
| Started | Oct 03 06:31:11 AM UTC 24 |
| Finished | Oct 03 06:31:18 AM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058880124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1058880124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2783527891 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 869978193 ps |
| CPU time | 9.96 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:59 AM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783527891 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.2783527891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.2812706769 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 108314028 ps |
| CPU time | 4.85 seconds |
| Started | Oct 03 06:31:40 AM UTC 24 |
| Finished | Oct 03 06:31:46 AM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812706769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2812706769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1698427990 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 65400931389 ps |
| CPU time | 198.92 seconds |
| Started | Oct 03 06:31:06 AM UTC 24 |
| Finished | Oct 03 06:34:29 AM UTC 24 |
| Peak memory | 268376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698427990 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.1698427990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.816881140 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 15431042093 ps |
| CPU time | 252.33 seconds |
| Started | Oct 03 06:31:17 AM UTC 24 |
| Finished | Oct 03 06:35:34 AM UTC 24 |
| Peak memory | 268504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=816881140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.816881140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.3929431595 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 13174570724 ps |
| CPU time | 96.47 seconds |
| Started | Oct 03 06:30:43 AM UTC 24 |
| Finished | Oct 03 06:32:21 AM UTC 24 |
| Peak memory | 254096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929431595 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.3929431595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.3922025996 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 126661773 ps |
| CPU time | 4.44 seconds |
| Started | Oct 03 06:34:48 AM UTC 24 |
| Finished | Oct 03 06:34:53 AM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922025996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3922025996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.2324406714 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3568735599 ps |
| CPU time | 31.29 seconds |
| Started | Oct 03 06:31:34 AM UTC 24 |
| Finished | Oct 03 06:32:07 AM UTC 24 |
| Peak memory | 258340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324406714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.2324406714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.2123691444 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4290899280 ps |
| CPU time | 32.72 seconds |
| Started | Oct 03 06:29:14 AM UTC 24 |
| Finished | Oct 03 06:29:48 AM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123691444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2123691444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.2674242725 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 12247337705 ps |
| CPU time | 94.81 seconds |
| Started | Oct 03 06:34:17 AM UTC 24 |
| Finished | Oct 03 06:35:54 AM UTC 24 |
| Peak memory | 258044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674242725 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.2674242725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.636582484 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 390529633 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636582484 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.636582484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.3932986466 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 198420829 ps |
| CPU time | 4.62 seconds |
| Started | Oct 03 06:43:23 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932986466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3932986466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.2465974310 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 567089384 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 06:29:07 AM UTC 24 |
| Finished | Oct 03 06:29:10 AM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465974310 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.2465974310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.2456505084 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1542345080 ps |
| CPU time | 28.09 seconds |
| Started | Oct 03 06:29:34 AM UTC 24 |
| Finished | Oct 03 06:30:04 AM UTC 24 |
| Peak memory | 252100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456505084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.2456505084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.2057542707 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 69180065367 ps |
| CPU time | 242.24 seconds |
| Started | Oct 03 06:32:20 AM UTC 24 |
| Finished | Oct 03 06:36:27 AM UTC 24 |
| Peak memory | 268412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057542707 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.2057542707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.3278884830 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 12098274880 ps |
| CPU time | 82.33 seconds |
| Started | Oct 03 06:30:58 AM UTC 24 |
| Finished | Oct 03 06:32:23 AM UTC 24 |
| Peak memory | 258336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278884830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3278884830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.2702003268 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 355542763 ps |
| CPU time | 5.78 seconds |
| Started | Oct 03 06:43:10 AM UTC 24 |
| Finished | Oct 03 06:43:17 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702003268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2702003268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.2023206103 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 271380780 ps |
| CPU time | 5.4 seconds |
| Started | Oct 03 06:30:07 AM UTC 24 |
| Finished | Oct 03 06:30:14 AM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023206103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2023206103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.548593865 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 633751643 ps |
| CPU time | 6.71 seconds |
| Started | Oct 03 06:42:08 AM UTC 24 |
| Finished | Oct 03 06:42:16 AM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548593865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.548593865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.316450604 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 19015033431 ps |
| CPU time | 63.54 seconds |
| Started | Oct 03 06:34:27 AM UTC 24 |
| Finished | Oct 03 06:35:32 AM UTC 24 |
| Peak memory | 268296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316450604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.316450604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.1159258341 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 187675044 ps |
| CPU time | 4.86 seconds |
| Started | Oct 03 06:28:56 AM UTC 24 |
| Finished | Oct 03 06:29:01 AM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159258341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1159258341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2292987024 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3708789080 ps |
| CPU time | 105.86 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:39:57 AM UTC 24 |
| Peak memory | 268500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2292987024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.otp_ctrl_stress_all_with_rand_reset.2292987024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2987783625 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 15113936248 ps |
| CPU time | 148.07 seconds |
| Started | Oct 03 06:40:24 AM UTC 24 |
| Finished | Oct 03 06:42:55 AM UTC 24 |
| Peak memory | 258140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2987783625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 61.otp_ctrl_stress_all_with_rand_reset.2987783625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.1992142736 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1708473127 ps |
| CPU time | 8.71 seconds |
| Started | Oct 03 06:30:28 AM UTC 24 |
| Finished | Oct 03 06:30:38 AM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992142736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1992142736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.2916896156 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 17167094321 ps |
| CPU time | 220.34 seconds |
| Started | Oct 03 06:36:06 AM UTC 24 |
| Finished | Oct 03 06:39:51 AM UTC 24 |
| Peak memory | 272384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916896156 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.2916896156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.3622820753 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 150797385 ps |
| CPU time | 6.54 seconds |
| Started | Oct 03 06:35:20 AM UTC 24 |
| Finished | Oct 03 06:35:28 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622820753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3622820753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.2367436600 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 23255484078 ps |
| CPU time | 74.5 seconds |
| Started | Oct 03 06:28:59 AM UTC 24 |
| Finished | Oct 03 06:30:15 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367436600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2367436600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.4032303001 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 276571662 ps |
| CPU time | 6.31 seconds |
| Started | Oct 03 06:39:04 AM UTC 24 |
| Finished | Oct 03 06:39:11 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032303001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.4032303001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.519909209 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1508446616 ps |
| CPU time | 19.42 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 255652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519909209 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.519909209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1344226604 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 775227992 ps |
| CPU time | 16.65 seconds |
| Started | Oct 03 06:37:14 AM UTC 24 |
| Finished | Oct 03 06:37:31 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344226604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1344226604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.321689155 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 26200401164 ps |
| CPU time | 186.46 seconds |
| Started | Oct 03 06:33:39 AM UTC 24 |
| Finished | Oct 03 06:36:49 AM UTC 24 |
| Peak memory | 305236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321689155 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.321689155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.2851354685 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 480509518 ps |
| CPU time | 10.05 seconds |
| Started | Oct 03 06:36:12 AM UTC 24 |
| Finished | Oct 03 06:36:24 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851354685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2851354685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.4004873351 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 8760323026 ps |
| CPU time | 105.63 seconds |
| Started | Oct 03 06:33:49 AM UTC 24 |
| Finished | Oct 03 06:35:37 AM UTC 24 |
| Peak memory | 258132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004873351 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.4004873351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.363409884 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1123993983 ps |
| CPU time | 17.34 seconds |
| Started | Oct 03 06:31:17 AM UTC 24 |
| Finished | Oct 03 06:31:36 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363409884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.363409884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.2313809897 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2262326751 ps |
| CPU time | 34.23 seconds |
| Started | Oct 03 06:39:08 AM UTC 24 |
| Finished | Oct 03 06:39:43 AM UTC 24 |
| Peak memory | 254024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313809897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2313809897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.2375114786 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 498486595 ps |
| CPU time | 9.22 seconds |
| Started | Oct 03 06:31:27 AM UTC 24 |
| Finished | Oct 03 06:31:38 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375114786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2375114786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.4214500018 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1300987981 ps |
| CPU time | 32.18 seconds |
| Started | Oct 03 06:30:54 AM UTC 24 |
| Finished | Oct 03 06:31:28 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214500018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.4214500018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2335970843 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 199890905 ps |
| CPU time | 3.97 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:26 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335970843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2335970843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.690278408 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 10258437138 ps |
| CPU time | 81.6 seconds |
| Started | Oct 03 06:31:37 AM UTC 24 |
| Finished | Oct 03 06:33:01 AM UTC 24 |
| Peak memory | 268372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690278408 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.690278408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.613793141 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 472045082 ps |
| CPU time | 6.97 seconds |
| Started | Oct 03 06:29:27 AM UTC 24 |
| Finished | Oct 03 06:29:35 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613793141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.613793141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.2656508141 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 10598592663 ps |
| CPU time | 69.72 seconds |
| Started | Oct 03 06:34:14 AM UTC 24 |
| Finished | Oct 03 06:35:26 AM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656508141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2656508141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.1196331148 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 39117406338 ps |
| CPU time | 145.81 seconds |
| Started | Oct 03 06:38:41 AM UTC 24 |
| Finished | Oct 03 06:41:10 AM UTC 24 |
| Peak memory | 260244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196331148 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.1196331148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.3598889121 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 212118422 ps |
| CPU time | 8.43 seconds |
| Started | Oct 03 06:40:31 AM UTC 24 |
| Finished | Oct 03 06:40:40 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598889121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3598889121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2004838395 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 36001860565 ps |
| CPU time | 78.48 seconds |
| Started | Oct 03 06:41:35 AM UTC 24 |
| Finished | Oct 03 06:42:55 AM UTC 24 |
| Peak memory | 260244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2004838395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 92.otp_ctrl_stress_all_with_rand_reset.2004838395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.2711625909 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4894101735 ps |
| CPU time | 112.17 seconds |
| Started | Oct 03 06:32:41 AM UTC 24 |
| Finished | Oct 03 06:34:36 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711625909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.2711625909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.2492048864 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 527385953 ps |
| CPU time | 8.18 seconds |
| Started | Oct 03 06:42:24 AM UTC 24 |
| Finished | Oct 03 06:42:33 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492048864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2492048864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.3950242865 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 595358022 ps |
| CPU time | 16.23 seconds |
| Started | Oct 03 06:42:26 AM UTC 24 |
| Finished | Oct 03 06:42:44 AM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950242865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3950242865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.2023633971 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 314174436 ps |
| CPU time | 2.61 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:42:58 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023633971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2023633971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.3605380054 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 348544865 ps |
| CPU time | 8.05 seconds |
| Started | Oct 03 06:43:11 AM UTC 24 |
| Finished | Oct 03 06:43:20 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605380054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3605380054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.2456962378 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1156607803 ps |
| CPU time | 20.33 seconds |
| Started | Oct 03 06:29:33 AM UTC 24 |
| Finished | Oct 03 06:29:54 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456962378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2456962378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.3797007121 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 203432213 ps |
| CPU time | 4.47 seconds |
| Started | Oct 03 06:43:34 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797007121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3797007121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.1214103208 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1925063284 ps |
| CPU time | 9.36 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:38:46 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214103208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1214103208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.4271699394 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 110482992 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 257136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271699394 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.4271699394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.657635312 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 18869393982 ps |
| CPU time | 27.16 seconds |
| Started | Oct 03 06:44:02 AM UTC 24 |
| Finished | Oct 03 06:44:30 AM UTC 24 |
| Peak memory | 255724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657635312 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.657635312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.3360174016 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 275804352 ps |
| CPU time | 10.33 seconds |
| Started | Oct 03 06:35:13 AM UTC 24 |
| Finished | Oct 03 06:35:24 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360174016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3360174016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.376046373 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1466923235 ps |
| CPU time | 23.52 seconds |
| Started | Oct 03 06:32:12 AM UTC 24 |
| Finished | Oct 03 06:32:37 AM UTC 24 |
| Peak memory | 252096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376046373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.376046373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.887387350 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3473838648 ps |
| CPU time | 106.79 seconds |
| Started | Oct 03 06:38:41 AM UTC 24 |
| Finished | Oct 03 06:40:30 AM UTC 24 |
| Peak memory | 268376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=887387350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.887387350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.2090837532 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2742711901 ps |
| CPU time | 13.58 seconds |
| Started | Oct 03 06:28:59 AM UTC 24 |
| Finished | Oct 03 06:29:14 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090837532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2090837532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.2650136683 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 674221994 ps |
| CPU time | 24.29 seconds |
| Started | Oct 03 06:33:45 AM UTC 24 |
| Finished | Oct 03 06:34:11 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650136683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2650136683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.3701398279 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1085346601 ps |
| CPU time | 33.44 seconds |
| Started | Oct 03 06:34:33 AM UTC 24 |
| Finished | Oct 03 06:35:08 AM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701398279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3701398279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.449066854 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 805512321 ps |
| CPU time | 6.44 seconds |
| Started | Oct 03 06:37:38 AM UTC 24 |
| Finished | Oct 03 06:37:46 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449066854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.449066854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.1890654780 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3833474125 ps |
| CPU time | 67.98 seconds |
| Started | Oct 03 06:35:13 AM UTC 24 |
| Finished | Oct 03 06:36:23 AM UTC 24 |
| Peak memory | 262356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1890654780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.otp_ctrl_stress_all_with_rand_reset.1890654780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4133891306 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 166023572 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133891306 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.4133891306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.2210426693 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 139176880635 ps |
| CPU time | 288.52 seconds |
| Started | Oct 03 06:32:05 AM UTC 24 |
| Finished | Oct 03 06:36:57 AM UTC 24 |
| Peak memory | 307412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210426693 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.2210426693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.2572501336 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 102610187365 ps |
| CPU time | 192.43 seconds |
| Started | Oct 03 06:32:44 AM UTC 24 |
| Finished | Oct 03 06:36:00 AM UTC 24 |
| Peak memory | 272448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572501336 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.2572501336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.682076282 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 447435123 ps |
| CPU time | 6.7 seconds |
| Started | Oct 03 06:41:57 AM UTC 24 |
| Finished | Oct 03 06:42:05 AM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682076282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.682076282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.1644814587 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 198965849 ps |
| CPU time | 5.59 seconds |
| Started | Oct 03 06:42:04 AM UTC 24 |
| Finished | Oct 03 06:42:11 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644814587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.1644814587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.848187702 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 478389088 ps |
| CPU time | 5.96 seconds |
| Started | Oct 03 06:42:12 AM UTC 24 |
| Finished | Oct 03 06:42:19 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848187702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.848187702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.1802592418 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 106477707 ps |
| CPU time | 5.11 seconds |
| Started | Oct 03 06:42:30 AM UTC 24 |
| Finished | Oct 03 06:42:37 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802592418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1802592418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.1541696719 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 313443623 ps |
| CPU time | 12.66 seconds |
| Started | Oct 03 06:29:25 AM UTC 24 |
| Finished | Oct 03 06:29:38 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541696719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1541696719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.3621250044 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 13314546147 ps |
| CPU time | 184.58 seconds |
| Started | Oct 03 06:39:40 AM UTC 24 |
| Finished | Oct 03 06:42:48 AM UTC 24 |
| Peak memory | 270396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621250044 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.3621250044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.2603162685 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2467577964 ps |
| CPU time | 9.87 seconds |
| Started | Oct 03 06:34:34 AM UTC 24 |
| Finished | Oct 03 06:34:45 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603162685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.2603162685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.849948499 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 517207475 ps |
| CPU time | 13.58 seconds |
| Started | Oct 03 06:35:06 AM UTC 24 |
| Finished | Oct 03 06:35:21 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849948499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.849948499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.1413273328 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2557047330 ps |
| CPU time | 19.67 seconds |
| Started | Oct 03 06:37:55 AM UTC 24 |
| Finished | Oct 03 06:38:16 AM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413273328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1413273328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.3578383630 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 363493604 ps |
| CPU time | 13.24 seconds |
| Started | Oct 03 06:31:47 AM UTC 24 |
| Finished | Oct 03 06:32:01 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578383630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3578383630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.645340244 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 858444989 ps |
| CPU time | 19.83 seconds |
| Started | Oct 03 06:29:36 AM UTC 24 |
| Finished | Oct 03 06:29:57 AM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645340244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.645340244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.2661089642 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 192262978 ps |
| CPU time | 2.68 seconds |
| Started | Oct 03 06:28:54 AM UTC 24 |
| Finished | Oct 03 06:28:58 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661089642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2661089642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.1880358859 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 579341157 ps |
| CPU time | 13.84 seconds |
| Started | Oct 03 06:30:50 AM UTC 24 |
| Finished | Oct 03 06:31:05 AM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880358859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.1880358859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.2728661408 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1403923134 ps |
| CPU time | 34.75 seconds |
| Started | Oct 03 06:30:41 AM UTC 24 |
| Finished | Oct 03 06:31:17 AM UTC 24 |
| Peak memory | 252124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728661408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.2728661408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.4229644306 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1264598188 ps |
| CPU time | 20.49 seconds |
| Started | Oct 03 06:31:34 AM UTC 24 |
| Finished | Oct 03 06:31:56 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229644306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.4229644306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.400624390 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 937900728 ps |
| CPU time | 30.68 seconds |
| Started | Oct 03 06:30:09 AM UTC 24 |
| Finished | Oct 03 06:30:41 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400624390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.400624390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.837096764 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2433404866 ps |
| CPU time | 6.99 seconds |
| Started | Oct 03 06:32:26 AM UTC 24 |
| Finished | Oct 03 06:32:34 AM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837096764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.837096764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1623744907 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 503677114 ps |
| CPU time | 5.6 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623744907 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.1623744907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.934465277 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 675580705 ps |
| CPU time | 8.45 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:57 AM UTC 24 |
| Peak memory | 241260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934465277 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.934465277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.12425272 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 86385976 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:50 AM UTC 24 |
| Peak memory | 253416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12425272 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.12425272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1315663681 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 142051776 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:50 AM UTC 24 |
| Peak memory | 239900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315663681 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1315663681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1490165002 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 47218298 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:50 AM UTC 24 |
| Peak memory | 239624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490165002 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.1490165002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.700479555 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 527666846 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:50 AM UTC 24 |
| Peak memory | 240476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700479555 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.700479555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.647601963 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 218077843 ps |
| CPU time | 2.86 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647601963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.647601963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3676889988 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 660755515 ps |
| CPU time | 6.39 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676889988 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3676889988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2975076072 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2500519088 ps |
| CPU time | 17.48 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 255612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975076072 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.2975076072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3048172088 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 874243757 ps |
| CPU time | 3.12 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:52 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048172088 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.3048172088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2154944558 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 410957471 ps |
| CPU time | 5.72 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154944558 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.2154944558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3848155094 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 81163409 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848155094 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.3848155094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3326040041 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 237841779 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 255192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3326040041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.3326040041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.3496902173 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 39772278 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:50 AM UTC 24 |
| Peak memory | 241080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496902173 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3496902173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2991946008 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 105092341 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:50 AM UTC 24 |
| Peak memory | 239124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991946008 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.2991946008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2116631101 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 138059194 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:50 AM UTC 24 |
| Peak memory | 239188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116631101 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.2116631101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2440784398 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 71592888 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440784398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.2440784398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2549659389 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 319454584 ps |
| CPU time | 6.5 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 257816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549659389 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2549659389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3702644241 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 76419345 ps |
| CPU time | 3.35 seconds |
| Started | Oct 03 06:43:59 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3702644241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c sr_mem_rw_with_rand_reset.3702644241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1867649809 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 155206200 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 06:43:59 AM UTC 24 |
| Finished | Oct 03 06:44:02 AM UTC 24 |
| Peak memory | 253412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867649809 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1867649809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.3934907463 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 40512357 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 06:43:56 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934907463 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3934907463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2557359742 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 47747436 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 06:43:59 AM UTC 24 |
| Finished | Oct 03 06:44:02 AM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557359742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.2557359742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2659113762 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 139602927 ps |
| CPU time | 4.46 seconds |
| Started | Oct 03 06:43:56 AM UTC 24 |
| Finished | Oct 03 06:44:01 AM UTC 24 |
| Peak memory | 257860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659113762 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.2659113762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1349384131 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 10244592489 ps |
| CPU time | 20.1 seconds |
| Started | Oct 03 06:43:56 AM UTC 24 |
| Finished | Oct 03 06:44:17 AM UTC 24 |
| Peak memory | 255728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349384131 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.1349384131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.337702730 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 437618770 ps |
| CPU time | 4.92 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=337702730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_cs r_mem_rw_with_rand_reset.337702730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2386754644 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 84019259 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:02 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386754644 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.2386754644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.33376793 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 40937825 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:02 AM UTC 24 |
| Peak memory | 240052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33376793 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.33376793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1228690331 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 123029074 ps |
| CPU time | 3.11 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 253600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228690331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.1228690331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3029835005 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 199587371 ps |
| CPU time | 3.54 seconds |
| Started | Oct 03 06:43:59 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 257824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029835005 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3029835005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.707793046 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2577465708 ps |
| CPU time | 11.83 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:12 AM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707793046 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.707793046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1095885341 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 75862995 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:03 AM UTC 24 |
| Peak memory | 255172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1095885341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.1095885341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4208298773 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 44615919 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:03 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208298773 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.4208298773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3924382127 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 158834198 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:03 AM UTC 24 |
| Peak memory | 241148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924382127 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3924382127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1365555064 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 157953077 ps |
| CPU time | 2.74 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365555064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.1365555064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.556351260 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 101844561 ps |
| CPU time | 2.83 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 257764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556351260 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.556351260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3665616174 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1258767926 ps |
| CPU time | 10.59 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:11 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665616174 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.3665616174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2758198128 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 359516995 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:05 AM UTC 24 |
| Peak memory | 257764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2758198128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c sr_mem_rw_with_rand_reset.2758198128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.648767760 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 564712952 ps |
| CPU time | 2 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:03 AM UTC 24 |
| Peak memory | 253408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648767760 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.648767760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.3248650638 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 37379007 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:03 AM UTC 24 |
| Peak memory | 239848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248650638 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3248650638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2182562041 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 270725034 ps |
| CPU time | 3.81 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:05 AM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182562041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.2182562041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3879579861 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 95200245 ps |
| CPU time | 3.49 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879579861 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3879579861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.436032626 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2565351065 ps |
| CPU time | 19.31 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:20 AM UTC 24 |
| Peak memory | 257704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436032626 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.436032626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2499889058 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 108653483 ps |
| CPU time | 3.59 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:05 AM UTC 24 |
| Peak memory | 257764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2499889058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.2499889058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.925503432 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 137447590 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:03 AM UTC 24 |
| Peak memory | 253408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925503432 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.925503432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.831231670 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 37373858 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:03 AM UTC 24 |
| Peak memory | 240056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831231670 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.831231670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2618841368 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 1923539670 ps |
| CPU time | 6.06 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618841368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.2618841368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3681178952 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 111121040 ps |
| CPU time | 4.88 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 257864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681178952 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3681178952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1175463762 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2570534122 ps |
| CPU time | 11.83 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:13 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175463762 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.1175463762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.291478958 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 253078605 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 255716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=291478958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_cs r_mem_rw_with_rand_reset.291478958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2822786139 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 568620570 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 253384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822786139 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2822786139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.266291919 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 39189233 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266291919 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.266291919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.811319390 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 73759086 ps |
| CPU time | 2.36 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811319390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.811319390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3388011839 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 400938812 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388011839 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.3388011839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3905076885 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 3046124747 ps |
| CPU time | 10.91 seconds |
| Started | Oct 03 06:44:00 AM UTC 24 |
| Finished | Oct 03 06:44:13 AM UTC 24 |
| Peak memory | 255596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905076885 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.3905076885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3371183918 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 368224850 ps |
| CPU time | 3.45 seconds |
| Started | Oct 03 06:44:02 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3371183918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.3371183918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.4038836176 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 116718348 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 06:44:02 AM UTC 24 |
| Finished | Oct 03 06:44:05 AM UTC 24 |
| Peak memory | 253388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038836176 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.4038836176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3395359890 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 39014225 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 06:44:01 AM UTC 24 |
| Finished | Oct 03 06:44:04 AM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395359890 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3395359890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.170697077 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 708250656 ps |
| CPU time | 2.9 seconds |
| Started | Oct 03 06:44:02 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170697077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.170697077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.780147278 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 1285056504 ps |
| CPU time | 4.45 seconds |
| Started | Oct 03 06:44:01 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780147278 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.780147278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.845217140 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 18893387738 ps |
| CPU time | 20.84 seconds |
| Started | Oct 03 06:44:01 AM UTC 24 |
| Finished | Oct 03 06:44:23 AM UTC 24 |
| Peak memory | 255788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845217140 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.845217140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.192754563 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 236399820 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 06:44:03 AM UTC 24 |
| Finished | Oct 03 06:44:07 AM UTC 24 |
| Peak memory | 257768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=192754563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_cs r_mem_rw_with_rand_reset.192754563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2216649683 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 40392355 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 06:44:02 AM UTC 24 |
| Finished | Oct 03 06:44:05 AM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216649683 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2216649683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.474294353 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 68916036 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 06:44:02 AM UTC 24 |
| Finished | Oct 03 06:44:05 AM UTC 24 |
| Peak memory | 239888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474294353 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.474294353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3849968984 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 96852079 ps |
| CPU time | 2.81 seconds |
| Started | Oct 03 06:44:02 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849968984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.3849968984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1389355288 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 433783335 ps |
| CPU time | 6.44 seconds |
| Started | Oct 03 06:44:02 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 257672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389355288 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1389355288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.46073996 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 137976672 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 06:44:03 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46073996 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.46073996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.626681500 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 580150361 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 06:44:03 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 240056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626681500 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.626681500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.315561763 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 357106732 ps |
| CPU time | 3.91 seconds |
| Started | Oct 03 06:44:03 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315561763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.315561763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3298456755 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 250839834 ps |
| CPU time | 3.53 seconds |
| Started | Oct 03 06:44:03 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 257696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298456755 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3298456755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3964914916 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 903462901 ps |
| CPU time | 10.85 seconds |
| Started | Oct 03 06:44:03 AM UTC 24 |
| Finished | Oct 03 06:44:15 AM UTC 24 |
| Peak memory | 255532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964914916 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.3964914916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1100740930 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 76993741 ps |
| CPU time | 2.22 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 255624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1100740930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c sr_mem_rw_with_rand_reset.1100740930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2224985591 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 100116021 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224985591 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2224985591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.2292628727 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 145618153 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292628727 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2292628727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1832867406 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 56358337 ps |
| CPU time | 2.59 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832867406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.1832867406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1484219309 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 731481394 ps |
| CPU time | 7.27 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:13 AM UTC 24 |
| Peak memory | 257820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484219309 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1484219309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1372277746 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 1556424435 ps |
| CPU time | 21.99 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:28 AM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372277746 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.1372277746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.173244757 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 2580483336 ps |
| CPU time | 6.99 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:56 AM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173244757 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.173244757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3683534413 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 518529412 ps |
| CPU time | 9.96 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:59 AM UTC 24 |
| Peak memory | 241312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683534413 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.3683534413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2320888187 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1461445978 ps |
| CPU time | 4.62 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320888187 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.2320888187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1935433931 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 77049209 ps |
| CPU time | 2.59 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:52 AM UTC 24 |
| Peak memory | 255848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1935433931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.1935433931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1972101107 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 51087387 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972101107 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1972101107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.4068626699 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 75797609 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 240316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068626699 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.4068626699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3158119204 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 39501756 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 239124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158119204 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.3158119204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3971603764 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 131587094 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:50 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971603764 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.3971603764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.709911616 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 496510613 ps |
| CPU time | 3.59 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:53 AM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709911616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.709911616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2396114086 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 113995127 ps |
| CPU time | 3.7 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:53 AM UTC 24 |
| Peak memory | 257716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396114086 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2396114086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1898124054 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1785884237 ps |
| CPU time | 9.09 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 255636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898124054 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.1898124054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.2876030301 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 593621483 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 240636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876030301 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.2876030301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3621108651 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 79193579 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621108651 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3621108651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.3441132336 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 40011518 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441132336 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.3441132336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3230132535 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 149398853 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230132535 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3230132535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.2365686110 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 573440189 ps |
| CPU time | 2.02 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 240376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365686110 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2365686110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.449023553 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 551679818 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449023553 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.449023553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1441367910 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 36236286 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441367910 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1441367910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1340020934 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 49928592 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340020934 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1340020934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3610529064 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 77071640 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 06:44:05 AM UTC 24 |
| Finished | Oct 03 06:44:08 AM UTC 24 |
| Peak memory | 239420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610529064 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3610529064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1708017585 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 40906406 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 06:44:06 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 240192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708017585 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1708017585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.789568861 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 132917000 ps |
| CPU time | 4.16 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789568861 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.789568861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2741849152 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 189020861 ps |
| CPU time | 4.93 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741849152 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.2741849152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.4076880877 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1059290000 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:43:52 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076880877 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.4076880877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3697314021 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 203471355 ps |
| CPU time | 2.89 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:43:53 AM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3697314021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.3697314021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.111507310 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 72734368 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 240252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111507310 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.111507310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1809088399 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 53119813 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 239392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809088399 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.1809088399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1334903589 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 79800016 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:51 AM UTC 24 |
| Peak memory | 241204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334903589 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.1334903589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.357493443 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 273479582 ps |
| CPU time | 3.14 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:43:53 AM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357493443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.357493443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3496783678 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 59202779 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 06:43:48 AM UTC 24 |
| Finished | Oct 03 06:43:52 AM UTC 24 |
| Peak memory | 257832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496783678 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3496783678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.1968794412 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 39413371 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 06:44:06 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968794412 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1968794412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1950867366 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 535756761 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 06:44:06 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 240048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950867366 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1950867366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2824869473 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 52178088 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 06:44:06 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 240312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824869473 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2824869473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1466582154 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 566446658 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 06:44:06 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466582154 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1466582154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.3880886372 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 75285546 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 06:44:06 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880886372 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3880886372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.2237576056 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 137152074 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 06:44:06 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237576056 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2237576056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.4015386369 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 41916902 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 06:44:06 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 239928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015386369 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.4015386369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.3463867837 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 42143173 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 06:44:07 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463867837 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3463867837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1735094142 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 66385610 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 06:44:07 AM UTC 24 |
| Finished | Oct 03 06:44:09 AM UTC 24 |
| Peak memory | 240000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735094142 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1735094142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.911350869 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 580672515 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 06:44:07 AM UTC 24 |
| Finished | Oct 03 06:44:10 AM UTC 24 |
| Peak memory | 239936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911350869 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.911350869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3884206125 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 188792192 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:56 AM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884206125 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.3884206125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.387994380 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 433396220 ps |
| CPU time | 7.86 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:44:00 AM UTC 24 |
| Peak memory | 241088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387994380 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.387994380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4154039998 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 64269356 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 06:43:51 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 253380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154039998 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.4154039998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3028365159 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 1070469094 ps |
| CPU time | 2.76 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 255716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3028365159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.3028365159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3084859618 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 152637193 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084859618 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3084859618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.2065165453 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 40857343 ps |
| CPU time | 1.49 seconds |
| Started | Oct 03 06:43:51 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 240252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065165453 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.2065165453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.235806321 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 67366963 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 06:43:51 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 238408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235806321 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.235806321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2479795112 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 547492301 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 06:43:51 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479795112 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.2479795112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1747606228 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 274967289 ps |
| CPU time | 2.59 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 253596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747606228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.1747606228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2845230500 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 905555653 ps |
| CPU time | 4.98 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 257664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845230500 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.2845230500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3302669604 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 10441951575 ps |
| CPU time | 9.68 seconds |
| Started | Oct 03 06:43:49 AM UTC 24 |
| Finished | Oct 03 06:44:00 AM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302669604 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.3302669604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.3593666074 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 136799244 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 06:44:07 AM UTC 24 |
| Finished | Oct 03 06:44:10 AM UTC 24 |
| Peak memory | 240252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593666074 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.3593666074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.478246647 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 39736314 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 06:44:07 AM UTC 24 |
| Finished | Oct 03 06:44:10 AM UTC 24 |
| Peak memory | 239936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478246647 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.478246647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.3691575155 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 44111909 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 06:44:07 AM UTC 24 |
| Finished | Oct 03 06:44:10 AM UTC 24 |
| Peak memory | 240248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691575155 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3691575155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.3961964028 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 48262168 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 06:44:07 AM UTC 24 |
| Finished | Oct 03 06:44:10 AM UTC 24 |
| Peak memory | 239924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961964028 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3961964028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.3719675218 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 522822588 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 06:44:08 AM UTC 24 |
| Finished | Oct 03 06:44:11 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719675218 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3719675218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.877211566 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 43470259 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 06:44:08 AM UTC 24 |
| Finished | Oct 03 06:44:11 AM UTC 24 |
| Peak memory | 240112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877211566 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.877211566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.1462020787 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 36871313 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 06:44:08 AM UTC 24 |
| Finished | Oct 03 06:44:11 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462020787 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1462020787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.3287091988 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 59982576 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 06:44:08 AM UTC 24 |
| Finished | Oct 03 06:44:11 AM UTC 24 |
| Peak memory | 241020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287091988 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.3287091988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.2434985816 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 602201849 ps |
| CPU time | 1.69 seconds |
| Started | Oct 03 06:44:08 AM UTC 24 |
| Finished | Oct 03 06:44:11 AM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434985816 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2434985816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.26012392 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 534759627 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 06:44:08 AM UTC 24 |
| Finished | Oct 03 06:44:11 AM UTC 24 |
| Peak memory | 241080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26012392 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.26012392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2512448910 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 79104738 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 257748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2512448910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.2512448910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.24917625 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 49365260 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24917625 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.24917625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.3634113477 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 40085360 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:54 AM UTC 24 |
| Peak memory | 240252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634113477 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3634113477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2899459326 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 140787693 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899459326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.2899459326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.551107664 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 265491214 ps |
| CPU time | 5.53 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551107664 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.551107664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3058361844 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 4563850055 ps |
| CPU time | 21.27 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:44:14 AM UTC 24 |
| Peak memory | 255732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058361844 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.3058361844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1090622988 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 1630284945 ps |
| CPU time | 3.49 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:59 AM UTC 24 |
| Peak memory | 257768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1090622988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.1090622988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3332959793 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 149642556 ps |
| CPU time | 1.59 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:57 AM UTC 24 |
| Peak memory | 251304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332959793 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.3332959793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.2947304814 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 100522424 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:57 AM UTC 24 |
| Peak memory | 240252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947304814 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2947304814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1254358769 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 70269110 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254358769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.1254358769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1722580790 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 83183640 ps |
| CPU time | 4.74 seconds |
| Started | Oct 03 06:43:52 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 257620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722580790 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1722580790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.851904511 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 4767113768 ps |
| CPU time | 19.1 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:44:15 AM UTC 24 |
| Peak memory | 257772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851904511 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.851904511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.425026689 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 219194016 ps |
| CPU time | 2.73 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:59 AM UTC 24 |
| Peak memory | 257768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=425026689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr _mem_rw_with_rand_reset.425026689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3915751343 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 120684281 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915751343 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3915751343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.3124687590 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 39352769 ps |
| CPU time | 1.75 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 239992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124687590 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3124687590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1549485701 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 124531287 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549485701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.1549485701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1264848411 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 56860869 ps |
| CPU time | 3.11 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:59 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264848411 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1264848411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2762447521 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1386405474 ps |
| CPU time | 9.79 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:44:06 AM UTC 24 |
| Peak memory | 251520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762447521 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.2762447521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3280946968 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 255168071 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 255692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3280946968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs r_mem_rw_with_rand_reset.3280946968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.571887446 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 47719696 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571887446 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.571887446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.3017033650 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 74603026 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 240196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017033650 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3017033650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3888100135 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 148274793 ps |
| CPU time | 3.79 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:44:00 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888100135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.3888100135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3393570510 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 522601309 ps |
| CPU time | 5.2 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:44:01 AM UTC 24 |
| Peak memory | 257860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393570510 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3393570510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3212248737 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2493130834 ps |
| CPU time | 9.32 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:44:05 AM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212248737 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3212248737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.266169359 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 1555607776 ps |
| CPU time | 4.56 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:44:01 AM UTC 24 |
| Peak memory | 257768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=266169359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr _mem_rw_with_rand_reset.266169359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1073127956 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 87840074 ps |
| CPU time | 2.09 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:59 AM UTC 24 |
| Peak memory | 253856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073127956 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1073127956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.672755633 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 141527007 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:58 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672755633 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.672755633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1939642743 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 47893377 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:43:59 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939642743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.1939642743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.487495246 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 373327176 ps |
| CPU time | 6.8 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:44:03 AM UTC 24 |
| Peak memory | 257856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487495246 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.487495246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.737131879 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2917869547 ps |
| CPU time | 20.36 seconds |
| Started | Oct 03 06:43:55 AM UTC 24 |
| Finished | Oct 03 06:44:17 AM UTC 24 |
| Peak memory | 255728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737131879 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.737131879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.5854794 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 405238536 ps |
| CPU time | 11.43 seconds |
| Started | Oct 03 06:28:56 AM UTC 24 |
| Finished | Oct 03 06:29:09 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5854794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.5854794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.2401142362 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 988533784 ps |
| CPU time | 22.92 seconds |
| Started | Oct 03 06:28:56 AM UTC 24 |
| Finished | Oct 03 06:29:20 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401142362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2401142362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.3713677302 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2225021958 ps |
| CPU time | 22.12 seconds |
| Started | Oct 03 06:28:56 AM UTC 24 |
| Finished | Oct 03 06:29:19 AM UTC 24 |
| Peak memory | 250956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713677302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3713677302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.1538482603 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3022549622 ps |
| CPU time | 15.55 seconds |
| Started | Oct 03 06:28:54 AM UTC 24 |
| Finished | Oct 03 06:29:11 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538482603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1538482603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.297050431 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6782017546 ps |
| CPU time | 34.23 seconds |
| Started | Oct 03 06:28:56 AM UTC 24 |
| Finished | Oct 03 06:29:31 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297050431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.297050431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.1472632888 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5085690396 ps |
| CPU time | 34.81 seconds |
| Started | Oct 03 06:28:54 AM UTC 24 |
| Finished | Oct 03 06:29:31 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472632888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1472632888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.2522478789 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 17241048376 ps |
| CPU time | 194.15 seconds |
| Started | Oct 03 06:29:03 AM UTC 24 |
| Finished | Oct 03 06:32:21 AM UTC 24 |
| Peak memory | 286368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522478789 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2522478789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.4254000995 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1030577161 ps |
| CPU time | 10 seconds |
| Started | Oct 03 06:28:54 AM UTC 24 |
| Finished | Oct 03 06:29:05 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254000995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.4254000995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.184484031 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3749393093 ps |
| CPU time | 19.58 seconds |
| Started | Oct 03 06:29:02 AM UTC 24 |
| Finished | Oct 03 06:29:23 AM UTC 24 |
| Peak memory | 257848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184484031 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.184484031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.4060944888 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 97535714 ps |
| CPU time | 2.83 seconds |
| Started | Oct 03 06:29:24 AM UTC 24 |
| Finished | Oct 03 06:29:28 AM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060944888 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.4060944888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.1955423015 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3183879257 ps |
| CPU time | 34.36 seconds |
| Started | Oct 03 06:29:09 AM UTC 24 |
| Finished | Oct 03 06:29:45 AM UTC 24 |
| Peak memory | 252180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955423015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1955423015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.3505419020 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4319569806 ps |
| CPU time | 41.2 seconds |
| Started | Oct 03 06:29:13 AM UTC 24 |
| Finished | Oct 03 06:29:56 AM UTC 24 |
| Peak memory | 258100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505419020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3505419020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.3702655077 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 931129078 ps |
| CPU time | 8.71 seconds |
| Started | Oct 03 06:29:12 AM UTC 24 |
| Finished | Oct 03 06:29:21 AM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702655077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3702655077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.1323792962 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 150474455 ps |
| CPU time | 3.39 seconds |
| Started | Oct 03 06:29:09 AM UTC 24 |
| Finished | Oct 03 06:29:14 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323792962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1323792962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.2496385867 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3167166056 ps |
| CPU time | 17.38 seconds |
| Started | Oct 03 06:29:15 AM UTC 24 |
| Finished | Oct 03 06:29:34 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496385867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2496385867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.915960895 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336057515 ps |
| CPU time | 11.29 seconds |
| Started | Oct 03 06:29:11 AM UTC 24 |
| Finished | Oct 03 06:29:23 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915960895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.915960895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.209105264 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1118800329 ps |
| CPU time | 26.33 seconds |
| Started | Oct 03 06:29:11 AM UTC 24 |
| Finished | Oct 03 06:29:38 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209105264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.209105264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.3887180682 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 364892200 ps |
| CPU time | 3.59 seconds |
| Started | Oct 03 06:29:18 AM UTC 24 |
| Finished | Oct 03 06:29:22 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887180682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3887180682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3900571515 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 37292194891 ps |
| CPU time | 225.4 seconds |
| Started | Oct 03 06:29:23 AM UTC 24 |
| Finished | Oct 03 06:33:12 AM UTC 24 |
| Peak memory | 286312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900571515 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3900571515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3859081642 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3000018987 ps |
| CPU time | 5.53 seconds |
| Started | Oct 03 06:29:09 AM UTC 24 |
| Finished | Oct 03 06:29:16 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859081642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3859081642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.1849045647 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 908789607 ps |
| CPU time | 16.22 seconds |
| Started | Oct 03 06:29:23 AM UTC 24 |
| Finished | Oct 03 06:29:41 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849045647 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.1849045647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.2551108032 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2716703718 ps |
| CPU time | 18.54 seconds |
| Started | Oct 03 06:29:20 AM UTC 24 |
| Finished | Oct 03 06:29:40 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551108032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2551108032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.3375350890 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 110863486 ps |
| CPU time | 3.19 seconds |
| Started | Oct 03 06:32:20 AM UTC 24 |
| Finished | Oct 03 06:32:24 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375350890 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3375350890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.3173555644 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1428735609 ps |
| CPU time | 15.86 seconds |
| Started | Oct 03 06:32:11 AM UTC 24 |
| Finished | Oct 03 06:32:28 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173555644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3173555644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.2287482686 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 20578226921 ps |
| CPU time | 56.28 seconds |
| Started | Oct 03 06:32:11 AM UTC 24 |
| Finished | Oct 03 06:33:08 AM UTC 24 |
| Peak memory | 260248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287482686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.2287482686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.4216224171 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 720946956 ps |
| CPU time | 27.33 seconds |
| Started | Oct 03 06:32:10 AM UTC 24 |
| Finished | Oct 03 06:32:39 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216224171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.4216224171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.3485211536 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1797963043 ps |
| CPU time | 8.21 seconds |
| Started | Oct 03 06:32:10 AM UTC 24 |
| Finished | Oct 03 06:32:20 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485211536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3485211536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.1076408863 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 828466946 ps |
| CPU time | 8 seconds |
| Started | Oct 03 06:32:11 AM UTC 24 |
| Finished | Oct 03 06:32:20 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076408863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.1076408863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.883956159 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3963296855 ps |
| CPU time | 34.22 seconds |
| Started | Oct 03 06:32:12 AM UTC 24 |
| Finished | Oct 03 06:32:48 AM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883956159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.883956159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.3972406333 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1861104362 ps |
| CPU time | 15.53 seconds |
| Started | Oct 03 06:32:10 AM UTC 24 |
| Finished | Oct 03 06:32:27 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972406333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.3972406333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.1155168507 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 665482837 ps |
| CPU time | 17.5 seconds |
| Started | Oct 03 06:32:10 AM UTC 24 |
| Finished | Oct 03 06:32:29 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155168507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1155168507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.1444917556 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 301022519 ps |
| CPU time | 9.02 seconds |
| Started | Oct 03 06:32:12 AM UTC 24 |
| Finished | Oct 03 06:32:22 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444917556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1444917556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.724571883 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 525961790 ps |
| CPU time | 13.56 seconds |
| Started | Oct 03 06:32:07 AM UTC 24 |
| Finished | Oct 03 06:32:22 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724571883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.724571883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.1711520117 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 483297951 ps |
| CPU time | 5.26 seconds |
| Started | Oct 03 06:41:53 AM UTC 24 |
| Finished | Oct 03 06:41:59 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711520117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1711520117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.1755080659 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 161621000 ps |
| CPU time | 6.65 seconds |
| Started | Oct 03 06:41:53 AM UTC 24 |
| Finished | Oct 03 06:42:00 AM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755080659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1755080659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.2828588861 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 154973593 ps |
| CPU time | 4.88 seconds |
| Started | Oct 03 06:41:53 AM UTC 24 |
| Finished | Oct 03 06:41:59 AM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828588861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2828588861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.74736279 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 318128882 ps |
| CPU time | 11.38 seconds |
| Started | Oct 03 06:41:53 AM UTC 24 |
| Finished | Oct 03 06:42:05 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74736279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.74736279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.1655935766 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1784984143 ps |
| CPU time | 9.04 seconds |
| Started | Oct 03 06:41:53 AM UTC 24 |
| Finished | Oct 03 06:42:03 AM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655935766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1655935766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.1958988864 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 411447411 ps |
| CPU time | 9.91 seconds |
| Started | Oct 03 06:41:53 AM UTC 24 |
| Finished | Oct 03 06:42:04 AM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958988864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1958988864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.379996756 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 466823730 ps |
| CPU time | 4.36 seconds |
| Started | Oct 03 06:41:55 AM UTC 24 |
| Finished | Oct 03 06:42:00 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379996756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.379996756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.3350081981 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 439427580 ps |
| CPU time | 16.3 seconds |
| Started | Oct 03 06:41:55 AM UTC 24 |
| Finished | Oct 03 06:42:12 AM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350081981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.3350081981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.818691766 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 64411083 ps |
| CPU time | 3.31 seconds |
| Started | Oct 03 06:42:00 AM UTC 24 |
| Finished | Oct 03 06:42:05 AM UTC 24 |
| Peak memory | 251592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818691766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.818691766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.51196117 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 230836640 ps |
| CPU time | 5.1 seconds |
| Started | Oct 03 06:42:00 AM UTC 24 |
| Finished | Oct 03 06:42:07 AM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51196117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.51196117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.2687709752 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 103216129 ps |
| CPU time | 4.57 seconds |
| Started | Oct 03 06:42:00 AM UTC 24 |
| Finished | Oct 03 06:42:06 AM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687709752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.2687709752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.3798757698 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 103197993 ps |
| CPU time | 5.31 seconds |
| Started | Oct 03 06:42:00 AM UTC 24 |
| Finished | Oct 03 06:42:07 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798757698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3798757698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.1517129483 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1201131735 ps |
| CPU time | 8.68 seconds |
| Started | Oct 03 06:42:01 AM UTC 24 |
| Finished | Oct 03 06:42:10 AM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517129483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.1517129483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.313806192 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 320864875 ps |
| CPU time | 6.02 seconds |
| Started | Oct 03 06:42:02 AM UTC 24 |
| Finished | Oct 03 06:42:09 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313806192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.313806192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.407719957 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1608242489 ps |
| CPU time | 8.3 seconds |
| Started | Oct 03 06:42:02 AM UTC 24 |
| Finished | Oct 03 06:42:12 AM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407719957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.407719957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.4147153289 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 95677727 ps |
| CPU time | 4.11 seconds |
| Started | Oct 03 06:42:02 AM UTC 24 |
| Finished | Oct 03 06:42:07 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147153289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.4147153289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.3548881940 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 213755184 ps |
| CPU time | 5.51 seconds |
| Started | Oct 03 06:42:04 AM UTC 24 |
| Finished | Oct 03 06:42:10 AM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548881940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3548881940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.2072346326 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 248748218 ps |
| CPU time | 5.15 seconds |
| Started | Oct 03 06:42:05 AM UTC 24 |
| Finished | Oct 03 06:42:11 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072346326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2072346326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.2611688709 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 48524209 ps |
| CPU time | 2.62 seconds |
| Started | Oct 03 06:32:32 AM UTC 24 |
| Finished | Oct 03 06:32:36 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611688709 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.2611688709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.2879849265 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5323802597 ps |
| CPU time | 40.19 seconds |
| Started | Oct 03 06:32:26 AM UTC 24 |
| Finished | Oct 03 06:33:08 AM UTC 24 |
| Peak memory | 256096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879849265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.2879849265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.4254063597 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1439592719 ps |
| CPU time | 30.61 seconds |
| Started | Oct 03 06:32:26 AM UTC 24 |
| Finished | Oct 03 06:32:58 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254063597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.4254063597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.3169959380 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 152104619 ps |
| CPU time | 5.72 seconds |
| Started | Oct 03 06:32:26 AM UTC 24 |
| Finished | Oct 03 06:32:33 AM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169959380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3169959380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.1427054163 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 551099550 ps |
| CPU time | 8.3 seconds |
| Started | Oct 03 06:32:26 AM UTC 24 |
| Finished | Oct 03 06:32:36 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427054163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.1427054163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.1183069461 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 4074103862 ps |
| CPU time | 16.67 seconds |
| Started | Oct 03 06:32:29 AM UTC 24 |
| Finished | Oct 03 06:32:47 AM UTC 24 |
| Peak memory | 253948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183069461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.1183069461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.447299535 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 486995424 ps |
| CPU time | 15.85 seconds |
| Started | Oct 03 06:32:26 AM UTC 24 |
| Finished | Oct 03 06:32:43 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447299535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.447299535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.2137582317 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1537661249 ps |
| CPU time | 31.51 seconds |
| Started | Oct 03 06:32:26 AM UTC 24 |
| Finished | Oct 03 06:32:59 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137582317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.2137582317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.3969250957 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 706681210 ps |
| CPU time | 8.72 seconds |
| Started | Oct 03 06:32:29 AM UTC 24 |
| Finished | Oct 03 06:32:39 AM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969250957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3969250957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.2745936321 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 949273813 ps |
| CPU time | 13.03 seconds |
| Started | Oct 03 06:32:20 AM UTC 24 |
| Finished | Oct 03 06:32:34 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745936321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2745936321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.3630092624 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2331054544 ps |
| CPU time | 27.85 seconds |
| Started | Oct 03 06:32:31 AM UTC 24 |
| Finished | Oct 03 06:33:00 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630092624 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.3630092624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.1682559373 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2040105331 ps |
| CPU time | 32.13 seconds |
| Started | Oct 03 06:32:29 AM UTC 24 |
| Finished | Oct 03 06:33:03 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682559373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1682559373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.952405458 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 418360408 ps |
| CPU time | 6.32 seconds |
| Started | Oct 03 06:42:05 AM UTC 24 |
| Finished | Oct 03 06:42:13 AM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952405458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.952405458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.2886284988 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 553704495 ps |
| CPU time | 8.66 seconds |
| Started | Oct 03 06:42:05 AM UTC 24 |
| Finished | Oct 03 06:42:15 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886284988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.2886284988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.3750937696 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 137915683 ps |
| CPU time | 5 seconds |
| Started | Oct 03 06:42:07 AM UTC 24 |
| Finished | Oct 03 06:42:13 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750937696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3750937696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.1573191856 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 1000672932 ps |
| CPU time | 8.9 seconds |
| Started | Oct 03 06:42:07 AM UTC 24 |
| Finished | Oct 03 06:42:17 AM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573191856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1573191856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.606700694 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 201280518 ps |
| CPU time | 5.12 seconds |
| Started | Oct 03 06:42:07 AM UTC 24 |
| Finished | Oct 03 06:42:13 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606700694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.606700694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.1270501612 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 223865510 ps |
| CPU time | 5.73 seconds |
| Started | Oct 03 06:42:07 AM UTC 24 |
| Finished | Oct 03 06:42:14 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270501612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1270501612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.741998770 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 886659461 ps |
| CPU time | 16.94 seconds |
| Started | Oct 03 06:42:09 AM UTC 24 |
| Finished | Oct 03 06:42:27 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741998770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.741998770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.3375337296 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 258316644 ps |
| CPU time | 5.84 seconds |
| Started | Oct 03 06:42:10 AM UTC 24 |
| Finished | Oct 03 06:42:17 AM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375337296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3375337296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.2537763838 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 316169725 ps |
| CPU time | 22.56 seconds |
| Started | Oct 03 06:42:10 AM UTC 24 |
| Finished | Oct 03 06:42:34 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537763838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2537763838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.1184975018 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 97600397 ps |
| CPU time | 3.75 seconds |
| Started | Oct 03 06:42:12 AM UTC 24 |
| Finished | Oct 03 06:42:17 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184975018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.1184975018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.1184854096 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 491281075 ps |
| CPU time | 5.05 seconds |
| Started | Oct 03 06:42:12 AM UTC 24 |
| Finished | Oct 03 06:42:18 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184854096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1184854096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.4291920188 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 685156774 ps |
| CPU time | 5.94 seconds |
| Started | Oct 03 06:42:12 AM UTC 24 |
| Finished | Oct 03 06:42:19 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291920188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.4291920188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.3011171072 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 85039969 ps |
| CPU time | 4.24 seconds |
| Started | Oct 03 06:42:12 AM UTC 24 |
| Finished | Oct 03 06:42:17 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011171072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.3011171072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.900051088 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 217008609 ps |
| CPU time | 5.76 seconds |
| Started | Oct 03 06:42:15 AM UTC 24 |
| Finished | Oct 03 06:42:22 AM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900051088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.900051088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.3234211093 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 1805513646 ps |
| CPU time | 4.85 seconds |
| Started | Oct 03 06:42:15 AM UTC 24 |
| Finished | Oct 03 06:42:21 AM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234211093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3234211093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.3265427118 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 1672485222 ps |
| CPU time | 29.73 seconds |
| Started | Oct 03 06:42:15 AM UTC 24 |
| Finished | Oct 03 06:42:46 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265427118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3265427118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.1859783404 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 1634764580 ps |
| CPU time | 5.9 seconds |
| Started | Oct 03 06:42:15 AM UTC 24 |
| Finished | Oct 03 06:42:22 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859783404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1859783404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.2127877402 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 1687899397 ps |
| CPU time | 22.42 seconds |
| Started | Oct 03 06:42:15 AM UTC 24 |
| Finished | Oct 03 06:42:39 AM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127877402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.2127877402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.2720303969 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 570617123 ps |
| CPU time | 6.04 seconds |
| Started | Oct 03 06:32:47 AM UTC 24 |
| Finished | Oct 03 06:32:54 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720303969 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.2720303969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.4286366848 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 900518686 ps |
| CPU time | 24.68 seconds |
| Started | Oct 03 06:32:39 AM UTC 24 |
| Finished | Oct 03 06:33:06 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286366848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.4286366848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.3579125675 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1929407512 ps |
| CPU time | 29.51 seconds |
| Started | Oct 03 06:32:39 AM UTC 24 |
| Finished | Oct 03 06:33:11 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579125675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3579125675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.2391186024 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 998699635 ps |
| CPU time | 25.22 seconds |
| Started | Oct 03 06:32:37 AM UTC 24 |
| Finished | Oct 03 06:33:04 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391186024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2391186024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.373797981 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 392997626 ps |
| CPU time | 4.8 seconds |
| Started | Oct 03 06:32:35 AM UTC 24 |
| Finished | Oct 03 06:32:41 AM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373797981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.373797981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.585253220 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 9768057850 ps |
| CPU time | 85.67 seconds |
| Started | Oct 03 06:32:41 AM UTC 24 |
| Finished | Oct 03 06:34:09 AM UTC 24 |
| Peak memory | 272480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585253220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.585253220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.3783518886 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 522620338 ps |
| CPU time | 6.12 seconds |
| Started | Oct 03 06:32:36 AM UTC 24 |
| Finished | Oct 03 06:32:43 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783518886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.3783518886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.1324807734 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1152497319 ps |
| CPU time | 19.75 seconds |
| Started | Oct 03 06:32:36 AM UTC 24 |
| Finished | Oct 03 06:32:57 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324807734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1324807734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.1390202347 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2085083369 ps |
| CPU time | 10.62 seconds |
| Started | Oct 03 06:32:43 AM UTC 24 |
| Finished | Oct 03 06:32:54 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390202347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1390202347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.575135745 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 314292418 ps |
| CPU time | 14.49 seconds |
| Started | Oct 03 06:32:33 AM UTC 24 |
| Finished | Oct 03 06:32:50 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575135745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.575135745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.2869047034 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13520200783 ps |
| CPU time | 55.52 seconds |
| Started | Oct 03 06:32:44 AM UTC 24 |
| Finished | Oct 03 06:33:41 AM UTC 24 |
| Peak memory | 258096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2869047034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.otp_ctrl_stress_all_with_rand_reset.2869047034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.1462564184 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 865443974 ps |
| CPU time | 13.63 seconds |
| Started | Oct 03 06:32:43 AM UTC 24 |
| Finished | Oct 03 06:32:58 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462564184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1462564184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.1906364913 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 178078707 ps |
| CPU time | 4.89 seconds |
| Started | Oct 03 06:42:15 AM UTC 24 |
| Finished | Oct 03 06:42:21 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906364913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.1906364913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.621600696 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 113493406 ps |
| CPU time | 6.31 seconds |
| Started | Oct 03 06:42:15 AM UTC 24 |
| Finished | Oct 03 06:42:22 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621600696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.621600696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.2749087163 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 2661064175 ps |
| CPU time | 7.94 seconds |
| Started | Oct 03 06:42:15 AM UTC 24 |
| Finished | Oct 03 06:42:24 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749087163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2749087163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.285439419 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 240005016 ps |
| CPU time | 13.8 seconds |
| Started | Oct 03 06:42:16 AM UTC 24 |
| Finished | Oct 03 06:42:31 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285439419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.285439419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.1774122517 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 2515716502 ps |
| CPU time | 7.22 seconds |
| Started | Oct 03 06:42:18 AM UTC 24 |
| Finished | Oct 03 06:42:26 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774122517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1774122517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.4213373078 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 156659790 ps |
| CPU time | 9.2 seconds |
| Started | Oct 03 06:42:18 AM UTC 24 |
| Finished | Oct 03 06:42:28 AM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213373078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.4213373078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.2864773859 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 156472090 ps |
| CPU time | 7.35 seconds |
| Started | Oct 03 06:42:18 AM UTC 24 |
| Finished | Oct 03 06:42:26 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864773859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.2864773859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.759515990 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 88221225 ps |
| CPU time | 4.63 seconds |
| Started | Oct 03 06:42:18 AM UTC 24 |
| Finished | Oct 03 06:42:24 AM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759515990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.759515990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.1982194325 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 133710697 ps |
| CPU time | 4.43 seconds |
| Started | Oct 03 06:42:18 AM UTC 24 |
| Finished | Oct 03 06:42:24 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982194325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1982194325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.1594148161 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 221614725 ps |
| CPU time | 7.85 seconds |
| Started | Oct 03 06:42:19 AM UTC 24 |
| Finished | Oct 03 06:42:28 AM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594148161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1594148161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.2879617821 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 189395314 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 06:42:20 AM UTC 24 |
| Finished | Oct 03 06:42:26 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879617821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2879617821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.4145656442 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 143065524 ps |
| CPU time | 3.93 seconds |
| Started | Oct 03 06:42:20 AM UTC 24 |
| Finished | Oct 03 06:42:25 AM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145656442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.4145656442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.1688193466 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 1708916922 ps |
| CPU time | 6.78 seconds |
| Started | Oct 03 06:42:22 AM UTC 24 |
| Finished | Oct 03 06:42:30 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688193466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1688193466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.3880472946 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 1315900122 ps |
| CPU time | 15.1 seconds |
| Started | Oct 03 06:42:22 AM UTC 24 |
| Finished | Oct 03 06:42:38 AM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880472946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.3880472946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.531854604 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 129437146 ps |
| CPU time | 5.81 seconds |
| Started | Oct 03 06:42:22 AM UTC 24 |
| Finished | Oct 03 06:42:29 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531854604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.531854604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.1043466276 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 252900846 ps |
| CPU time | 9.47 seconds |
| Started | Oct 03 06:42:24 AM UTC 24 |
| Finished | Oct 03 06:42:34 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043466276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.1043466276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.2329549677 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 172303971 ps |
| CPU time | 4.46 seconds |
| Started | Oct 03 06:42:24 AM UTC 24 |
| Finished | Oct 03 06:42:29 AM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329549677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2329549677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.2895124658 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 268789678 ps |
| CPU time | 5.7 seconds |
| Started | Oct 03 06:42:25 AM UTC 24 |
| Finished | Oct 03 06:42:32 AM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895124658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2895124658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.1620148489 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 425188765 ps |
| CPU time | 7.49 seconds |
| Started | Oct 03 06:42:25 AM UTC 24 |
| Finished | Oct 03 06:42:34 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620148489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1620148489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.4134842687 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 71047471 ps |
| CPU time | 3.02 seconds |
| Started | Oct 03 06:33:03 AM UTC 24 |
| Finished | Oct 03 06:33:07 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134842687 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.4134842687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.223787160 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 313152011 ps |
| CPU time | 11.02 seconds |
| Started | Oct 03 06:33:00 AM UTC 24 |
| Finished | Oct 03 06:33:12 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223787160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.223787160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.1040389622 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1020358103 ps |
| CPU time | 21.89 seconds |
| Started | Oct 03 06:32:55 AM UTC 24 |
| Finished | Oct 03 06:33:18 AM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040389622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1040389622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.3689174052 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1274479385 ps |
| CPU time | 19.38 seconds |
| Started | Oct 03 06:32:55 AM UTC 24 |
| Finished | Oct 03 06:33:16 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689174052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3689174052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.1226660260 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1590660678 ps |
| CPU time | 8.61 seconds |
| Started | Oct 03 06:32:49 AM UTC 24 |
| Finished | Oct 03 06:32:59 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226660260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.1226660260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.2080665664 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 21520705624 ps |
| CPU time | 267.04 seconds |
| Started | Oct 03 06:33:00 AM UTC 24 |
| Finished | Oct 03 06:37:31 AM UTC 24 |
| Peak memory | 268388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080665664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2080665664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.2739643759 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 987757288 ps |
| CPU time | 17.69 seconds |
| Started | Oct 03 06:33:00 AM UTC 24 |
| Finished | Oct 03 06:33:19 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739643759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2739643759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.529616788 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 460098625 ps |
| CPU time | 13.75 seconds |
| Started | Oct 03 06:32:51 AM UTC 24 |
| Finished | Oct 03 06:33:06 AM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529616788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.529616788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.3524552463 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2108667670 ps |
| CPU time | 16.94 seconds |
| Started | Oct 03 06:32:49 AM UTC 24 |
| Finished | Oct 03 06:33:08 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524552463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.3524552463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.3209048881 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1113950024 ps |
| CPU time | 14.5 seconds |
| Started | Oct 03 06:33:00 AM UTC 24 |
| Finished | Oct 03 06:33:16 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209048881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.3209048881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.2936099150 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 364171588 ps |
| CPU time | 8.14 seconds |
| Started | Oct 03 06:32:49 AM UTC 24 |
| Finished | Oct 03 06:32:59 AM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936099150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2936099150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.1941329202 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 57022891158 ps |
| CPU time | 172.37 seconds |
| Started | Oct 03 06:33:03 AM UTC 24 |
| Finished | Oct 03 06:35:58 AM UTC 24 |
| Peak memory | 268140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941329202 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.1941329202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.4290886343 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 841502499 ps |
| CPU time | 21.51 seconds |
| Started | Oct 03 06:33:00 AM UTC 24 |
| Finished | Oct 03 06:33:23 AM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290886343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.4290886343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.3946200615 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 635124820 ps |
| CPU time | 5.47 seconds |
| Started | Oct 03 06:42:25 AM UTC 24 |
| Finished | Oct 03 06:42:32 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946200615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.3946200615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.3603060414 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 16001098030 ps |
| CPU time | 39.57 seconds |
| Started | Oct 03 06:42:25 AM UTC 24 |
| Finished | Oct 03 06:43:07 AM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603060414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3603060414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.3675508156 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 489193648 ps |
| CPU time | 4.65 seconds |
| Started | Oct 03 06:42:26 AM UTC 24 |
| Finished | Oct 03 06:42:32 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675508156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.3675508156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.1053509354 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 473676650 ps |
| CPU time | 6.23 seconds |
| Started | Oct 03 06:42:28 AM UTC 24 |
| Finished | Oct 03 06:42:35 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053509354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1053509354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.2913223957 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1508321913 ps |
| CPU time | 10.39 seconds |
| Started | Oct 03 06:42:28 AM UTC 24 |
| Finished | Oct 03 06:42:40 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913223957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2913223957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.1620432302 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 120409393 ps |
| CPU time | 3.94 seconds |
| Started | Oct 03 06:42:28 AM UTC 24 |
| Finished | Oct 03 06:42:33 AM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620432302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1620432302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.1851680456 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 956416530 ps |
| CPU time | 16.73 seconds |
| Started | Oct 03 06:42:30 AM UTC 24 |
| Finished | Oct 03 06:42:48 AM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851680456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1851680456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.1840918109 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 126180099 ps |
| CPU time | 6.11 seconds |
| Started | Oct 03 06:42:30 AM UTC 24 |
| Finished | Oct 03 06:42:38 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840918109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1840918109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.2918385147 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3749205996 ps |
| CPU time | 19.62 seconds |
| Started | Oct 03 06:42:30 AM UTC 24 |
| Finished | Oct 03 06:42:51 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918385147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2918385147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.4221568787 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 74743079 ps |
| CPU time | 5.83 seconds |
| Started | Oct 03 06:42:31 AM UTC 24 |
| Finished | Oct 03 06:42:38 AM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221568787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.4221568787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.1339566601 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 107728977 ps |
| CPU time | 4.38 seconds |
| Started | Oct 03 06:42:32 AM UTC 24 |
| Finished | Oct 03 06:42:38 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339566601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1339566601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.3922627777 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 295905638 ps |
| CPU time | 11.27 seconds |
| Started | Oct 03 06:42:32 AM UTC 24 |
| Finished | Oct 03 06:42:45 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922627777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.3922627777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.1876178328 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 429973823 ps |
| CPU time | 4.44 seconds |
| Started | Oct 03 06:42:35 AM UTC 24 |
| Finished | Oct 03 06:42:41 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876178328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1876178328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.1493715805 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 1719645890 ps |
| CPU time | 12.65 seconds |
| Started | Oct 03 06:42:36 AM UTC 24 |
| Finished | Oct 03 06:42:49 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493715805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1493715805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.3395503635 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 237972073 ps |
| CPU time | 4.76 seconds |
| Started | Oct 03 06:42:36 AM UTC 24 |
| Finished | Oct 03 06:42:41 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395503635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3395503635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.2792875454 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 625986566 ps |
| CPU time | 16.82 seconds |
| Started | Oct 03 06:42:36 AM UTC 24 |
| Finished | Oct 03 06:42:54 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792875454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2792875454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.1406266267 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 137464801 ps |
| CPU time | 5.29 seconds |
| Started | Oct 03 06:42:36 AM UTC 24 |
| Finished | Oct 03 06:42:42 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406266267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1406266267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.1263544474 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 353254350 ps |
| CPU time | 8.39 seconds |
| Started | Oct 03 06:42:36 AM UTC 24 |
| Finished | Oct 03 06:42:45 AM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263544474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1263544474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.313650373 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 51493627 ps |
| CPU time | 2.48 seconds |
| Started | Oct 03 06:33:13 AM UTC 24 |
| Finished | Oct 03 06:33:16 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313650373 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.313650373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.4157727880 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 620289784 ps |
| CPU time | 14.14 seconds |
| Started | Oct 03 06:33:08 AM UTC 24 |
| Finished | Oct 03 06:33:23 AM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157727880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.4157727880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.2267655717 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 11658863425 ps |
| CPU time | 50.57 seconds |
| Started | Oct 03 06:33:08 AM UTC 24 |
| Finished | Oct 03 06:34:00 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267655717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.2267655717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.395849590 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1978161988 ps |
| CPU time | 26.69 seconds |
| Started | Oct 03 06:33:08 AM UTC 24 |
| Finished | Oct 03 06:33:36 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395849590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.395849590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.869635647 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 301219646 ps |
| CPU time | 4.63 seconds |
| Started | Oct 03 06:33:05 AM UTC 24 |
| Finished | Oct 03 06:33:10 AM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869635647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.869635647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.239973939 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1065914901 ps |
| CPU time | 10.62 seconds |
| Started | Oct 03 06:33:10 AM UTC 24 |
| Finished | Oct 03 06:33:22 AM UTC 24 |
| Peak memory | 256088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239973939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.239973939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.1413970302 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 996526389 ps |
| CPU time | 18.91 seconds |
| Started | Oct 03 06:33:10 AM UTC 24 |
| Finished | Oct 03 06:33:30 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413970302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1413970302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.2147253882 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 852154066 ps |
| CPU time | 7.37 seconds |
| Started | Oct 03 06:33:06 AM UTC 24 |
| Finished | Oct 03 06:33:14 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147253882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2147253882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.2680029927 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 10249828131 ps |
| CPU time | 33.76 seconds |
| Started | Oct 03 06:33:05 AM UTC 24 |
| Finished | Oct 03 06:33:40 AM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680029927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2680029927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.2812094431 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 837111528 ps |
| CPU time | 15.35 seconds |
| Started | Oct 03 06:33:10 AM UTC 24 |
| Finished | Oct 03 06:33:27 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812094431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2812094431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.1546368258 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 583975359 ps |
| CPU time | 6.28 seconds |
| Started | Oct 03 06:33:03 AM UTC 24 |
| Finished | Oct 03 06:33:10 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546368258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1546368258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.1288623344 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 25141252895 ps |
| CPU time | 192.54 seconds |
| Started | Oct 03 06:33:13 AM UTC 24 |
| Finished | Oct 03 06:36:28 AM UTC 24 |
| Peak memory | 284756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288623344 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.1288623344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.1389161463 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1667133783 ps |
| CPU time | 33.88 seconds |
| Started | Oct 03 06:33:12 AM UTC 24 |
| Finished | Oct 03 06:33:48 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389161463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1389161463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.2197689467 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 545172068 ps |
| CPU time | 5.62 seconds |
| Started | Oct 03 06:42:36 AM UTC 24 |
| Finished | Oct 03 06:42:43 AM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197689467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2197689467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.1159593412 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 134141450 ps |
| CPU time | 5.65 seconds |
| Started | Oct 03 06:42:36 AM UTC 24 |
| Finished | Oct 03 06:42:43 AM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159593412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1159593412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.3124118334 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 195869513 ps |
| CPU time | 5.33 seconds |
| Started | Oct 03 06:42:36 AM UTC 24 |
| Finished | Oct 03 06:42:42 AM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124118334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3124118334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.745547647 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 409866972 ps |
| CPU time | 6.31 seconds |
| Started | Oct 03 06:42:38 AM UTC 24 |
| Finished | Oct 03 06:42:45 AM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745547647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.745547647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.964345448 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 137294341 ps |
| CPU time | 5.15 seconds |
| Started | Oct 03 06:42:38 AM UTC 24 |
| Finished | Oct 03 06:42:44 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964345448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.964345448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.1481781547 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 170804797 ps |
| CPU time | 4.04 seconds |
| Started | Oct 03 06:42:38 AM UTC 24 |
| Finished | Oct 03 06:42:43 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481781547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1481781547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.2191544998 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 126210887 ps |
| CPU time | 4.71 seconds |
| Started | Oct 03 06:42:39 AM UTC 24 |
| Finished | Oct 03 06:42:45 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191544998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2191544998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.1093728774 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 235523800 ps |
| CPU time | 14.01 seconds |
| Started | Oct 03 06:42:39 AM UTC 24 |
| Finished | Oct 03 06:42:55 AM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093728774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.1093728774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.2149410176 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 112425301 ps |
| CPU time | 4.12 seconds |
| Started | Oct 03 06:42:39 AM UTC 24 |
| Finished | Oct 03 06:42:45 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149410176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2149410176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.1106394706 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 676513806 ps |
| CPU time | 16.49 seconds |
| Started | Oct 03 06:42:40 AM UTC 24 |
| Finished | Oct 03 06:42:57 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106394706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1106394706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.814430160 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 1956580431 ps |
| CPU time | 5.63 seconds |
| Started | Oct 03 06:42:41 AM UTC 24 |
| Finished | Oct 03 06:42:48 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814430160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.814430160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.2234185535 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 6219126079 ps |
| CPU time | 13.99 seconds |
| Started | Oct 03 06:42:41 AM UTC 24 |
| Finished | Oct 03 06:42:57 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234185535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.2234185535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.3173789535 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 155118052 ps |
| CPU time | 5.27 seconds |
| Started | Oct 03 06:42:42 AM UTC 24 |
| Finished | Oct 03 06:42:48 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173789535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3173789535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.2234401151 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 525294175 ps |
| CPU time | 14.72 seconds |
| Started | Oct 03 06:42:44 AM UTC 24 |
| Finished | Oct 03 06:43:00 AM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234401151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2234401151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.2341927379 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 145991193 ps |
| CPU time | 3.7 seconds |
| Started | Oct 03 06:42:44 AM UTC 24 |
| Finished | Oct 03 06:42:49 AM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341927379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2341927379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.3932348382 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 549118513 ps |
| CPU time | 8.06 seconds |
| Started | Oct 03 06:42:44 AM UTC 24 |
| Finished | Oct 03 06:42:53 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932348382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3932348382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.4091957040 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 219363018 ps |
| CPU time | 3.66 seconds |
| Started | Oct 03 06:42:44 AM UTC 24 |
| Finished | Oct 03 06:42:49 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091957040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.4091957040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.3984944996 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 16046343884 ps |
| CPU time | 42.69 seconds |
| Started | Oct 03 06:42:44 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984944996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.3984944996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.1367362535 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 208349132 ps |
| CPU time | 3.83 seconds |
| Started | Oct 03 06:42:44 AM UTC 24 |
| Finished | Oct 03 06:42:49 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367362535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1367362535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.1245923648 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 181185947 ps |
| CPU time | 4.89 seconds |
| Started | Oct 03 06:42:44 AM UTC 24 |
| Finished | Oct 03 06:42:50 AM UTC 24 |
| Peak memory | 257944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245923648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1245923648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.1382739384 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 177085756 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 06:33:26 AM UTC 24 |
| Finished | Oct 03 06:33:30 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382739384 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1382739384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.1267221397 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3394707800 ps |
| CPU time | 19 seconds |
| Started | Oct 03 06:33:19 AM UTC 24 |
| Finished | Oct 03 06:33:40 AM UTC 24 |
| Peak memory | 252120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267221397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1267221397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.4051044332 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 307980731 ps |
| CPU time | 20.22 seconds |
| Started | Oct 03 06:33:17 AM UTC 24 |
| Finished | Oct 03 06:33:38 AM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051044332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.4051044332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.1483390895 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2130398254 ps |
| CPU time | 8.61 seconds |
| Started | Oct 03 06:33:17 AM UTC 24 |
| Finished | Oct 03 06:33:26 AM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483390895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1483390895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.2118183515 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 518997553 ps |
| CPU time | 5.63 seconds |
| Started | Oct 03 06:33:17 AM UTC 24 |
| Finished | Oct 03 06:33:23 AM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118183515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.2118183515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.3673808732 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 7652465782 ps |
| CPU time | 30.18 seconds |
| Started | Oct 03 06:33:20 AM UTC 24 |
| Finished | Oct 03 06:33:51 AM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673808732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3673808732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.1515353062 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2622330427 ps |
| CPU time | 6.92 seconds |
| Started | Oct 03 06:33:25 AM UTC 24 |
| Finished | Oct 03 06:33:33 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515353062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1515353062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.1014184366 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 277716740 ps |
| CPU time | 5.69 seconds |
| Started | Oct 03 06:33:17 AM UTC 24 |
| Finished | Oct 03 06:33:23 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014184366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.1014184366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.1274558934 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1922446745 ps |
| CPU time | 25.32 seconds |
| Started | Oct 03 06:33:17 AM UTC 24 |
| Finished | Oct 03 06:33:43 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274558934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.1274558934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.3845491657 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 629453254 ps |
| CPU time | 7.36 seconds |
| Started | Oct 03 06:33:26 AM UTC 24 |
| Finished | Oct 03 06:33:34 AM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845491657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3845491657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.1704423016 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 958397302 ps |
| CPU time | 5.91 seconds |
| Started | Oct 03 06:33:17 AM UTC 24 |
| Finished | Oct 03 06:33:24 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704423016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.1704423016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.3990953457 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 27828827315 ps |
| CPU time | 115.87 seconds |
| Started | Oct 03 06:33:26 AM UTC 24 |
| Finished | Oct 03 06:35:24 AM UTC 24 |
| Peak memory | 258044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990953457 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.3990953457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2267292610 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 5142395669 ps |
| CPU time | 78.63 seconds |
| Started | Oct 03 06:33:26 AM UTC 24 |
| Finished | Oct 03 06:34:46 AM UTC 24 |
| Peak memory | 258156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2267292610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.otp_ctrl_stress_all_with_rand_reset.2267292610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.557995509 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 5062316523 ps |
| CPU time | 35.42 seconds |
| Started | Oct 03 06:33:26 AM UTC 24 |
| Finished | Oct 03 06:34:02 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557995509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.557995509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.305842842 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 169387027 ps |
| CPU time | 4.75 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:01 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305842842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.305842842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.391269754 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 424926068 ps |
| CPU time | 5.29 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:01 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391269754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.391269754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.1678920707 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 793624304 ps |
| CPU time | 9.86 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:06 AM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678920707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.1678920707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.3018913962 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 2096497437 ps |
| CPU time | 6.97 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:03 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018913962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3018913962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.1769957306 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 119838678 ps |
| CPU time | 4.24 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:00 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769957306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1769957306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.3642333903 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 1250883573 ps |
| CPU time | 9.64 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:06 AM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642333903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.3642333903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.736722417 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 442504397 ps |
| CPU time | 6.33 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:03 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736722417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.736722417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.2081665083 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 1143378629 ps |
| CPU time | 16.24 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:13 AM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081665083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2081665083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.199240846 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 316206627 ps |
| CPU time | 5.58 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:02 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199240846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.199240846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.980571589 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 4570860002 ps |
| CPU time | 37.29 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980571589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.980571589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.3285464051 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2302847194 ps |
| CPU time | 5.55 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:02 AM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285464051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3285464051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.54640851 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2818232143 ps |
| CPU time | 21 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:18 AM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54640851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.54640851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.4142035120 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 114615958 ps |
| CPU time | 4.92 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:01 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142035120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.4142035120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.1171773427 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 758736142 ps |
| CPU time | 8.96 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:05 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171773427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1171773427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.3901285963 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 1618404487 ps |
| CPU time | 5.28 seconds |
| Started | Oct 03 06:42:55 AM UTC 24 |
| Finished | Oct 03 06:43:02 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901285963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3901285963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.230117238 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 147887111 ps |
| CPU time | 5.95 seconds |
| Started | Oct 03 06:42:56 AM UTC 24 |
| Finished | Oct 03 06:43:03 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230117238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.230117238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.3073153500 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 398857515 ps |
| CPU time | 3.55 seconds |
| Started | Oct 03 06:42:56 AM UTC 24 |
| Finished | Oct 03 06:43:00 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073153500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.3073153500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.4129755579 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 102823040 ps |
| CPU time | 4.76 seconds |
| Started | Oct 03 06:42:56 AM UTC 24 |
| Finished | Oct 03 06:43:01 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129755579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.4129755579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.189224195 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 98076470 ps |
| CPU time | 2.74 seconds |
| Started | Oct 03 06:33:39 AM UTC 24 |
| Finished | Oct 03 06:33:43 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189224195 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.189224195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.3820126212 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 435464870 ps |
| CPU time | 4.69 seconds |
| Started | Oct 03 06:33:32 AM UTC 24 |
| Finished | Oct 03 06:33:38 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820126212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3820126212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.1190541868 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 947429075 ps |
| CPU time | 34.09 seconds |
| Started | Oct 03 06:33:32 AM UTC 24 |
| Finished | Oct 03 06:34:07 AM UTC 24 |
| Peak memory | 253924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190541868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1190541868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.4291396186 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 716886783 ps |
| CPU time | 18.19 seconds |
| Started | Oct 03 06:33:30 AM UTC 24 |
| Finished | Oct 03 06:33:50 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291396186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.4291396186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.2251408216 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 103888748 ps |
| CPU time | 5.95 seconds |
| Started | Oct 03 06:33:27 AM UTC 24 |
| Finished | Oct 03 06:33:34 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251408216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2251408216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.2594494504 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 22785781461 ps |
| CPU time | 50.14 seconds |
| Started | Oct 03 06:33:33 AM UTC 24 |
| Finished | Oct 03 06:34:25 AM UTC 24 |
| Peak memory | 258204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594494504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2594494504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.2869640129 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 218260047 ps |
| CPU time | 7.24 seconds |
| Started | Oct 03 06:33:34 AM UTC 24 |
| Finished | Oct 03 06:33:43 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869640129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2869640129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.3825360344 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 10593097987 ps |
| CPU time | 35.3 seconds |
| Started | Oct 03 06:33:29 AM UTC 24 |
| Finished | Oct 03 06:34:06 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825360344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3825360344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.2294279725 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 235286159 ps |
| CPU time | 9.65 seconds |
| Started | Oct 03 06:33:29 AM UTC 24 |
| Finished | Oct 03 06:33:40 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294279725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2294279725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.3038358693 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 131272860 ps |
| CPU time | 6.87 seconds |
| Started | Oct 03 06:33:34 AM UTC 24 |
| Finished | Oct 03 06:33:42 AM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038358693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.3038358693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.3352526313 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 253656682 ps |
| CPU time | 3.91 seconds |
| Started | Oct 03 06:33:26 AM UTC 24 |
| Finished | Oct 03 06:33:31 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352526313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.3352526313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.3045079287 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 906014542 ps |
| CPU time | 9.04 seconds |
| Started | Oct 03 06:33:36 AM UTC 24 |
| Finished | Oct 03 06:33:46 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045079287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3045079287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.1194784557 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 106610713 ps |
| CPU time | 3.67 seconds |
| Started | Oct 03 06:42:56 AM UTC 24 |
| Finished | Oct 03 06:43:00 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194784557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.1194784557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.2854353564 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 7053508264 ps |
| CPU time | 18.53 seconds |
| Started | Oct 03 06:42:56 AM UTC 24 |
| Finished | Oct 03 06:43:15 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854353564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2854353564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.678474321 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 298943108 ps |
| CPU time | 4.02 seconds |
| Started | Oct 03 06:42:56 AM UTC 24 |
| Finished | Oct 03 06:43:01 AM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678474321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.678474321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.938232212 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 322161973 ps |
| CPU time | 8.4 seconds |
| Started | Oct 03 06:43:00 AM UTC 24 |
| Finished | Oct 03 06:43:10 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938232212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.938232212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.3204708447 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 549896839 ps |
| CPU time | 4.45 seconds |
| Started | Oct 03 06:43:00 AM UTC 24 |
| Finished | Oct 03 06:43:06 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204708447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.3204708447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.1587248435 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1065273595 ps |
| CPU time | 8.16 seconds |
| Started | Oct 03 06:43:00 AM UTC 24 |
| Finished | Oct 03 06:43:09 AM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587248435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.1587248435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.916506894 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 330064523 ps |
| CPU time | 4.61 seconds |
| Started | Oct 03 06:43:00 AM UTC 24 |
| Finished | Oct 03 06:43:06 AM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916506894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.916506894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.304650354 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 301592980 ps |
| CPU time | 8.37 seconds |
| Started | Oct 03 06:43:00 AM UTC 24 |
| Finished | Oct 03 06:43:10 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304650354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.304650354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.208970898 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 1474160255 ps |
| CPU time | 3.56 seconds |
| Started | Oct 03 06:43:00 AM UTC 24 |
| Finished | Oct 03 06:43:05 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208970898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.208970898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.341193081 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 335103703 ps |
| CPU time | 4.16 seconds |
| Started | Oct 03 06:43:01 AM UTC 24 |
| Finished | Oct 03 06:43:06 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341193081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.341193081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.2485324398 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 138170540 ps |
| CPU time | 5.09 seconds |
| Started | Oct 03 06:43:01 AM UTC 24 |
| Finished | Oct 03 06:43:07 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485324398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2485324398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.3775892170 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 169227075 ps |
| CPU time | 8.12 seconds |
| Started | Oct 03 06:43:01 AM UTC 24 |
| Finished | Oct 03 06:43:10 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775892170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3775892170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.1679497508 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 103394148 ps |
| CPU time | 4.43 seconds |
| Started | Oct 03 06:43:01 AM UTC 24 |
| Finished | Oct 03 06:43:06 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679497508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1679497508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.1926827890 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 872204389 ps |
| CPU time | 7.22 seconds |
| Started | Oct 03 06:43:01 AM UTC 24 |
| Finished | Oct 03 06:43:09 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926827890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1926827890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.4223076203 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2287921368 ps |
| CPU time | 7.94 seconds |
| Started | Oct 03 06:43:02 AM UTC 24 |
| Finished | Oct 03 06:43:11 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223076203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.4223076203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.3471670348 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 1209808353 ps |
| CPU time | 5.61 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:09 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471670348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.3471670348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.3151379066 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 154728975 ps |
| CPU time | 4.28 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:08 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151379066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3151379066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.3884612650 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 117553716 ps |
| CPU time | 4.39 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:08 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884612650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3884612650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.3012405755 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 108668762 ps |
| CPU time | 4.93 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:09 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012405755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3012405755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.809339734 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 494915673 ps |
| CPU time | 7.1 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:11 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809339734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.809339734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.3621107303 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 53901404 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 06:33:51 AM UTC 24 |
| Finished | Oct 03 06:33:54 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621107303 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3621107303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.3948499458 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1393515689 ps |
| CPU time | 15.7 seconds |
| Started | Oct 03 06:33:45 AM UTC 24 |
| Finished | Oct 03 06:34:02 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948499458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3948499458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.2685516976 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 8263959152 ps |
| CPU time | 18.62 seconds |
| Started | Oct 03 06:33:45 AM UTC 24 |
| Finished | Oct 03 06:34:05 AM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685516976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2685516976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.1944952012 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 103938631 ps |
| CPU time | 5.76 seconds |
| Started | Oct 03 06:33:41 AM UTC 24 |
| Finished | Oct 03 06:33:48 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944952012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1944952012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.307652362 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 830941163 ps |
| CPU time | 23.58 seconds |
| Started | Oct 03 06:33:45 AM UTC 24 |
| Finished | Oct 03 06:34:10 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307652362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.307652362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.4155852958 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 6746932239 ps |
| CPU time | 23.14 seconds |
| Started | Oct 03 06:33:45 AM UTC 24 |
| Finished | Oct 03 06:34:10 AM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155852958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.4155852958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.2344312303 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1586126276 ps |
| CPU time | 13.75 seconds |
| Started | Oct 03 06:33:45 AM UTC 24 |
| Finished | Oct 03 06:34:00 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344312303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.2344312303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.2916552671 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1266418820 ps |
| CPU time | 35.27 seconds |
| Started | Oct 03 06:33:41 AM UTC 24 |
| Finished | Oct 03 06:34:18 AM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916552671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.2916552671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.2189282151 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 465406665 ps |
| CPU time | 8.44 seconds |
| Started | Oct 03 06:33:46 AM UTC 24 |
| Finished | Oct 03 06:33:55 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189282151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2189282151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.2822698796 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 806779077 ps |
| CPU time | 13.65 seconds |
| Started | Oct 03 06:33:41 AM UTC 24 |
| Finished | Oct 03 06:33:56 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822698796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2822698796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.4139200007 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2272362460 ps |
| CPU time | 37.04 seconds |
| Started | Oct 03 06:33:47 AM UTC 24 |
| Finished | Oct 03 06:34:25 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139200007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.4139200007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.248751837 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2203730828 ps |
| CPU time | 4.37 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:08 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248751837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.248751837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.104115810 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 225248481 ps |
| CPU time | 4.26 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:08 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104115810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.104115810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.2704949968 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 210476342 ps |
| CPU time | 4.22 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:08 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704949968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2704949968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.640958419 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 436623659 ps |
| CPU time | 10.12 seconds |
| Started | Oct 03 06:43:03 AM UTC 24 |
| Finished | Oct 03 06:43:14 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640958419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.640958419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.249029735 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 223157674 ps |
| CPU time | 3.15 seconds |
| Started | Oct 03 06:43:05 AM UTC 24 |
| Finished | Oct 03 06:43:10 AM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249029735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.249029735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.2210994522 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 811354038 ps |
| CPU time | 5.7 seconds |
| Started | Oct 03 06:43:06 AM UTC 24 |
| Finished | Oct 03 06:43:12 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210994522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.2210994522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.3781729105 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 499007261 ps |
| CPU time | 3.99 seconds |
| Started | Oct 03 06:43:06 AM UTC 24 |
| Finished | Oct 03 06:43:11 AM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781729105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3781729105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.1787495950 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 1834576766 ps |
| CPU time | 5.96 seconds |
| Started | Oct 03 06:43:06 AM UTC 24 |
| Finished | Oct 03 06:43:13 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787495950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.1787495950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.307998180 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 137794323 ps |
| CPU time | 4.26 seconds |
| Started | Oct 03 06:43:06 AM UTC 24 |
| Finished | Oct 03 06:43:11 AM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307998180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.307998180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.4093410866 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 152866707 ps |
| CPU time | 4.54 seconds |
| Started | Oct 03 06:43:06 AM UTC 24 |
| Finished | Oct 03 06:43:11 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093410866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.4093410866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.2768669464 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 530455309 ps |
| CPU time | 3.75 seconds |
| Started | Oct 03 06:43:06 AM UTC 24 |
| Finished | Oct 03 06:43:11 AM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768669464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2768669464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.103242502 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1249933121 ps |
| CPU time | 10.97 seconds |
| Started | Oct 03 06:43:06 AM UTC 24 |
| Finished | Oct 03 06:43:18 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103242502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.103242502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.3154155902 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 261384956 ps |
| CPU time | 4.36 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:13 AM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154155902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3154155902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.3948917655 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 818409085 ps |
| CPU time | 10.82 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:20 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948917655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.3948917655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.2285207319 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 1333609244 ps |
| CPU time | 5.49 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:15 AM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285207319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2285207319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.1880421162 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 406354806 ps |
| CPU time | 6.04 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:15 AM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880421162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1880421162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.234609900 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 1709652614 ps |
| CPU time | 7.08 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:16 AM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234609900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.234609900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.1477995632 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 649346489 ps |
| CPU time | 10.1 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:19 AM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477995632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.1477995632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.1158672685 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 592960481 ps |
| CPU time | 4.83 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:14 AM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158672685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.1158672685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.2044525949 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 533043282 ps |
| CPU time | 5.14 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:14 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044525949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2044525949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.3955146103 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 112138195 ps |
| CPU time | 2.99 seconds |
| Started | Oct 03 06:34:10 AM UTC 24 |
| Finished | Oct 03 06:34:14 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955146103 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3955146103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.2040763925 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1183855870 ps |
| CPU time | 11.51 seconds |
| Started | Oct 03 06:34:01 AM UTC 24 |
| Finished | Oct 03 06:34:14 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040763925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2040763925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.2242576236 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 244304214 ps |
| CPU time | 13.78 seconds |
| Started | Oct 03 06:34:01 AM UTC 24 |
| Finished | Oct 03 06:34:16 AM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242576236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2242576236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.139552394 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 723392939 ps |
| CPU time | 8.76 seconds |
| Started | Oct 03 06:33:58 AM UTC 24 |
| Finished | Oct 03 06:34:07 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139552394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.139552394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.2530711693 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 163371801 ps |
| CPU time | 6.54 seconds |
| Started | Oct 03 06:33:57 AM UTC 24 |
| Finished | Oct 03 06:34:05 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530711693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2530711693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.3804271211 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 7124707972 ps |
| CPU time | 60.25 seconds |
| Started | Oct 03 06:34:04 AM UTC 24 |
| Finished | Oct 03 06:35:06 AM UTC 24 |
| Peak memory | 268440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804271211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.3804271211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.240744697 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2540204995 ps |
| CPU time | 33.26 seconds |
| Started | Oct 03 06:34:04 AM UTC 24 |
| Finished | Oct 03 06:34:39 AM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240744697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.240744697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.3935135250 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 318820646 ps |
| CPU time | 9.8 seconds |
| Started | Oct 03 06:33:57 AM UTC 24 |
| Finished | Oct 03 06:34:08 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935135250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3935135250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.1704669168 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 5208920376 ps |
| CPU time | 18.43 seconds |
| Started | Oct 03 06:33:57 AM UTC 24 |
| Finished | Oct 03 06:34:17 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704669168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.1704669168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.1082763091 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 293189046 ps |
| CPU time | 12.86 seconds |
| Started | Oct 03 06:34:10 AM UTC 24 |
| Finished | Oct 03 06:34:24 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082763091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1082763091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.3946910438 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 857035768 ps |
| CPU time | 11.66 seconds |
| Started | Oct 03 06:33:52 AM UTC 24 |
| Finished | Oct 03 06:34:05 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946910438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3946910438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.3410705597 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 44739244298 ps |
| CPU time | 68.27 seconds |
| Started | Oct 03 06:34:10 AM UTC 24 |
| Finished | Oct 03 06:35:20 AM UTC 24 |
| Peak memory | 258124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410705597 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.3410705597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.219342417 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 813707879 ps |
| CPU time | 14.3 seconds |
| Started | Oct 03 06:34:10 AM UTC 24 |
| Finished | Oct 03 06:34:26 AM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219342417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.219342417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.3124283751 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 301392522 ps |
| CPU time | 3.14 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:12 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124283751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3124283751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.1921398516 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 484253720 ps |
| CPU time | 7.47 seconds |
| Started | Oct 03 06:43:08 AM UTC 24 |
| Finished | Oct 03 06:43:17 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921398516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1921398516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.3671527143 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 598782662 ps |
| CPU time | 4.69 seconds |
| Started | Oct 03 06:43:10 AM UTC 24 |
| Finished | Oct 03 06:43:16 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671527143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3671527143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.540658386 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 3369808703 ps |
| CPU time | 14.54 seconds |
| Started | Oct 03 06:43:10 AM UTC 24 |
| Finished | Oct 03 06:43:26 AM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540658386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.540658386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.3111779365 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 2055134621 ps |
| CPU time | 4.72 seconds |
| Started | Oct 03 06:43:10 AM UTC 24 |
| Finished | Oct 03 06:43:16 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111779365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.3111779365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.3701033135 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 587886098 ps |
| CPU time | 4.89 seconds |
| Started | Oct 03 06:43:10 AM UTC 24 |
| Finished | Oct 03 06:43:16 AM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701033135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.3701033135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.278825920 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 368107661 ps |
| CPU time | 9.64 seconds |
| Started | Oct 03 06:43:10 AM UTC 24 |
| Finished | Oct 03 06:43:21 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278825920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.278825920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.589398628 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2759847314 ps |
| CPU time | 7.85 seconds |
| Started | Oct 03 06:43:11 AM UTC 24 |
| Finished | Oct 03 06:43:19 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589398628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.589398628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.2492584370 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 501172838 ps |
| CPU time | 14.72 seconds |
| Started | Oct 03 06:43:11 AM UTC 24 |
| Finished | Oct 03 06:43:26 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492584370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2492584370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.2056864759 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 175315641 ps |
| CPU time | 4.47 seconds |
| Started | Oct 03 06:43:11 AM UTC 24 |
| Finished | Oct 03 06:43:16 AM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056864759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.2056864759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.2823195306 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 4561328691 ps |
| CPU time | 11.94 seconds |
| Started | Oct 03 06:43:11 AM UTC 24 |
| Finished | Oct 03 06:43:24 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823195306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2823195306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.3569537872 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 262532003 ps |
| CPU time | 4.53 seconds |
| Started | Oct 03 06:43:11 AM UTC 24 |
| Finished | Oct 03 06:43:16 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569537872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3569537872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.1698358059 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 105417342 ps |
| CPU time | 4.42 seconds |
| Started | Oct 03 06:43:12 AM UTC 24 |
| Finished | Oct 03 06:43:18 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698358059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1698358059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.3216789880 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 1396889269 ps |
| CPU time | 18.15 seconds |
| Started | Oct 03 06:43:12 AM UTC 24 |
| Finished | Oct 03 06:43:32 AM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216789880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3216789880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.4168171811 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 255708938 ps |
| CPU time | 5.16 seconds |
| Started | Oct 03 06:43:12 AM UTC 24 |
| Finished | Oct 03 06:43:19 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168171811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.4168171811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.1202416565 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 155948029 ps |
| CPU time | 4.73 seconds |
| Started | Oct 03 06:43:13 AM UTC 24 |
| Finished | Oct 03 06:43:18 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202416565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.1202416565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.3463466662 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 401420558 ps |
| CPU time | 3.64 seconds |
| Started | Oct 03 06:43:13 AM UTC 24 |
| Finished | Oct 03 06:43:17 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463466662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.3463466662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.274296147 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 4901408407 ps |
| CPU time | 14.83 seconds |
| Started | Oct 03 06:43:13 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274296147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.274296147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.1031095144 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 156559484 ps |
| CPU time | 2.81 seconds |
| Started | Oct 03 06:34:18 AM UTC 24 |
| Finished | Oct 03 06:34:22 AM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031095144 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.1031095144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.1951938236 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2900428757 ps |
| CPU time | 26.42 seconds |
| Started | Oct 03 06:34:14 AM UTC 24 |
| Finished | Oct 03 06:34:42 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951938236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1951938236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.2058154104 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 614912799 ps |
| CPU time | 19.73 seconds |
| Started | Oct 03 06:34:14 AM UTC 24 |
| Finished | Oct 03 06:34:35 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058154104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2058154104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.4209776724 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2028763890 ps |
| CPU time | 22.97 seconds |
| Started | Oct 03 06:34:14 AM UTC 24 |
| Finished | Oct 03 06:34:39 AM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209776724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.4209776724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.3888838554 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 414082733 ps |
| CPU time | 4.55 seconds |
| Started | Oct 03 06:34:11 AM UTC 24 |
| Finished | Oct 03 06:34:16 AM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888838554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.3888838554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.1411207603 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 995793370 ps |
| CPU time | 19.25 seconds |
| Started | Oct 03 06:34:14 AM UTC 24 |
| Finished | Oct 03 06:34:35 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411207603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.1411207603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.3057442481 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 115336235 ps |
| CPU time | 6.34 seconds |
| Started | Oct 03 06:34:14 AM UTC 24 |
| Finished | Oct 03 06:34:22 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057442481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3057442481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.2988987312 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 7106666464 ps |
| CPU time | 27.07 seconds |
| Started | Oct 03 06:34:14 AM UTC 24 |
| Finished | Oct 03 06:34:43 AM UTC 24 |
| Peak memory | 252096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988987312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2988987312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.1834198163 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 153512491 ps |
| CPU time | 7.75 seconds |
| Started | Oct 03 06:34:15 AM UTC 24 |
| Finished | Oct 03 06:34:25 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834198163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1834198163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.526135763 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5408641927 ps |
| CPU time | 19.18 seconds |
| Started | Oct 03 06:34:11 AM UTC 24 |
| Finished | Oct 03 06:34:31 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526135763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.526135763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.299171320 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 801557880 ps |
| CPU time | 23.68 seconds |
| Started | Oct 03 06:34:16 AM UTC 24 |
| Finished | Oct 03 06:34:41 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299171320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.299171320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.4063893277 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 547554343 ps |
| CPU time | 4.13 seconds |
| Started | Oct 03 06:43:13 AM UTC 24 |
| Finished | Oct 03 06:43:18 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063893277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.4063893277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3999069787 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 592156792 ps |
| CPU time | 8.68 seconds |
| Started | Oct 03 06:43:13 AM UTC 24 |
| Finished | Oct 03 06:43:23 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999069787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3999069787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.3262259524 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 524694400 ps |
| CPU time | 4.61 seconds |
| Started | Oct 03 06:43:13 AM UTC 24 |
| Finished | Oct 03 06:43:18 AM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262259524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3262259524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.4011992614 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 283522477 ps |
| CPU time | 5.46 seconds |
| Started | Oct 03 06:43:15 AM UTC 24 |
| Finished | Oct 03 06:43:21 AM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011992614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.4011992614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.1401680529 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 508407647 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 06:43:15 AM UTC 24 |
| Finished | Oct 03 06:43:19 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401680529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1401680529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.3835946058 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 129688270 ps |
| CPU time | 5.45 seconds |
| Started | Oct 03 06:43:15 AM UTC 24 |
| Finished | Oct 03 06:43:21 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835946058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3835946058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.3243730427 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2164329576 ps |
| CPU time | 5.07 seconds |
| Started | Oct 03 06:43:15 AM UTC 24 |
| Finished | Oct 03 06:43:21 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243730427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3243730427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.1874085014 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 416019716 ps |
| CPU time | 11.02 seconds |
| Started | Oct 03 06:43:15 AM UTC 24 |
| Finished | Oct 03 06:43:27 AM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874085014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1874085014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.3341941722 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2068914951 ps |
| CPU time | 5.53 seconds |
| Started | Oct 03 06:43:15 AM UTC 24 |
| Finished | Oct 03 06:43:21 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341941722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.3341941722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.1843369476 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 765988614 ps |
| CPU time | 20.13 seconds |
| Started | Oct 03 06:43:16 AM UTC 24 |
| Finished | Oct 03 06:43:38 AM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843369476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1843369476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.1249146024 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 180462073 ps |
| CPU time | 4.97 seconds |
| Started | Oct 03 06:43:16 AM UTC 24 |
| Finished | Oct 03 06:43:22 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249146024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1249146024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.1941333547 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 1049378927 ps |
| CPU time | 13.7 seconds |
| Started | Oct 03 06:43:17 AM UTC 24 |
| Finished | Oct 03 06:43:31 AM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941333547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1941333547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2225469384 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 1915389046 ps |
| CPU time | 6.62 seconds |
| Started | Oct 03 06:43:17 AM UTC 24 |
| Finished | Oct 03 06:43:24 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225469384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2225469384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.160219169 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 213797047 ps |
| CPU time | 6.01 seconds |
| Started | Oct 03 06:43:17 AM UTC 24 |
| Finished | Oct 03 06:43:24 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160219169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.160219169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.2962712900 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 762364330 ps |
| CPU time | 6.59 seconds |
| Started | Oct 03 06:43:17 AM UTC 24 |
| Finished | Oct 03 06:43:24 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962712900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.2962712900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.1328217270 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 743065328 ps |
| CPU time | 8.39 seconds |
| Started | Oct 03 06:43:18 AM UTC 24 |
| Finished | Oct 03 06:43:27 AM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328217270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1328217270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.3037599951 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 1668303451 ps |
| CPU time | 5.97 seconds |
| Started | Oct 03 06:43:18 AM UTC 24 |
| Finished | Oct 03 06:43:25 AM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037599951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3037599951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.2912034236 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 1898517752 ps |
| CPU time | 8.11 seconds |
| Started | Oct 03 06:43:18 AM UTC 24 |
| Finished | Oct 03 06:43:27 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912034236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2912034236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.118583694 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 230245011 ps |
| CPU time | 4.33 seconds |
| Started | Oct 03 06:43:18 AM UTC 24 |
| Finished | Oct 03 06:43:24 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118583694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.118583694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.1177379229 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 273148323 ps |
| CPU time | 5.41 seconds |
| Started | Oct 03 06:43:18 AM UTC 24 |
| Finished | Oct 03 06:43:25 AM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177379229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1177379229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.484709000 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 43442444 ps |
| CPU time | 2.37 seconds |
| Started | Oct 03 06:29:46 AM UTC 24 |
| Finished | Oct 03 06:29:50 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484709000 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.484709000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.961832628 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 491837063 ps |
| CPU time | 13.59 seconds |
| Started | Oct 03 06:29:29 AM UTC 24 |
| Finished | Oct 03 06:29:44 AM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961832628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.961832628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.1613975193 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3597005067 ps |
| CPU time | 30.38 seconds |
| Started | Oct 03 06:29:35 AM UTC 24 |
| Finished | Oct 03 06:30:07 AM UTC 24 |
| Peak memory | 254084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613975193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1613975193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.3436359516 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 14198377597 ps |
| CPU time | 24.98 seconds |
| Started | Oct 03 06:29:40 AM UTC 24 |
| Finished | Oct 03 06:30:06 AM UTC 24 |
| Peak memory | 254024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436359516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3436359516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.2754565559 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3077086430 ps |
| CPU time | 32.15 seconds |
| Started | Oct 03 06:29:40 AM UTC 24 |
| Finished | Oct 03 06:30:13 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754565559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2754565559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.2759633148 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 908568243 ps |
| CPU time | 14.99 seconds |
| Started | Oct 03 06:29:32 AM UTC 24 |
| Finished | Oct 03 06:29:49 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759633148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2759633148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.1791657476 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2069570231 ps |
| CPU time | 9 seconds |
| Started | Oct 03 06:29:43 AM UTC 24 |
| Finished | Oct 03 06:29:53 AM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791657476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1791657476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.3317932356 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10506463309 ps |
| CPU time | 194.89 seconds |
| Started | Oct 03 06:29:43 AM UTC 24 |
| Finished | Oct 03 06:33:02 AM UTC 24 |
| Peak memory | 296572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317932356 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3317932356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.918164444 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4204205206 ps |
| CPU time | 15.96 seconds |
| Started | Oct 03 06:29:43 AM UTC 24 |
| Finished | Oct 03 06:30:00 AM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918164444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.918164444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.2987619621 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 132347961 ps |
| CPU time | 2.86 seconds |
| Started | Oct 03 06:34:39 AM UTC 24 |
| Finished | Oct 03 06:34:43 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987619621 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.2987619621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.1944510433 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 691657614 ps |
| CPU time | 15.93 seconds |
| Started | Oct 03 06:34:27 AM UTC 24 |
| Finished | Oct 03 06:34:44 AM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944510433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1944510433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.1821612463 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1768356687 ps |
| CPU time | 26.23 seconds |
| Started | Oct 03 06:34:27 AM UTC 24 |
| Finished | Oct 03 06:34:55 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821612463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.1821612463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.3042071263 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 294314451 ps |
| CPU time | 8.73 seconds |
| Started | Oct 03 06:34:27 AM UTC 24 |
| Finished | Oct 03 06:34:37 AM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042071263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3042071263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.1478733294 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 156928154 ps |
| CPU time | 5.19 seconds |
| Started | Oct 03 06:34:22 AM UTC 24 |
| Finished | Oct 03 06:34:29 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478733294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1478733294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.1252654311 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1151441549 ps |
| CPU time | 15.72 seconds |
| Started | Oct 03 06:34:27 AM UTC 24 |
| Finished | Oct 03 06:34:44 AM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252654311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1252654311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.2304514623 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 699802179 ps |
| CPU time | 27.95 seconds |
| Started | Oct 03 06:34:23 AM UTC 24 |
| Finished | Oct 03 06:34:53 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304514623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2304514623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.2158009396 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 868276737 ps |
| CPU time | 16.94 seconds |
| Started | Oct 03 06:34:20 AM UTC 24 |
| Finished | Oct 03 06:34:38 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158009396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.2158009396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.584953078 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2837688080 ps |
| CPU time | 37.86 seconds |
| Started | Oct 03 06:34:39 AM UTC 24 |
| Finished | Oct 03 06:35:19 AM UTC 24 |
| Peak memory | 255988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584953078 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.584953078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.2745983682 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5568608051 ps |
| CPU time | 20.64 seconds |
| Started | Oct 03 06:34:34 AM UTC 24 |
| Finished | Oct 03 06:34:56 AM UTC 24 |
| Peak memory | 252104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745983682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.2745983682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.2790778186 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 2617156192 ps |
| CPU time | 9.86 seconds |
| Started | Oct 03 06:43:18 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790778186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.2790778186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.2593667276 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 449070483 ps |
| CPU time | 4.18 seconds |
| Started | Oct 03 06:43:18 AM UTC 24 |
| Finished | Oct 03 06:43:24 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593667276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2593667276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.3163578199 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 156463379 ps |
| CPU time | 5.63 seconds |
| Started | Oct 03 06:43:18 AM UTC 24 |
| Finished | Oct 03 06:43:25 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163578199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.3163578199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.500840879 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 402501499 ps |
| CPU time | 5.32 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:27 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500840879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.500840879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.4238413056 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 207301485 ps |
| CPU time | 5.74 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:27 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238413056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.4238413056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.504631765 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2225433308 ps |
| CPU time | 7.38 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504631765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.504631765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.449620455 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 650690319 ps |
| CPU time | 4.44 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:26 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449620455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.449620455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.1569168921 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 1880452669 ps |
| CPU time | 3.71 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:25 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569168921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1569168921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.3411397698 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 208310586 ps |
| CPU time | 5.26 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:27 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411397698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3411397698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.4213073007 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 376899880 ps |
| CPU time | 4.16 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:26 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213073007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.4213073007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.2084018527 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 188023831 ps |
| CPU time | 3.59 seconds |
| Started | Oct 03 06:34:46 AM UTC 24 |
| Finished | Oct 03 06:34:51 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084018527 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2084018527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.2315464680 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 21443613755 ps |
| CPU time | 52.32 seconds |
| Started | Oct 03 06:34:42 AM UTC 24 |
| Finished | Oct 03 06:35:36 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315464680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2315464680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.1939145939 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 8914473381 ps |
| CPU time | 27.97 seconds |
| Started | Oct 03 06:34:42 AM UTC 24 |
| Finished | Oct 03 06:35:12 AM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939145939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1939145939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.1421158692 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1547576724 ps |
| CPU time | 25.3 seconds |
| Started | Oct 03 06:34:42 AM UTC 24 |
| Finished | Oct 03 06:35:09 AM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421158692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1421158692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.574808459 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 227066296 ps |
| CPU time | 4.87 seconds |
| Started | Oct 03 06:34:40 AM UTC 24 |
| Finished | Oct 03 06:34:45 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574808459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.574808459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.3590997273 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 393534654 ps |
| CPU time | 4.77 seconds |
| Started | Oct 03 06:34:45 AM UTC 24 |
| Finished | Oct 03 06:34:50 AM UTC 24 |
| Peak memory | 251724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590997273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3590997273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.1507983930 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1434308935 ps |
| CPU time | 27.01 seconds |
| Started | Oct 03 06:34:45 AM UTC 24 |
| Finished | Oct 03 06:35:13 AM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507983930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1507983930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.1052399132 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 570757224 ps |
| CPU time | 13.02 seconds |
| Started | Oct 03 06:34:42 AM UTC 24 |
| Finished | Oct 03 06:34:56 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052399132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.1052399132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.317422080 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1774853644 ps |
| CPU time | 26.28 seconds |
| Started | Oct 03 06:34:40 AM UTC 24 |
| Finished | Oct 03 06:35:07 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317422080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.317422080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.2856011444 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 181065025 ps |
| CPU time | 9 seconds |
| Started | Oct 03 06:34:45 AM UTC 24 |
| Finished | Oct 03 06:34:55 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856011444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.2856011444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.2140178330 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 4076126286 ps |
| CPU time | 18.86 seconds |
| Started | Oct 03 06:34:40 AM UTC 24 |
| Finished | Oct 03 06:35:00 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140178330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2140178330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.3103126388 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 14793272145 ps |
| CPU time | 157.19 seconds |
| Started | Oct 03 06:34:46 AM UTC 24 |
| Finished | Oct 03 06:37:26 AM UTC 24 |
| Peak memory | 268424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103126388 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.3103126388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.2873024748 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1595056293 ps |
| CPU time | 10.08 seconds |
| Started | Oct 03 06:34:45 AM UTC 24 |
| Finished | Oct 03 06:34:56 AM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873024748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2873024748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.3183101313 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 176803908 ps |
| CPU time | 4.89 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:26 AM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183101313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3183101313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.1507929894 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 1912430146 ps |
| CPU time | 6.97 seconds |
| Started | Oct 03 06:43:20 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507929894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1507929894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.152506965 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 392886771 ps |
| CPU time | 4.27 seconds |
| Started | Oct 03 06:43:23 AM UTC 24 |
| Finished | Oct 03 06:43:28 AM UTC 24 |
| Peak memory | 251584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152506965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.152506965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.393255874 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 452188531 ps |
| CPU time | 4.11 seconds |
| Started | Oct 03 06:43:23 AM UTC 24 |
| Finished | Oct 03 06:43:28 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393255874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.393255874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.3271794158 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 186137933 ps |
| CPU time | 5.14 seconds |
| Started | Oct 03 06:43:23 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271794158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3271794158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.1845019793 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 417980636 ps |
| CPU time | 4.63 seconds |
| Started | Oct 03 06:43:23 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845019793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1845019793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.2692868756 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 147941415 ps |
| CPU time | 4.33 seconds |
| Started | Oct 03 06:43:23 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692868756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2692868756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.884782948 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 1994500841 ps |
| CPU time | 4.65 seconds |
| Started | Oct 03 06:43:23 AM UTC 24 |
| Finished | Oct 03 06:43:29 AM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884782948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.884782948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.4153206120 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 50023322 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 06:34:59 AM UTC 24 |
| Finished | Oct 03 06:35:02 AM UTC 24 |
| Peak memory | 250580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153206120 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.4153206120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.335730417 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 7739661987 ps |
| CPU time | 44.52 seconds |
| Started | Oct 03 06:34:54 AM UTC 24 |
| Finished | Oct 03 06:35:40 AM UTC 24 |
| Peak memory | 256080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335730417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.335730417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.1059127481 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2467082461 ps |
| CPU time | 46.29 seconds |
| Started | Oct 03 06:34:54 AM UTC 24 |
| Finished | Oct 03 06:35:42 AM UTC 24 |
| Peak memory | 256080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059127481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1059127481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.2410945838 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 208686666 ps |
| CPU time | 4.83 seconds |
| Started | Oct 03 06:34:51 AM UTC 24 |
| Finished | Oct 03 06:34:57 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410945838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2410945838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.3652374101 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 25517656799 ps |
| CPU time | 83.56 seconds |
| Started | Oct 03 06:34:56 AM UTC 24 |
| Finished | Oct 03 06:36:21 AM UTC 24 |
| Peak memory | 268288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652374101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3652374101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.3923764598 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 508246106 ps |
| CPU time | 19.08 seconds |
| Started | Oct 03 06:34:56 AM UTC 24 |
| Finished | Oct 03 06:35:16 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923764598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3923764598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.3156533125 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 686916329 ps |
| CPU time | 19.32 seconds |
| Started | Oct 03 06:34:51 AM UTC 24 |
| Finished | Oct 03 06:35:12 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156533125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.3156533125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.2717065704 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1236239901 ps |
| CPU time | 29.82 seconds |
| Started | Oct 03 06:34:51 AM UTC 24 |
| Finished | Oct 03 06:35:22 AM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717065704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2717065704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.775677025 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 173958902 ps |
| CPU time | 7.08 seconds |
| Started | Oct 03 06:34:58 AM UTC 24 |
| Finished | Oct 03 06:35:06 AM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775677025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.775677025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.498027518 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1032287250 ps |
| CPU time | 9.38 seconds |
| Started | Oct 03 06:34:48 AM UTC 24 |
| Finished | Oct 03 06:34:58 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498027518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.498027518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.3798523739 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2925477687 ps |
| CPU time | 69.98 seconds |
| Started | Oct 03 06:34:58 AM UTC 24 |
| Finished | Oct 03 06:36:09 AM UTC 24 |
| Peak memory | 274440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798523739 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.3798523739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.3236646602 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3926415857 ps |
| CPU time | 74.59 seconds |
| Started | Oct 03 06:34:58 AM UTC 24 |
| Finished | Oct 03 06:36:14 AM UTC 24 |
| Peak memory | 258256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3236646602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.otp_ctrl_stress_all_with_rand_reset.3236646602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.181108749 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 13534692416 ps |
| CPU time | 73.38 seconds |
| Started | Oct 03 06:34:58 AM UTC 24 |
| Finished | Oct 03 06:36:13 AM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181108749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.181108749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.3419602807 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 121879108 ps |
| CPU time | 3.45 seconds |
| Started | Oct 03 06:43:23 AM UTC 24 |
| Finished | Oct 03 06:43:28 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419602807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3419602807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.2390091526 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 2691591145 ps |
| CPU time | 5.29 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390091526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.2390091526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.4049392185 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 230040715 ps |
| CPU time | 4.6 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049392185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.4049392185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3858896778 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 103663863 ps |
| CPU time | 3.24 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:32 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858896778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3858896778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.327067425 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 113191780 ps |
| CPU time | 4.07 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:33 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327067425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.327067425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.774212776 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 183724192 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:33 AM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774212776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.774212776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.3322226727 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 226039408 ps |
| CPU time | 4.15 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:33 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322226727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3322226727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.1996870933 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 173180172 ps |
| CPU time | 3.85 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:33 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996870933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1996870933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.2327901637 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 127081914 ps |
| CPU time | 4 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:33 AM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327901637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2327901637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3826713981 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 377961079 ps |
| CPU time | 4.16 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826713981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3826713981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.838380764 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 129788949 ps |
| CPU time | 3.11 seconds |
| Started | Oct 03 06:35:15 AM UTC 24 |
| Finished | Oct 03 06:35:19 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838380764 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.838380764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.3204703618 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 12272091295 ps |
| CPU time | 44.21 seconds |
| Started | Oct 03 06:35:11 AM UTC 24 |
| Finished | Oct 03 06:35:57 AM UTC 24 |
| Peak memory | 252088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204703618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3204703618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.2656423278 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 835930959 ps |
| CPU time | 29.43 seconds |
| Started | Oct 03 06:35:11 AM UTC 24 |
| Finished | Oct 03 06:35:42 AM UTC 24 |
| Peak memory | 258148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656423278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.2656423278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.2580490614 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1410865154 ps |
| CPU time | 15.95 seconds |
| Started | Oct 03 06:35:09 AM UTC 24 |
| Finished | Oct 03 06:35:26 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580490614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2580490614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.1146499194 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 348837118 ps |
| CPU time | 6.07 seconds |
| Started | Oct 03 06:35:02 AM UTC 24 |
| Finished | Oct 03 06:35:09 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146499194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1146499194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.2281105864 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 5584293634 ps |
| CPU time | 55.58 seconds |
| Started | Oct 03 06:35:11 AM UTC 24 |
| Finished | Oct 03 06:36:09 AM UTC 24 |
| Peak memory | 268440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281105864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2281105864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.2568086047 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1040676934 ps |
| CPU time | 26.52 seconds |
| Started | Oct 03 06:35:11 AM UTC 24 |
| Finished | Oct 03 06:35:39 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568086047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.2568086047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.1250712575 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1059751928 ps |
| CPU time | 33.88 seconds |
| Started | Oct 03 06:35:09 AM UTC 24 |
| Finished | Oct 03 06:35:44 AM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250712575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1250712575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.3128442136 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 600972947 ps |
| CPU time | 11.03 seconds |
| Started | Oct 03 06:35:00 AM UTC 24 |
| Finished | Oct 03 06:35:12 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128442136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3128442136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.2437723176 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 59118690633 ps |
| CPU time | 441.88 seconds |
| Started | Oct 03 06:35:15 AM UTC 24 |
| Finished | Oct 03 06:42:43 AM UTC 24 |
| Peak memory | 303188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437723176 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.2437723176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.2906503925 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2638535381 ps |
| CPU time | 16.46 seconds |
| Started | Oct 03 06:35:13 AM UTC 24 |
| Finished | Oct 03 06:35:31 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906503925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.2906503925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.3363393330 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 2219107870 ps |
| CPU time | 5.82 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:35 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363393330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3363393330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.3220961601 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 212189711 ps |
| CPU time | 4.76 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220961601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3220961601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.1713327428 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 316302068 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 06:43:28 AM UTC 24 |
| Finished | Oct 03 06:43:33 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713327428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1713327428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.3471096762 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 133555287 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:33 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471096762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3471096762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.424660733 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 402187951 ps |
| CPU time | 4.59 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424660733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.424660733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.1233836259 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 1315218113 ps |
| CPU time | 4.53 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233836259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1233836259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2051654017 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 2332617972 ps |
| CPU time | 5.46 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:35 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051654017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2051654017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.3243917640 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 86835372 ps |
| CPU time | 3.97 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243917640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.3243917640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.2945154494 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 555165805 ps |
| CPU time | 5 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:35 AM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945154494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2945154494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3853113059 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 115642600 ps |
| CPU time | 3.31 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:33 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853113059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3853113059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.1836184565 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 223002360 ps |
| CPU time | 3.11 seconds |
| Started | Oct 03 06:35:33 AM UTC 24 |
| Finished | Oct 03 06:35:37 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836184565 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1836184565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.2475839651 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 473412838 ps |
| CPU time | 8.88 seconds |
| Started | Oct 03 06:35:27 AM UTC 24 |
| Finished | Oct 03 06:35:37 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475839651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.2475839651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.689211035 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 4610714906 ps |
| CPU time | 27.99 seconds |
| Started | Oct 03 06:35:24 AM UTC 24 |
| Finished | Oct 03 06:35:53 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689211035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.689211035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.2187522213 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 5829616625 ps |
| CPU time | 17.61 seconds |
| Started | Oct 03 06:35:22 AM UTC 24 |
| Finished | Oct 03 06:35:41 AM UTC 24 |
| Peak memory | 254164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187522213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2187522213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.2708553214 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 808875866 ps |
| CPU time | 19.75 seconds |
| Started | Oct 03 06:35:27 AM UTC 24 |
| Finished | Oct 03 06:35:48 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708553214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2708553214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.3457870667 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1797379891 ps |
| CPU time | 54.14 seconds |
| Started | Oct 03 06:35:27 AM UTC 24 |
| Finished | Oct 03 06:36:23 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457870667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3457870667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.2802608745 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1010563884 ps |
| CPU time | 8.9 seconds |
| Started | Oct 03 06:35:22 AM UTC 24 |
| Finished | Oct 03 06:35:32 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802608745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.2802608745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.244788566 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 451727635 ps |
| CPU time | 12.07 seconds |
| Started | Oct 03 06:35:20 AM UTC 24 |
| Finished | Oct 03 06:35:33 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244788566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.244788566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.3505462536 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 347651459 ps |
| CPU time | 5.25 seconds |
| Started | Oct 03 06:35:28 AM UTC 24 |
| Finished | Oct 03 06:35:34 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505462536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3505462536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.386782150 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 574025676 ps |
| CPU time | 17.74 seconds |
| Started | Oct 03 06:35:17 AM UTC 24 |
| Finished | Oct 03 06:35:36 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386782150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.386782150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.2037041750 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 54908438683 ps |
| CPU time | 186.17 seconds |
| Started | Oct 03 06:35:32 AM UTC 24 |
| Finished | Oct 03 06:38:42 AM UTC 24 |
| Peak memory | 268280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037041750 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.2037041750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.4200482607 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2209303739 ps |
| CPU time | 30.7 seconds |
| Started | Oct 03 06:35:29 AM UTC 24 |
| Finished | Oct 03 06:36:01 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200482607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.4200482607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.486560115 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 264217056 ps |
| CPU time | 5.13 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:35 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486560115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.486560115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2126154960 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 165253667 ps |
| CPU time | 4.36 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126154960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2126154960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.3759789788 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 137315705 ps |
| CPU time | 4.52 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759789788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.3759789788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.3857138314 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 100609075 ps |
| CPU time | 4 seconds |
| Started | Oct 03 06:43:29 AM UTC 24 |
| Finished | Oct 03 06:43:34 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857138314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3857138314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.3998553338 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 101958504 ps |
| CPU time | 3.82 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998553338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3998553338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.1262264851 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 470937363 ps |
| CPU time | 4.15 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262264851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1262264851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.2906217627 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 356532824 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906217627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2906217627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3768880419 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 125858753 ps |
| CPU time | 3.64 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768880419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3768880419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.1788105661 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 1905851844 ps |
| CPU time | 7 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788105661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.1788105661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.925093372 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 198237800 ps |
| CPU time | 4.38 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925093372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.925093372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.2834373567 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 77321752 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 06:35:42 AM UTC 24 |
| Finished | Oct 03 06:35:45 AM UTC 24 |
| Peak memory | 250520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834373567 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2834373567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.1764050798 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 408874466 ps |
| CPU time | 15.25 seconds |
| Started | Oct 03 06:35:42 AM UTC 24 |
| Finished | Oct 03 06:35:58 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764050798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.1764050798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.3033177354 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1700714405 ps |
| CPU time | 48.17 seconds |
| Started | Oct 03 06:35:37 AM UTC 24 |
| Finished | Oct 03 06:36:26 AM UTC 24 |
| Peak memory | 254044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033177354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.3033177354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.2405816726 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 5600773463 ps |
| CPU time | 13.8 seconds |
| Started | Oct 03 06:35:37 AM UTC 24 |
| Finished | Oct 03 06:35:52 AM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405816726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.2405816726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.3712557633 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 238513151 ps |
| CPU time | 6.08 seconds |
| Started | Oct 03 06:35:34 AM UTC 24 |
| Finished | Oct 03 06:35:41 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712557633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3712557633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.2387927438 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 490340457 ps |
| CPU time | 16.34 seconds |
| Started | Oct 03 06:35:42 AM UTC 24 |
| Finished | Oct 03 06:35:59 AM UTC 24 |
| Peak memory | 254168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387927438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.2387927438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.1894750975 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 372664170 ps |
| CPU time | 10.9 seconds |
| Started | Oct 03 06:35:42 AM UTC 24 |
| Finished | Oct 03 06:35:54 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894750975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1894750975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.1984965667 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 456592188 ps |
| CPU time | 8.55 seconds |
| Started | Oct 03 06:35:37 AM UTC 24 |
| Finished | Oct 03 06:35:46 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984965667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.1984965667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.2186493707 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 4420434875 ps |
| CPU time | 10.36 seconds |
| Started | Oct 03 06:35:34 AM UTC 24 |
| Finished | Oct 03 06:35:46 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186493707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2186493707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.2912896020 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 466930533 ps |
| CPU time | 7.42 seconds |
| Started | Oct 03 06:35:42 AM UTC 24 |
| Finished | Oct 03 06:35:51 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912896020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2912896020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.3500785011 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 591398337 ps |
| CPU time | 14.48 seconds |
| Started | Oct 03 06:35:34 AM UTC 24 |
| Finished | Oct 03 06:35:50 AM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500785011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3500785011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.1956426892 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 52952166518 ps |
| CPU time | 162.63 seconds |
| Started | Oct 03 06:35:42 AM UTC 24 |
| Finished | Oct 03 06:38:28 AM UTC 24 |
| Peak memory | 268300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956426892 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.1956426892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.1566384903 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2989296495 ps |
| CPU time | 31.39 seconds |
| Started | Oct 03 06:35:42 AM UTC 24 |
| Finished | Oct 03 06:36:15 AM UTC 24 |
| Peak memory | 253888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566384903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1566384903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.2749017402 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 166855786 ps |
| CPU time | 3.33 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:35 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749017402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2749017402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.3918065791 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 511336018 ps |
| CPU time | 5.11 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:37 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918065791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3918065791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.2616614238 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 281369856 ps |
| CPU time | 3.73 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616614238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.2616614238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.1833499010 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 148772322 ps |
| CPU time | 3.4 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833499010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.1833499010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.817314449 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 321479677 ps |
| CPU time | 4.51 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:37 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817314449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.817314449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.1367094630 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 151282126 ps |
| CPU time | 4.08 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 252008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367094630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1367094630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.3368519279 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 124293263 ps |
| CPU time | 3.84 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:36 AM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368519279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.3368519279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.828539130 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 335093279 ps |
| CPU time | 4.4 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:37 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828539130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.828539130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.2353426672 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 357028565 ps |
| CPU time | 4.41 seconds |
| Started | Oct 03 06:43:31 AM UTC 24 |
| Finished | Oct 03 06:43:37 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353426672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.2353426672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.1856953260 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 586834508 ps |
| CPU time | 4.5 seconds |
| Started | Oct 03 06:43:34 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856953260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1856953260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2557473986 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 818435801 ps |
| CPU time | 2.81 seconds |
| Started | Oct 03 06:35:55 AM UTC 24 |
| Finished | Oct 03 06:35:59 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557473986 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2557473986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.3956816730 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 488211423 ps |
| CPU time | 5.86 seconds |
| Started | Oct 03 06:35:49 AM UTC 24 |
| Finished | Oct 03 06:35:56 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956816730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3956816730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.562706529 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3017912903 ps |
| CPU time | 26.33 seconds |
| Started | Oct 03 06:35:48 AM UTC 24 |
| Finished | Oct 03 06:36:15 AM UTC 24 |
| Peak memory | 252148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562706529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.562706529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.2151647794 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 416526689 ps |
| CPU time | 5.48 seconds |
| Started | Oct 03 06:35:47 AM UTC 24 |
| Finished | Oct 03 06:35:53 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151647794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2151647794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.3491642251 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2549658668 ps |
| CPU time | 6.44 seconds |
| Started | Oct 03 06:35:45 AM UTC 24 |
| Finished | Oct 03 06:35:52 AM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491642251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3491642251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.107725498 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3670414789 ps |
| CPU time | 30.2 seconds |
| Started | Oct 03 06:35:51 AM UTC 24 |
| Finished | Oct 03 06:36:22 AM UTC 24 |
| Peak memory | 256024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107725498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.107725498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.1766369003 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 6553253660 ps |
| CPU time | 20.77 seconds |
| Started | Oct 03 06:35:52 AM UTC 24 |
| Finished | Oct 03 06:36:14 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766369003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1766369003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.3941978298 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2914870095 ps |
| CPU time | 29.68 seconds |
| Started | Oct 03 06:35:47 AM UTC 24 |
| Finished | Oct 03 06:36:18 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941978298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.3941978298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.2731087033 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 4939441030 ps |
| CPU time | 14.99 seconds |
| Started | Oct 03 06:35:47 AM UTC 24 |
| Finished | Oct 03 06:36:03 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731087033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2731087033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.844823611 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 509043475 ps |
| CPU time | 8.89 seconds |
| Started | Oct 03 06:35:53 AM UTC 24 |
| Finished | Oct 03 06:36:03 AM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844823611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.844823611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.519076006 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 6945759355 ps |
| CPU time | 16.06 seconds |
| Started | Oct 03 06:35:45 AM UTC 24 |
| Finished | Oct 03 06:36:02 AM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519076006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.519076006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.3800007509 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2046162013 ps |
| CPU time | 18.1 seconds |
| Started | Oct 03 06:35:55 AM UTC 24 |
| Finished | Oct 03 06:36:14 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800007509 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.3800007509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.533467619 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 27941099900 ps |
| CPU time | 153.69 seconds |
| Started | Oct 03 06:35:55 AM UTC 24 |
| Finished | Oct 03 06:38:31 AM UTC 24 |
| Peak memory | 268432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=533467619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.533467619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.1810829068 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 46698076334 ps |
| CPU time | 37.24 seconds |
| Started | Oct 03 06:35:53 AM UTC 24 |
| Finished | Oct 03 06:36:32 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810829068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.1810829068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.3293903610 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 259263230 ps |
| CPU time | 4.39 seconds |
| Started | Oct 03 06:43:34 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293903610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.3293903610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.2778097365 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 108274168 ps |
| CPU time | 3.48 seconds |
| Started | Oct 03 06:43:34 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778097365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2778097365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.1236933745 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 124385553 ps |
| CPU time | 3.98 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236933745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.1236933745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.2364201227 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 1791720031 ps |
| CPU time | 4.37 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364201227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2364201227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.972618086 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 114884865 ps |
| CPU time | 3.93 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972618086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.972618086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.3649698973 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 143214799 ps |
| CPU time | 3.87 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649698973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3649698973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.317189554 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 384779165 ps |
| CPU time | 4.01 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317189554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.317189554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.760668965 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 492546182 ps |
| CPU time | 3.35 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760668965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.760668965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.352456779 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 168898118 ps |
| CPU time | 2.83 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352456779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.352456779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.1460816707 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 219907702 ps |
| CPU time | 3.5 seconds |
| Started | Oct 03 06:36:06 AM UTC 24 |
| Finished | Oct 03 06:36:11 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460816707 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1460816707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.2392375511 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1888719784 ps |
| CPU time | 22.44 seconds |
| Started | Oct 03 06:36:03 AM UTC 24 |
| Finished | Oct 03 06:36:27 AM UTC 24 |
| Peak memory | 253848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392375511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.2392375511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.3003486687 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 296293143 ps |
| CPU time | 15.11 seconds |
| Started | Oct 03 06:36:03 AM UTC 24 |
| Finished | Oct 03 06:36:20 AM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003486687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3003486687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.3051645361 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 179126267 ps |
| CPU time | 6.22 seconds |
| Started | Oct 03 06:36:03 AM UTC 24 |
| Finished | Oct 03 06:36:11 AM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051645361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3051645361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.4179529060 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 236100758 ps |
| CPU time | 6.24 seconds |
| Started | Oct 03 06:35:58 AM UTC 24 |
| Finished | Oct 03 06:36:05 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179529060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.4179529060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.3199257094 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2465778455 ps |
| CPU time | 37.49 seconds |
| Started | Oct 03 06:36:03 AM UTC 24 |
| Finished | Oct 03 06:36:43 AM UTC 24 |
| Peak memory | 256280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199257094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.3199257094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.2048101765 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 595290694 ps |
| CPU time | 27.16 seconds |
| Started | Oct 03 06:36:03 AM UTC 24 |
| Finished | Oct 03 06:36:32 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048101765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2048101765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.1743902996 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 683222663 ps |
| CPU time | 17.15 seconds |
| Started | Oct 03 06:36:03 AM UTC 24 |
| Finished | Oct 03 06:36:22 AM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743902996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.1743902996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.1704271101 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 8183054968 ps |
| CPU time | 16.94 seconds |
| Started | Oct 03 06:35:58 AM UTC 24 |
| Finished | Oct 03 06:36:16 AM UTC 24 |
| Peak memory | 252092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704271101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.1704271101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.3509984139 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 401238718 ps |
| CPU time | 5.35 seconds |
| Started | Oct 03 06:36:04 AM UTC 24 |
| Finished | Oct 03 06:36:10 AM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509984139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.3509984139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.720385893 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 157819757 ps |
| CPU time | 5.19 seconds |
| Started | Oct 03 06:35:58 AM UTC 24 |
| Finished | Oct 03 06:36:04 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720385893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.720385893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.3358313192 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 910739631 ps |
| CPU time | 33.62 seconds |
| Started | Oct 03 06:36:06 AM UTC 24 |
| Finished | Oct 03 06:36:41 AM UTC 24 |
| Peak memory | 258096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3358313192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.otp_ctrl_stress_all_with_rand_reset.3358313192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.1321431360 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 11104738401 ps |
| CPU time | 33.66 seconds |
| Started | Oct 03 06:36:06 AM UTC 24 |
| Finished | Oct 03 06:36:41 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321431360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1321431360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.4116525991 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 103732615 ps |
| CPU time | 2.88 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116525991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.4116525991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3284802234 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 248636836 ps |
| CPU time | 3.54 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284802234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3284802234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.4005441778 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 358701399 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005441778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.4005441778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.499620455 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 130504870 ps |
| CPU time | 3.58 seconds |
| Started | Oct 03 06:43:35 AM UTC 24 |
| Finished | Oct 03 06:43:40 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499620455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.499620455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.3306194338 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 444844662 ps |
| CPU time | 4.2 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306194338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.3306194338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.1714771756 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 311271535 ps |
| CPU time | 4.48 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:44 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714771756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1714771756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.1588503692 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 174559470 ps |
| CPU time | 4.66 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:44 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588503692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1588503692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.4050232019 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 111736937 ps |
| CPU time | 3.67 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050232019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.4050232019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.3957070444 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 387127619 ps |
| CPU time | 4.32 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:44 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957070444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3957070444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.4117427436 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 393505061 ps |
| CPU time | 3.88 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117427436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.4117427436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.2194829328 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 55356275 ps |
| CPU time | 2.7 seconds |
| Started | Oct 03 06:36:20 AM UTC 24 |
| Finished | Oct 03 06:36:23 AM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194829328 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.2194829328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.3858590644 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2281204113 ps |
| CPU time | 50.84 seconds |
| Started | Oct 03 06:36:15 AM UTC 24 |
| Finished | Oct 03 06:37:07 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858590644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3858590644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.4002612963 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1988614821 ps |
| CPU time | 24.97 seconds |
| Started | Oct 03 06:36:14 AM UTC 24 |
| Finished | Oct 03 06:36:41 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002612963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.4002612963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.1815598380 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 10361269482 ps |
| CPU time | 32 seconds |
| Started | Oct 03 06:36:12 AM UTC 24 |
| Finished | Oct 03 06:36:46 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815598380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.1815598380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.3416230681 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 113023807 ps |
| CPU time | 4.92 seconds |
| Started | Oct 03 06:36:12 AM UTC 24 |
| Finished | Oct 03 06:36:18 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416230681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3416230681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.2066926901 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 434657102 ps |
| CPU time | 12.51 seconds |
| Started | Oct 03 06:36:18 AM UTC 24 |
| Finished | Oct 03 06:36:31 AM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066926901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2066926901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2432280146 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 402221434 ps |
| CPU time | 14.08 seconds |
| Started | Oct 03 06:36:18 AM UTC 24 |
| Finished | Oct 03 06:36:33 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432280146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2432280146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.3359461959 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1073939829 ps |
| CPU time | 12.74 seconds |
| Started | Oct 03 06:36:12 AM UTC 24 |
| Finished | Oct 03 06:36:26 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359461959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3359461959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.2302592056 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 258389197 ps |
| CPU time | 4.76 seconds |
| Started | Oct 03 06:36:18 AM UTC 24 |
| Finished | Oct 03 06:36:24 AM UTC 24 |
| Peak memory | 251720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302592056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2302592056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.3294590625 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 841111230 ps |
| CPU time | 12.63 seconds |
| Started | Oct 03 06:36:10 AM UTC 24 |
| Finished | Oct 03 06:36:24 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294590625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3294590625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.4096095985 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 29942896830 ps |
| CPU time | 222.79 seconds |
| Started | Oct 03 06:36:20 AM UTC 24 |
| Finished | Oct 03 06:40:06 AM UTC 24 |
| Peak memory | 255824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096095985 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.4096095985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.4123638229 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 604356152 ps |
| CPU time | 17.97 seconds |
| Started | Oct 03 06:36:18 AM UTC 24 |
| Finished | Oct 03 06:36:37 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123638229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.4123638229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2525886520 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 138750090 ps |
| CPU time | 3.79 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525886520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2525886520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.3514550557 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 275422432 ps |
| CPU time | 2.8 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:42 AM UTC 24 |
| Peak memory | 251208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514550557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3514550557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2357907283 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 122147264 ps |
| CPU time | 3.07 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357907283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2357907283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.562415322 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 617234072 ps |
| CPU time | 3.91 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562415322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.562415322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.4210376299 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 397584641 ps |
| CPU time | 3.96 seconds |
| Started | Oct 03 06:43:38 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210376299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.4210376299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.1524300212 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 119634012 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524300212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1524300212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.2738889042 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 1827978667 ps |
| CPU time | 4.48 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:44 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738889042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.2738889042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.1409551583 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 1952103840 ps |
| CPU time | 5.6 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:45 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409551583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1409551583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.1005869174 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 527433945 ps |
| CPU time | 3.73 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005869174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.1005869174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2630458906 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2602245579 ps |
| CPU time | 5.17 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:45 AM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630458906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2630458906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.3389935881 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 63993899 ps |
| CPU time | 2.79 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:36:32 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389935881 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3389935881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.3793861542 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 340620568 ps |
| CPU time | 9.88 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:36:39 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793861542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3793861542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.2285575183 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 3938672107 ps |
| CPU time | 38.42 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:37:07 AM UTC 24 |
| Peak memory | 258088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285575183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.2285575183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.3878938997 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 155375927 ps |
| CPU time | 4.76 seconds |
| Started | Oct 03 06:36:24 AM UTC 24 |
| Finished | Oct 03 06:36:30 AM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878938997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3878938997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.994235060 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 459637700 ps |
| CPU time | 3.74 seconds |
| Started | Oct 03 06:36:21 AM UTC 24 |
| Finished | Oct 03 06:36:26 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994235060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.994235060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.3460705442 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 9968736391 ps |
| CPU time | 20.06 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:36:49 AM UTC 24 |
| Peak memory | 255980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460705442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3460705442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.1760662625 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1992241008 ps |
| CPU time | 23.37 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:36:52 AM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760662625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1760662625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.498122066 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 88513604 ps |
| CPU time | 3.92 seconds |
| Started | Oct 03 06:36:24 AM UTC 24 |
| Finished | Oct 03 06:36:29 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498122066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.498122066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.1778130485 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1912445327 ps |
| CPU time | 20.41 seconds |
| Started | Oct 03 06:36:24 AM UTC 24 |
| Finished | Oct 03 06:36:46 AM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778130485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1778130485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.1661055115 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 179696344 ps |
| CPU time | 7.24 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:36:36 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661055115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1661055115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.2335702526 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 165640967 ps |
| CPU time | 5.67 seconds |
| Started | Oct 03 06:36:20 AM UTC 24 |
| Finished | Oct 03 06:36:27 AM UTC 24 |
| Peak memory | 251596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335702526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2335702526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.1629223322 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 26351573914 ps |
| CPU time | 192.54 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:39:44 AM UTC 24 |
| Peak memory | 290968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629223322 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.1629223322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.3660111115 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1865195680 ps |
| CPU time | 24.9 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:36:54 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660111115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.3660111115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.644791512 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 276088014 ps |
| CPU time | 4.02 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:44 AM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644791512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.644791512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.3108006795 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 556745668 ps |
| CPU time | 4.86 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:45 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108006795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3108006795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.4058209302 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 304286013 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058209302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.4058209302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3244971493 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 428921017 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244971493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3244971493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.1179939441 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 274086826 ps |
| CPU time | 3.33 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179939441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1179939441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.3385639600 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 161795180 ps |
| CPU time | 3.62 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:44 AM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385639600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3385639600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.2107899267 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 258503185 ps |
| CPU time | 3.26 seconds |
| Started | Oct 03 06:43:39 AM UTC 24 |
| Finished | Oct 03 06:43:43 AM UTC 24 |
| Peak memory | 251816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107899267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2107899267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.3649901789 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 105525180 ps |
| CPU time | 3.43 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:52 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649901789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3649901789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.250638520 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 362075865 ps |
| CPU time | 3.49 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:52 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250638520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.250638520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.394813461 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2419570261 ps |
| CPU time | 6.82 seconds |
| Started | Oct 03 06:43:47 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394813461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.394813461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.1559038842 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 96844399 ps |
| CPU time | 3.1 seconds |
| Started | Oct 03 06:30:05 AM UTC 24 |
| Finished | Oct 03 06:30:09 AM UTC 24 |
| Peak memory | 251656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559038842 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1559038842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.2344309429 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2091776406 ps |
| CPU time | 22.65 seconds |
| Started | Oct 03 06:29:50 AM UTC 24 |
| Finished | Oct 03 06:30:14 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344309429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.2344309429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.924673182 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 823555031 ps |
| CPU time | 30.45 seconds |
| Started | Oct 03 06:29:54 AM UTC 24 |
| Finished | Oct 03 06:30:26 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924673182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.924673182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.665890343 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3770331833 ps |
| CPU time | 43.44 seconds |
| Started | Oct 03 06:29:52 AM UTC 24 |
| Finished | Oct 03 06:30:37 AM UTC 24 |
| Peak memory | 252128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665890343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.665890343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.4078373419 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 207379633 ps |
| CPU time | 5.78 seconds |
| Started | Oct 03 06:29:50 AM UTC 24 |
| Finished | Oct 03 06:29:57 AM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078373419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.4078373419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.172938415 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 778942319 ps |
| CPU time | 25.04 seconds |
| Started | Oct 03 06:29:57 AM UTC 24 |
| Finished | Oct 03 06:30:23 AM UTC 24 |
| Peak memory | 256088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172938415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.172938415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.3931263914 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4680580608 ps |
| CPU time | 23.91 seconds |
| Started | Oct 03 06:29:59 AM UTC 24 |
| Finished | Oct 03 06:30:24 AM UTC 24 |
| Peak memory | 253984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931263914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.3931263914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.3020184928 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1083812906 ps |
| CPU time | 10.89 seconds |
| Started | Oct 03 06:29:52 AM UTC 24 |
| Finished | Oct 03 06:30:04 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020184928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3020184928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.3964081283 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 482007005 ps |
| CPU time | 17.65 seconds |
| Started | Oct 03 06:29:52 AM UTC 24 |
| Finished | Oct 03 06:30:11 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964081283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.3964081283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.3543243293 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 501007179 ps |
| CPU time | 12.96 seconds |
| Started | Oct 03 06:29:59 AM UTC 24 |
| Finished | Oct 03 06:30:13 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543243293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3543243293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.1529913790 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 154707814161 ps |
| CPU time | 321.61 seconds |
| Started | Oct 03 06:30:05 AM UTC 24 |
| Finished | Oct 03 06:35:31 AM UTC 24 |
| Peak memory | 290412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529913790 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1529913790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.1762145402 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 314530501 ps |
| CPU time | 7.6 seconds |
| Started | Oct 03 06:29:50 AM UTC 24 |
| Finished | Oct 03 06:29:59 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762145402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1762145402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.1907995765 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2094626072 ps |
| CPU time | 60.89 seconds |
| Started | Oct 03 06:30:00 AM UTC 24 |
| Finished | Oct 03 06:31:02 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907995765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1907995765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.3785511993 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 814776695 ps |
| CPU time | 4 seconds |
| Started | Oct 03 06:36:38 AM UTC 24 |
| Finished | Oct 03 06:36:43 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785511993 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3785511993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.1089917880 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 907376529 ps |
| CPU time | 10.04 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:36:48 AM UTC 24 |
| Peak memory | 252116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089917880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1089917880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.1349361084 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2295190964 ps |
| CPU time | 37.7 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:37:16 AM UTC 24 |
| Peak memory | 258144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349361084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.1349361084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.35146453 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1912402155 ps |
| CPU time | 20.03 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:36:58 AM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35146453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.35146453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.2725944027 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 581540904 ps |
| CPU time | 4.62 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:36:34 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725944027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.2725944027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.543507363 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2174350005 ps |
| CPU time | 23.28 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:37:02 AM UTC 24 |
| Peak memory | 254240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543507363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.543507363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.1843800950 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1291453937 ps |
| CPU time | 18.5 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:36:57 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843800950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1843800950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.3426465974 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 951353883 ps |
| CPU time | 8.76 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:36:47 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426465974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3426465974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.1467667482 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3106091928 ps |
| CPU time | 22.67 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:37:01 AM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467667482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1467667482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.167178184 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 292014878 ps |
| CPU time | 14.66 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:36:53 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167178184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.167178184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.108374528 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 161736788 ps |
| CPU time | 6.19 seconds |
| Started | Oct 03 06:36:28 AM UTC 24 |
| Finished | Oct 03 06:36:35 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108374528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.108374528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.1720074136 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 36818936765 ps |
| CPU time | 47.95 seconds |
| Started | Oct 03 06:36:38 AM UTC 24 |
| Finished | Oct 03 06:37:27 AM UTC 24 |
| Peak memory | 256204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720074136 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.1720074136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.2383638982 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 6401414500 ps |
| CPU time | 117.13 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:38:37 AM UTC 24 |
| Peak memory | 258328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2383638982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.otp_ctrl_stress_all_with_rand_reset.2383638982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.1007818590 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2201638041 ps |
| CPU time | 23.55 seconds |
| Started | Oct 03 06:36:37 AM UTC 24 |
| Finished | Oct 03 06:37:02 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007818590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1007818590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.304370772 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 91563402 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 06:36:50 AM UTC 24 |
| Finished | Oct 03 06:36:53 AM UTC 24 |
| Peak memory | 250580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304370772 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.304370772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.3510454471 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 440907076 ps |
| CPU time | 10.07 seconds |
| Started | Oct 03 06:36:44 AM UTC 24 |
| Finished | Oct 03 06:36:55 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510454471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3510454471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.1266018038 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 3429163193 ps |
| CPU time | 24.56 seconds |
| Started | Oct 03 06:36:44 AM UTC 24 |
| Finished | Oct 03 06:37:10 AM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266018038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1266018038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.223099358 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3155785836 ps |
| CPU time | 36.13 seconds |
| Started | Oct 03 06:36:44 AM UTC 24 |
| Finished | Oct 03 06:37:21 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223099358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.223099358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.3580233856 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1893350097 ps |
| CPU time | 11.96 seconds |
| Started | Oct 03 06:36:39 AM UTC 24 |
| Finished | Oct 03 06:36:52 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580233856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.3580233856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.502388282 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 436404199 ps |
| CPU time | 5.46 seconds |
| Started | Oct 03 06:36:46 AM UTC 24 |
| Finished | Oct 03 06:36:52 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502388282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.502388282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.1136410819 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 459618133 ps |
| CPU time | 6.44 seconds |
| Started | Oct 03 06:36:46 AM UTC 24 |
| Finished | Oct 03 06:36:53 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136410819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.1136410819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.1314919241 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 794018770 ps |
| CPU time | 8.55 seconds |
| Started | Oct 03 06:36:42 AM UTC 24 |
| Finished | Oct 03 06:36:51 AM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314919241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1314919241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.478821211 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1361715337 ps |
| CPU time | 17.11 seconds |
| Started | Oct 03 06:36:39 AM UTC 24 |
| Finished | Oct 03 06:36:58 AM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478821211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.478821211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.2064450135 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 416245442 ps |
| CPU time | 9.32 seconds |
| Started | Oct 03 06:36:47 AM UTC 24 |
| Finished | Oct 03 06:36:58 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064450135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2064450135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.3847720532 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 313617104 ps |
| CPU time | 6.42 seconds |
| Started | Oct 03 06:36:38 AM UTC 24 |
| Finished | Oct 03 06:36:45 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847720532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3847720532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.1060629572 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 481874966 ps |
| CPU time | 7.55 seconds |
| Started | Oct 03 06:36:50 AM UTC 24 |
| Finished | Oct 03 06:36:58 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060629572 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.1060629572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.831065402 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 50671469561 ps |
| CPU time | 150.16 seconds |
| Started | Oct 03 06:36:48 AM UTC 24 |
| Finished | Oct 03 06:39:20 AM UTC 24 |
| Peak memory | 268564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=831065402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.831065402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.632767888 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 209467055 ps |
| CPU time | 5.88 seconds |
| Started | Oct 03 06:36:47 AM UTC 24 |
| Finished | Oct 03 06:36:54 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632767888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.632767888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.1138995062 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 143224740 ps |
| CPU time | 3.21 seconds |
| Started | Oct 03 06:36:58 AM UTC 24 |
| Finished | Oct 03 06:37:02 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138995062 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1138995062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.2467856264 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 422029766 ps |
| CPU time | 8.7 seconds |
| Started | Oct 03 06:36:55 AM UTC 24 |
| Finished | Oct 03 06:37:04 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467856264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2467856264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.461820444 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1134673407 ps |
| CPU time | 15.13 seconds |
| Started | Oct 03 06:36:55 AM UTC 24 |
| Finished | Oct 03 06:37:11 AM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461820444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.461820444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.3383822560 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2274318916 ps |
| CPU time | 35.22 seconds |
| Started | Oct 03 06:36:54 AM UTC 24 |
| Finished | Oct 03 06:37:31 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383822560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.3383822560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.1698215559 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 122729918 ps |
| CPU time | 5.57 seconds |
| Started | Oct 03 06:36:54 AM UTC 24 |
| Finished | Oct 03 06:37:01 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698215559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1698215559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.2591704022 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2781308914 ps |
| CPU time | 32.35 seconds |
| Started | Oct 03 06:36:55 AM UTC 24 |
| Finished | Oct 03 06:37:28 AM UTC 24 |
| Peak memory | 256224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591704022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2591704022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.1947325257 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1310953568 ps |
| CPU time | 37.12 seconds |
| Started | Oct 03 06:36:55 AM UTC 24 |
| Finished | Oct 03 06:37:33 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947325257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.1947325257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.4153428682 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1357477031 ps |
| CPU time | 16.44 seconds |
| Started | Oct 03 06:36:54 AM UTC 24 |
| Finished | Oct 03 06:37:12 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153428682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.4153428682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.3436014273 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 698693686 ps |
| CPU time | 18.9 seconds |
| Started | Oct 03 06:36:54 AM UTC 24 |
| Finished | Oct 03 06:37:14 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436014273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3436014273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.1988160644 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3438221593 ps |
| CPU time | 11.89 seconds |
| Started | Oct 03 06:36:57 AM UTC 24 |
| Finished | Oct 03 06:37:10 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988160644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1988160644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.254752086 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 296040459 ps |
| CPU time | 10.7 seconds |
| Started | Oct 03 06:36:50 AM UTC 24 |
| Finished | Oct 03 06:37:02 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254752086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.254752086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.1822681409 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 11515291250 ps |
| CPU time | 246.61 seconds |
| Started | Oct 03 06:36:58 AM UTC 24 |
| Finished | Oct 03 06:41:09 AM UTC 24 |
| Peak memory | 307268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822681409 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.1822681409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.3503483311 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 7950354631 ps |
| CPU time | 93.79 seconds |
| Started | Oct 03 06:36:57 AM UTC 24 |
| Finished | Oct 03 06:38:33 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503483311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3503483311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.456822688 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 126327075 ps |
| CPU time | 4.03 seconds |
| Started | Oct 03 06:37:10 AM UTC 24 |
| Finished | Oct 03 06:37:15 AM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456822688 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.456822688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.3294146848 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 4017999977 ps |
| CPU time | 11.73 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:16 AM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294146848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3294146848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.2886673517 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 352917093 ps |
| CPU time | 19.86 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:24 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886673517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.2886673517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.1272317588 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 10597498234 ps |
| CPU time | 50.68 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:55 AM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272317588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.1272317588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.2921791216 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 309721839 ps |
| CPU time | 4.13 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:08 AM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921791216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2921791216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.2809855301 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 692394810 ps |
| CPU time | 27.61 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:32 AM UTC 24 |
| Peak memory | 253904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809855301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2809855301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.2412213511 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 303736193 ps |
| CPU time | 8.18 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:13 AM UTC 24 |
| Peak memory | 252032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412213511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2412213511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.2791644670 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1673897828 ps |
| CPU time | 4.79 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:09 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791644670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2791644670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.3445646494 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 441659049 ps |
| CPU time | 7.56 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:11 AM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445646494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.3445646494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.716596059 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 511082405 ps |
| CPU time | 13.39 seconds |
| Started | Oct 03 06:37:05 AM UTC 24 |
| Finished | Oct 03 06:37:19 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716596059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.716596059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.1966933424 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 5265528928 ps |
| CPU time | 34.51 seconds |
| Started | Oct 03 06:37:03 AM UTC 24 |
| Finished | Oct 03 06:37:39 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966933424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.1966933424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.1112458551 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 12629151922 ps |
| CPU time | 52.94 seconds |
| Started | Oct 03 06:37:10 AM UTC 24 |
| Finished | Oct 03 06:38:04 AM UTC 24 |
| Peak memory | 254096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112458551 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.1112458551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.2900021789 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1040913861 ps |
| CPU time | 25.71 seconds |
| Started | Oct 03 06:37:06 AM UTC 24 |
| Finished | Oct 03 06:37:33 AM UTC 24 |
| Peak memory | 251980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900021789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2900021789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.2904238140 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 63092008 ps |
| CPU time | 2.83 seconds |
| Started | Oct 03 06:37:21 AM UTC 24 |
| Finished | Oct 03 06:37:25 AM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904238140 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2904238140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.2665361188 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 3770133117 ps |
| CPU time | 41 seconds |
| Started | Oct 03 06:37:12 AM UTC 24 |
| Finished | Oct 03 06:37:54 AM UTC 24 |
| Peak memory | 258068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665361188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2665361188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.3808650353 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1735458401 ps |
| CPU time | 33.81 seconds |
| Started | Oct 03 06:37:12 AM UTC 24 |
| Finished | Oct 03 06:37:47 AM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808650353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3808650353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.3751200958 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1830806409 ps |
| CPU time | 8.69 seconds |
| Started | Oct 03 06:37:10 AM UTC 24 |
| Finished | Oct 03 06:37:20 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751200958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.3751200958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.2340584225 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1964889943 ps |
| CPU time | 9.58 seconds |
| Started | Oct 03 06:37:14 AM UTC 24 |
| Finished | Oct 03 06:37:24 AM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340584225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2340584225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.1321277754 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 745662708 ps |
| CPU time | 14.53 seconds |
| Started | Oct 03 06:37:16 AM UTC 24 |
| Finished | Oct 03 06:37:32 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321277754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1321277754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.638415832 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 11037767393 ps |
| CPU time | 36.9 seconds |
| Started | Oct 03 06:37:12 AM UTC 24 |
| Finished | Oct 03 06:37:50 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638415832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.638415832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.4099295744 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1111896595 ps |
| CPU time | 23.46 seconds |
| Started | Oct 03 06:37:12 AM UTC 24 |
| Finished | Oct 03 06:37:37 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099295744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.4099295744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.2546345384 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 149917826 ps |
| CPU time | 8.63 seconds |
| Started | Oct 03 06:37:16 AM UTC 24 |
| Finished | Oct 03 06:37:26 AM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546345384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2546345384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.3152930113 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2201686555 ps |
| CPU time | 9.19 seconds |
| Started | Oct 03 06:37:10 AM UTC 24 |
| Finished | Oct 03 06:37:20 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152930113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.3152930113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.3717016929 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 118181449006 ps |
| CPU time | 272.55 seconds |
| Started | Oct 03 06:37:21 AM UTC 24 |
| Finished | Oct 03 06:41:58 AM UTC 24 |
| Peak memory | 307348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717016929 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.3717016929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.2537664595 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 18796856419 ps |
| CPU time | 44.32 seconds |
| Started | Oct 03 06:37:18 AM UTC 24 |
| Finished | Oct 03 06:38:04 AM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537664595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.2537664595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.2944237958 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 937280702 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 06:37:33 AM UTC 24 |
| Finished | Oct 03 06:37:37 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944237958 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2944237958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.923638644 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 3495090485 ps |
| CPU time | 15.11 seconds |
| Started | Oct 03 06:37:27 AM UTC 24 |
| Finished | Oct 03 06:37:43 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923638644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.923638644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.654068819 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 265022406 ps |
| CPU time | 16.41 seconds |
| Started | Oct 03 06:37:27 AM UTC 24 |
| Finished | Oct 03 06:37:44 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654068819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.654068819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.3650754429 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 493167674 ps |
| CPU time | 12.75 seconds |
| Started | Oct 03 06:37:27 AM UTC 24 |
| Finished | Oct 03 06:37:41 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650754429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.3650754429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.722394456 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1984530059 ps |
| CPU time | 6.22 seconds |
| Started | Oct 03 06:37:21 AM UTC 24 |
| Finished | Oct 03 06:37:29 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722394456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.722394456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.848180707 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1471176581 ps |
| CPU time | 26.09 seconds |
| Started | Oct 03 06:37:27 AM UTC 24 |
| Finished | Oct 03 06:37:54 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848180707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.848180707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.1833152906 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3355933341 ps |
| CPU time | 37.7 seconds |
| Started | Oct 03 06:37:27 AM UTC 24 |
| Finished | Oct 03 06:38:06 AM UTC 24 |
| Peak memory | 254080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833152906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1833152906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.607782051 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 4028580965 ps |
| CPU time | 10.9 seconds |
| Started | Oct 03 06:37:26 AM UTC 24 |
| Finished | Oct 03 06:37:39 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607782051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.607782051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.234848251 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 868563960 ps |
| CPU time | 23.04 seconds |
| Started | Oct 03 06:37:23 AM UTC 24 |
| Finished | Oct 03 06:37:47 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234848251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.234848251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.997726055 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1834258104 ps |
| CPU time | 8.79 seconds |
| Started | Oct 03 06:37:32 AM UTC 24 |
| Finished | Oct 03 06:37:42 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997726055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.997726055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.3868734452 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 169841550 ps |
| CPU time | 8.24 seconds |
| Started | Oct 03 06:37:21 AM UTC 24 |
| Finished | Oct 03 06:37:31 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868734452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3868734452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.2688818636 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 4344938794 ps |
| CPU time | 39.01 seconds |
| Started | Oct 03 06:37:32 AM UTC 24 |
| Finished | Oct 03 06:38:13 AM UTC 24 |
| Peak memory | 254076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688818636 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.2688818636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.780902152 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1106901515 ps |
| CPU time | 10.54 seconds |
| Started | Oct 03 06:37:32 AM UTC 24 |
| Finished | Oct 03 06:37:44 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780902152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.780902152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.1255134225 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 162608040 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 06:37:41 AM UTC 24 |
| Finished | Oct 03 06:37:45 AM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255134225 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1255134225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.147308749 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 657517338 ps |
| CPU time | 8.02 seconds |
| Started | Oct 03 06:37:36 AM UTC 24 |
| Finished | Oct 03 06:37:46 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147308749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.147308749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.3515561673 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 819243657 ps |
| CPU time | 12.47 seconds |
| Started | Oct 03 06:37:36 AM UTC 24 |
| Finished | Oct 03 06:37:50 AM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515561673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3515561673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.526469417 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 884060815 ps |
| CPU time | 11.53 seconds |
| Started | Oct 03 06:37:36 AM UTC 24 |
| Finished | Oct 03 06:37:49 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526469417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.526469417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.3131823402 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 326769666 ps |
| CPU time | 5.01 seconds |
| Started | Oct 03 06:37:33 AM UTC 24 |
| Finished | Oct 03 06:37:39 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131823402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3131823402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.1001154755 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2296587027 ps |
| CPU time | 46.21 seconds |
| Started | Oct 03 06:37:38 AM UTC 24 |
| Finished | Oct 03 06:38:26 AM UTC 24 |
| Peak memory | 268380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001154755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1001154755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.467598764 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4904066351 ps |
| CPU time | 22.81 seconds |
| Started | Oct 03 06:37:38 AM UTC 24 |
| Finished | Oct 03 06:38:02 AM UTC 24 |
| Peak memory | 254020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467598764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.467598764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.120421568 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1003292089 ps |
| CPU time | 8.03 seconds |
| Started | Oct 03 06:37:36 AM UTC 24 |
| Finished | Oct 03 06:37:45 AM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120421568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.120421568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.1746632958 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 511779578 ps |
| CPU time | 15.91 seconds |
| Started | Oct 03 06:37:36 AM UTC 24 |
| Finished | Oct 03 06:37:53 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746632958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1746632958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.1504160759 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 446324427 ps |
| CPU time | 14.29 seconds |
| Started | Oct 03 06:37:33 AM UTC 24 |
| Finished | Oct 03 06:37:48 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504160759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.1504160759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.108595026 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 49594350286 ps |
| CPU time | 338.42 seconds |
| Started | Oct 03 06:37:40 AM UTC 24 |
| Finished | Oct 03 06:43:23 AM UTC 24 |
| Peak memory | 303108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108595026 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.108595026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.69652761 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 760467410 ps |
| CPU time | 9.11 seconds |
| Started | Oct 03 06:37:40 AM UTC 24 |
| Finished | Oct 03 06:37:50 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69652761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.69652761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.2014852467 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 170066065 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 06:37:51 AM UTC 24 |
| Finished | Oct 03 06:37:54 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014852467 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2014852467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.2698421902 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2530317578 ps |
| CPU time | 24.06 seconds |
| Started | Oct 03 06:37:47 AM UTC 24 |
| Finished | Oct 03 06:38:13 AM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698421902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.2698421902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.2938169047 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1777468592 ps |
| CPU time | 18.08 seconds |
| Started | Oct 03 06:37:47 AM UTC 24 |
| Finished | Oct 03 06:38:07 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938169047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2938169047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.1700161232 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1003734601 ps |
| CPU time | 14.32 seconds |
| Started | Oct 03 06:37:47 AM UTC 24 |
| Finished | Oct 03 06:38:03 AM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700161232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1700161232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.3510503621 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 151083465 ps |
| CPU time | 5.7 seconds |
| Started | Oct 03 06:37:45 AM UTC 24 |
| Finished | Oct 03 06:37:51 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510503621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3510503621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.3627047779 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4381096116 ps |
| CPU time | 48.07 seconds |
| Started | Oct 03 06:37:47 AM UTC 24 |
| Finished | Oct 03 06:38:37 AM UTC 24 |
| Peak memory | 258200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627047779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3627047779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.280009841 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 623456752 ps |
| CPU time | 6.38 seconds |
| Started | Oct 03 06:37:49 AM UTC 24 |
| Finished | Oct 03 06:37:57 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280009841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.280009841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.4277694111 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 174721935 ps |
| CPU time | 5.19 seconds |
| Started | Oct 03 06:37:47 AM UTC 24 |
| Finished | Oct 03 06:37:53 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277694111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.4277694111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.1501141679 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1077028256 ps |
| CPU time | 17.56 seconds |
| Started | Oct 03 06:37:47 AM UTC 24 |
| Finished | Oct 03 06:38:06 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501141679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.1501141679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.267647821 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 347808714 ps |
| CPU time | 8.95 seconds |
| Started | Oct 03 06:37:49 AM UTC 24 |
| Finished | Oct 03 06:38:00 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267647821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.267647821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.3181944145 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 185354905 ps |
| CPU time | 4.36 seconds |
| Started | Oct 03 06:37:43 AM UTC 24 |
| Finished | Oct 03 06:37:49 AM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181944145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.3181944145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.2947262543 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 171395908585 ps |
| CPU time | 1364.5 seconds |
| Started | Oct 03 06:37:51 AM UTC 24 |
| Finished | Oct 03 07:00:50 AM UTC 24 |
| Peak memory | 273324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947262543 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.2947262543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.2855587439 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 276776406 ps |
| CPU time | 8.4 seconds |
| Started | Oct 03 06:37:49 AM UTC 24 |
| Finished | Oct 03 06:37:59 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855587439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.2855587439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.1177223071 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 137086827 ps |
| CPU time | 3.09 seconds |
| Started | Oct 03 06:38:00 AM UTC 24 |
| Finished | Oct 03 06:38:05 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177223071 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1177223071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.1763553194 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 917450366 ps |
| CPU time | 10 seconds |
| Started | Oct 03 06:37:55 AM UTC 24 |
| Finished | Oct 03 06:38:06 AM UTC 24 |
| Peak memory | 252188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763553194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.1763553194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.1688069867 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3681399409 ps |
| CPU time | 29.48 seconds |
| Started | Oct 03 06:37:55 AM UTC 24 |
| Finished | Oct 03 06:38:25 AM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688069867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.1688069867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.1451621772 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 105729668 ps |
| CPU time | 6.23 seconds |
| Started | Oct 03 06:37:51 AM UTC 24 |
| Finished | Oct 03 06:37:58 AM UTC 24 |
| Peak memory | 252020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451621772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1451621772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.1306217404 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 396724842 ps |
| CPU time | 7.36 seconds |
| Started | Oct 03 06:37:57 AM UTC 24 |
| Finished | Oct 03 06:38:05 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306217404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1306217404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.1106249970 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1561614204 ps |
| CPU time | 44.93 seconds |
| Started | Oct 03 06:37:57 AM UTC 24 |
| Finished | Oct 03 06:38:43 AM UTC 24 |
| Peak memory | 251880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106249970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1106249970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.383941809 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 221779631 ps |
| CPU time | 6.87 seconds |
| Started | Oct 03 06:37:52 AM UTC 24 |
| Finished | Oct 03 06:38:00 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383941809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.383941809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.4240705498 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 608349829 ps |
| CPU time | 6.14 seconds |
| Started | Oct 03 06:37:52 AM UTC 24 |
| Finished | Oct 03 06:38:00 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240705498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.4240705498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.17093229 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 550570235 ps |
| CPU time | 9.62 seconds |
| Started | Oct 03 06:37:57 AM UTC 24 |
| Finished | Oct 03 06:38:08 AM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17093229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.17093229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.4016179701 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 811311635 ps |
| CPU time | 7.6 seconds |
| Started | Oct 03 06:37:51 AM UTC 24 |
| Finished | Oct 03 06:38:00 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016179701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.4016179701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.2771812478 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 36612481273 ps |
| CPU time | 284.31 seconds |
| Started | Oct 03 06:37:59 AM UTC 24 |
| Finished | Oct 03 06:42:48 AM UTC 24 |
| Peak memory | 258124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771812478 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.2771812478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.2697579715 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1680122249 ps |
| CPU time | 39.51 seconds |
| Started | Oct 03 06:37:59 AM UTC 24 |
| Finished | Oct 03 06:38:40 AM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697579715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.2697579715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.2759175412 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 130037708 ps |
| CPU time | 3 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:38:13 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759175412 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2759175412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.3239607384 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4650536833 ps |
| CPU time | 37.43 seconds |
| Started | Oct 03 06:38:05 AM UTC 24 |
| Finished | Oct 03 06:38:44 AM UTC 24 |
| Peak memory | 254032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239607384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3239607384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.236494675 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 714443002 ps |
| CPU time | 14.67 seconds |
| Started | Oct 03 06:38:04 AM UTC 24 |
| Finished | Oct 03 06:38:20 AM UTC 24 |
| Peak memory | 251972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236494675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.236494675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.1238537821 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3424071826 ps |
| CPU time | 29.01 seconds |
| Started | Oct 03 06:38:03 AM UTC 24 |
| Finished | Oct 03 06:38:34 AM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238537821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1238537821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.2170828888 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 333756891 ps |
| CPU time | 5.88 seconds |
| Started | Oct 03 06:38:01 AM UTC 24 |
| Finished | Oct 03 06:38:08 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170828888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2170828888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.2032574824 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1725466859 ps |
| CPU time | 44.44 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:38:55 AM UTC 24 |
| Peak memory | 258140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032574824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2032574824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.2146967655 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 1483085519 ps |
| CPU time | 34.93 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:38:45 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146967655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2146967655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.3478103055 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1633183799 ps |
| CPU time | 19.18 seconds |
| Started | Oct 03 06:38:02 AM UTC 24 |
| Finished | Oct 03 06:38:23 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478103055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3478103055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.2580552075 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 6180661409 ps |
| CPU time | 26.54 seconds |
| Started | Oct 03 06:38:01 AM UTC 24 |
| Finished | Oct 03 06:38:29 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580552075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2580552075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.509522301 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 600207485 ps |
| CPU time | 14.16 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:38:24 AM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509522301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.509522301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.3053305780 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 862110263 ps |
| CPU time | 8.69 seconds |
| Started | Oct 03 06:38:01 AM UTC 24 |
| Finished | Oct 03 06:38:10 AM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053305780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.3053305780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.865291918 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1580841160 ps |
| CPU time | 31.76 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:38:42 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865291918 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.865291918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.328050495 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2264573564 ps |
| CPU time | 22.36 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:38:32 AM UTC 24 |
| Peak memory | 252028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328050495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.328050495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.28791024 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 120269223 ps |
| CPU time | 2.89 seconds |
| Started | Oct 03 06:30:25 AM UTC 24 |
| Finished | Oct 03 06:30:29 AM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28791024 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.28791024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.654776067 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 158082045 ps |
| CPU time | 5.57 seconds |
| Started | Oct 03 06:30:16 AM UTC 24 |
| Finished | Oct 03 06:30:23 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654776067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.654776067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.3563425312 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4290328234 ps |
| CPU time | 51.76 seconds |
| Started | Oct 03 06:30:14 AM UTC 24 |
| Finished | Oct 03 06:31:07 AM UTC 24 |
| Peak memory | 256196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563425312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.3563425312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.3272697190 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 6187733133 ps |
| CPU time | 37.68 seconds |
| Started | Oct 03 06:30:12 AM UTC 24 |
| Finished | Oct 03 06:30:51 AM UTC 24 |
| Peak memory | 252088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272697190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.3272697190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.1283086191 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1211693996 ps |
| CPU time | 11.93 seconds |
| Started | Oct 03 06:30:16 AM UTC 24 |
| Finished | Oct 03 06:30:29 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283086191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1283086191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.3390584364 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 703436601 ps |
| CPU time | 18.29 seconds |
| Started | Oct 03 06:30:16 AM UTC 24 |
| Finished | Oct 03 06:30:36 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390584364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3390584364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.4191924421 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 413880618 ps |
| CPU time | 15.34 seconds |
| Started | Oct 03 06:30:10 AM UTC 24 |
| Finished | Oct 03 06:30:26 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191924421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.4191924421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.1694601972 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 278125412 ps |
| CPU time | 11.9 seconds |
| Started | Oct 03 06:30:10 AM UTC 24 |
| Finished | Oct 03 06:30:23 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694601972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1694601972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.931994057 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 307027524 ps |
| CPU time | 9.18 seconds |
| Started | Oct 03 06:30:16 AM UTC 24 |
| Finished | Oct 03 06:30:26 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931994057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.931994057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.2907630548 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 320380303 ps |
| CPU time | 7.19 seconds |
| Started | Oct 03 06:30:07 AM UTC 24 |
| Finished | Oct 03 06:30:15 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907630548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.2907630548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.3377094380 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1813182329 ps |
| CPU time | 49.99 seconds |
| Started | Oct 03 06:30:18 AM UTC 24 |
| Finished | Oct 03 06:31:10 AM UTC 24 |
| Peak memory | 258100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3377094380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.otp_ctrl_stress_all_with_rand_reset.3377094380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.3588692687 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1554483006 ps |
| CPU time | 15.86 seconds |
| Started | Oct 03 06:30:16 AM UTC 24 |
| Finished | Oct 03 06:30:33 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588692687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3588692687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.82640961 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 50019066 ps |
| CPU time | 2.63 seconds |
| Started | Oct 03 06:38:21 AM UTC 24 |
| Finished | Oct 03 06:38:24 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82640961 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.82640961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.1923247326 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 195919167 ps |
| CPU time | 7.28 seconds |
| Started | Oct 03 06:38:17 AM UTC 24 |
| Finished | Oct 03 06:38:25 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923247326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1923247326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.901090422 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 401572398 ps |
| CPU time | 27.4 seconds |
| Started | Oct 03 06:38:15 AM UTC 24 |
| Finished | Oct 03 06:38:43 AM UTC 24 |
| Peak memory | 252012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901090422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.901090422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.1861975822 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 369754490 ps |
| CPU time | 17.81 seconds |
| Started | Oct 03 06:38:14 AM UTC 24 |
| Finished | Oct 03 06:38:33 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861975822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1861975822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.1595771637 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 465129684 ps |
| CPU time | 6.88 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:38:17 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595771637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1595771637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.275844286 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 3160004712 ps |
| CPU time | 37.17 seconds |
| Started | Oct 03 06:38:18 AM UTC 24 |
| Finished | Oct 03 06:38:57 AM UTC 24 |
| Peak memory | 256160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275844286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.275844286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.2245219230 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 858828458 ps |
| CPU time | 13.77 seconds |
| Started | Oct 03 06:38:18 AM UTC 24 |
| Finished | Oct 03 06:38:33 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245219230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.2245219230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.141871939 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 224179230 ps |
| CPU time | 9.43 seconds |
| Started | Oct 03 06:38:14 AM UTC 24 |
| Finished | Oct 03 06:38:25 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141871939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.141871939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.348351898 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 443528020 ps |
| CPU time | 6.77 seconds |
| Started | Oct 03 06:38:11 AM UTC 24 |
| Finished | Oct 03 06:38:19 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348351898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.348351898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.1246811949 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 831213016 ps |
| CPU time | 13.6 seconds |
| Started | Oct 03 06:38:18 AM UTC 24 |
| Finished | Oct 03 06:38:33 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246811949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1246811949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.1885862357 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 807534380 ps |
| CPU time | 7.37 seconds |
| Started | Oct 03 06:38:09 AM UTC 24 |
| Finished | Oct 03 06:38:17 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885862357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1885862357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.1570212553 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 12330674563 ps |
| CPU time | 118.05 seconds |
| Started | Oct 03 06:38:21 AM UTC 24 |
| Finished | Oct 03 06:40:21 AM UTC 24 |
| Peak memory | 258200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570212553 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.1570212553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.1667564511 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 8752033446 ps |
| CPU time | 89.62 seconds |
| Started | Oct 03 06:38:21 AM UTC 24 |
| Finished | Oct 03 06:39:52 AM UTC 24 |
| Peak memory | 268408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1667564511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.otp_ctrl_stress_all_with_rand_reset.1667564511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2754896147 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1313552703 ps |
| CPU time | 33.55 seconds |
| Started | Oct 03 06:38:21 AM UTC 24 |
| Finished | Oct 03 06:38:56 AM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754896147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2754896147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.1947371396 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 124694281 ps |
| CPU time | 2.89 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:38:40 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947371396 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1947371396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.297934829 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 129959347 ps |
| CPU time | 6.22 seconds |
| Started | Oct 03 06:38:29 AM UTC 24 |
| Finished | Oct 03 06:38:36 AM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297934829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.297934829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.2087039190 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1437292439 ps |
| CPU time | 22.61 seconds |
| Started | Oct 03 06:38:29 AM UTC 24 |
| Finished | Oct 03 06:38:53 AM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087039190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2087039190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.638181219 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 997971843 ps |
| CPU time | 9.33 seconds |
| Started | Oct 03 06:38:26 AM UTC 24 |
| Finished | Oct 03 06:38:37 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638181219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.638181219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.2686831645 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 135996364 ps |
| CPU time | 5.39 seconds |
| Started | Oct 03 06:38:25 AM UTC 24 |
| Finished | Oct 03 06:38:31 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686831645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.2686831645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.639387584 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 7673699498 ps |
| CPU time | 16.53 seconds |
| Started | Oct 03 06:38:35 AM UTC 24 |
| Finished | Oct 03 06:38:53 AM UTC 24 |
| Peak memory | 258164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639387584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.639387584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.1294102585 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4816564360 ps |
| CPU time | 15.08 seconds |
| Started | Oct 03 06:38:35 AM UTC 24 |
| Finished | Oct 03 06:38:52 AM UTC 24 |
| Peak memory | 251752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294102585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1294102585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.112352875 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 438311675 ps |
| CPU time | 8.37 seconds |
| Started | Oct 03 06:38:26 AM UTC 24 |
| Finished | Oct 03 06:38:36 AM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112352875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.112352875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.2732441781 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 401275235 ps |
| CPU time | 9.31 seconds |
| Started | Oct 03 06:38:26 AM UTC 24 |
| Finished | Oct 03 06:38:36 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732441781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2732441781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.4009041747 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4646703646 ps |
| CPU time | 18.33 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:38:55 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009041747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.4009041747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.563351556 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1042971568 ps |
| CPU time | 8.21 seconds |
| Started | Oct 03 06:38:23 AM UTC 24 |
| Finished | Oct 03 06:38:33 AM UTC 24 |
| Peak memory | 252056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563351556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.563351556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.3474622827 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 2702172139 ps |
| CPU time | 44.46 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:39:22 AM UTC 24 |
| Peak memory | 253880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474622827 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.3474622827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.1695723221 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 190155133 ps |
| CPU time | 7.7 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:38:44 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695723221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1695723221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.852185508 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 279936195 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 06:38:51 AM UTC 24 |
| Finished | Oct 03 06:38:55 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852185508 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.852185508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.2193536004 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 481428148 ps |
| CPU time | 12.37 seconds |
| Started | Oct 03 06:38:37 AM UTC 24 |
| Finished | Oct 03 06:38:51 AM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193536004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2193536004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.1902931220 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 768715797 ps |
| CPU time | 24.98 seconds |
| Started | Oct 03 06:38:37 AM UTC 24 |
| Finished | Oct 03 06:39:04 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902931220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1902931220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.1610413358 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2338566434 ps |
| CPU time | 16.18 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:38:53 AM UTC 24 |
| Peak memory | 252004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610413358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1610413358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.4236702796 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1568445865 ps |
| CPU time | 8.21 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:38:45 AM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236702796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4236702796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.3348295140 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4366078148 ps |
| CPU time | 23.92 seconds |
| Started | Oct 03 06:38:37 AM UTC 24 |
| Finished | Oct 03 06:39:03 AM UTC 24 |
| Peak memory | 258252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348295140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.3348295140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.2042008821 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 10642602368 ps |
| CPU time | 28.13 seconds |
| Started | Oct 03 06:38:37 AM UTC 24 |
| Finished | Oct 03 06:39:07 AM UTC 24 |
| Peak memory | 253968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042008821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2042008821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.54394487 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5750051229 ps |
| CPU time | 15.31 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:38:52 AM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54394487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.54394487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.739152081 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5041630362 ps |
| CPU time | 16.39 seconds |
| Started | Oct 03 06:38:39 AM UTC 24 |
| Finished | Oct 03 06:38:57 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739152081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.739152081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.2223979049 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 201915958 ps |
| CPU time | 4.6 seconds |
| Started | Oct 03 06:38:36 AM UTC 24 |
| Finished | Oct 03 06:38:41 AM UTC 24 |
| Peak memory | 252060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223979049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2223979049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.2441238810 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1540720076 ps |
| CPU time | 34.03 seconds |
| Started | Oct 03 06:38:39 AM UTC 24 |
| Finished | Oct 03 06:39:15 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441238810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2441238810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.1224469546 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 97461165 ps |
| CPU time | 2.91 seconds |
| Started | Oct 03 06:38:53 AM UTC 24 |
| Finished | Oct 03 06:38:57 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224469546 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1224469546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.3798003463 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 353146299 ps |
| CPU time | 9.67 seconds |
| Started | Oct 03 06:38:52 AM UTC 24 |
| Finished | Oct 03 06:39:02 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798003463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3798003463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.4103841607 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1997765992 ps |
| CPU time | 48.19 seconds |
| Started | Oct 03 06:38:52 AM UTC 24 |
| Finished | Oct 03 06:39:41 AM UTC 24 |
| Peak memory | 258020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103841607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.4103841607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.3944989886 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 21828648548 ps |
| CPU time | 65.51 seconds |
| Started | Oct 03 06:38:52 AM UTC 24 |
| Finished | Oct 03 06:39:59 AM UTC 24 |
| Peak memory | 253972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944989886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3944989886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.849211684 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 247041351 ps |
| CPU time | 4.61 seconds |
| Started | Oct 03 06:38:51 AM UTC 24 |
| Finished | Oct 03 06:38:57 AM UTC 24 |
| Peak memory | 251684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849211684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.849211684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.3785514017 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1375200245 ps |
| CPU time | 43.14 seconds |
| Started | Oct 03 06:38:52 AM UTC 24 |
| Finished | Oct 03 06:39:36 AM UTC 24 |
| Peak memory | 258132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785514017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.3785514017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.1980308813 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1763425014 ps |
| CPU time | 24.44 seconds |
| Started | Oct 03 06:38:52 AM UTC 24 |
| Finished | Oct 03 06:39:17 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980308813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1980308813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.4225268416 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 703993677 ps |
| CPU time | 12.48 seconds |
| Started | Oct 03 06:38:51 AM UTC 24 |
| Finished | Oct 03 06:39:05 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225268416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.4225268416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.906451035 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1164831557 ps |
| CPU time | 15.57 seconds |
| Started | Oct 03 06:38:51 AM UTC 24 |
| Finished | Oct 03 06:39:08 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906451035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.906451035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.426551652 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1600214543 ps |
| CPU time | 8.66 seconds |
| Started | Oct 03 06:38:52 AM UTC 24 |
| Finished | Oct 03 06:39:01 AM UTC 24 |
| Peak memory | 251748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426551652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.426551652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.4236435566 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 488474755 ps |
| CPU time | 4.04 seconds |
| Started | Oct 03 06:38:51 AM UTC 24 |
| Finished | Oct 03 06:38:56 AM UTC 24 |
| Peak memory | 251868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236435566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.4236435566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.4030568334 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 12416413328 ps |
| CPU time | 169.18 seconds |
| Started | Oct 03 06:38:53 AM UTC 24 |
| Finished | Oct 03 06:41:45 AM UTC 24 |
| Peak memory | 268376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030568334 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.4030568334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.767478915 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 29406988992 ps |
| CPU time | 53.3 seconds |
| Started | Oct 03 06:38:52 AM UTC 24 |
| Finished | Oct 03 06:39:47 AM UTC 24 |
| Peak memory | 268316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=767478915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.767478915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.852309122 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 11551550492 ps |
| CPU time | 26.74 seconds |
| Started | Oct 03 06:38:52 AM UTC 24 |
| Finished | Oct 03 06:39:20 AM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852309122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.852309122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.2307394957 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 313172405 ps |
| CPU time | 3.28 seconds |
| Started | Oct 03 06:39:04 AM UTC 24 |
| Finished | Oct 03 06:39:08 AM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307394957 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.2307394957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.2994820801 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 875681965 ps |
| CPU time | 6.18 seconds |
| Started | Oct 03 06:38:58 AM UTC 24 |
| Finished | Oct 03 06:39:06 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994820801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.2994820801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.2127412102 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4029414718 ps |
| CPU time | 40.06 seconds |
| Started | Oct 03 06:38:58 AM UTC 24 |
| Finished | Oct 03 06:39:40 AM UTC 24 |
| Peak memory | 258276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127412102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2127412102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.1597095796 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 624466847 ps |
| CPU time | 28.12 seconds |
| Started | Oct 03 06:38:58 AM UTC 24 |
| Finished | Oct 03 06:39:28 AM UTC 24 |
| Peak memory | 251940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597095796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.1597095796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.896009304 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2536473228 ps |
| CPU time | 8.8 seconds |
| Started | Oct 03 06:38:55 AM UTC 24 |
| Finished | Oct 03 06:39:05 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896009304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.896009304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.948741770 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1732418199 ps |
| CPU time | 22.42 seconds |
| Started | Oct 03 06:38:58 AM UTC 24 |
| Finished | Oct 03 06:39:22 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948741770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.948741770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.1498540571 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1356498012 ps |
| CPU time | 35.95 seconds |
| Started | Oct 03 06:38:59 AM UTC 24 |
| Finished | Oct 03 06:39:36 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498540571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1498540571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.3775159804 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 7478368530 ps |
| CPU time | 20.28 seconds |
| Started | Oct 03 06:38:58 AM UTC 24 |
| Finished | Oct 03 06:39:20 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775159804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3775159804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.780890365 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 837356299 ps |
| CPU time | 29.07 seconds |
| Started | Oct 03 06:38:55 AM UTC 24 |
| Finished | Oct 03 06:39:26 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780890365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.780890365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.948087636 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 530412538 ps |
| CPU time | 6.67 seconds |
| Started | Oct 03 06:38:59 AM UTC 24 |
| Finished | Oct 03 06:39:06 AM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948087636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.948087636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.1820980839 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5687717642 ps |
| CPU time | 12.09 seconds |
| Started | Oct 03 06:38:55 AM UTC 24 |
| Finished | Oct 03 06:39:08 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820980839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1820980839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.2754526115 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 11816444255 ps |
| CPU time | 136.43 seconds |
| Started | Oct 03 06:39:04 AM UTC 24 |
| Finished | Oct 03 06:41:23 AM UTC 24 |
| Peak memory | 274496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754526115 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.2754526115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.3095534947 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 2809149863 ps |
| CPU time | 35.91 seconds |
| Started | Oct 03 06:38:59 AM UTC 24 |
| Finished | Oct 03 06:39:36 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095534947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3095534947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.2175538951 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 50636419 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 06:39:16 AM UTC 24 |
| Finished | Oct 03 06:39:20 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175538951 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2175538951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.4204728029 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1525470523 ps |
| CPU time | 33.17 seconds |
| Started | Oct 03 06:39:06 AM UTC 24 |
| Finished | Oct 03 06:39:41 AM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204728029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.4204728029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.1657948871 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1690504793 ps |
| CPU time | 19.67 seconds |
| Started | Oct 03 06:39:06 AM UTC 24 |
| Finished | Oct 03 06:39:27 AM UTC 24 |
| Peak memory | 252124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657948871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1657948871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.562265170 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 365237822 ps |
| CPU time | 15.75 seconds |
| Started | Oct 03 06:39:08 AM UTC 24 |
| Finished | Oct 03 06:39:25 AM UTC 24 |
| Peak memory | 251992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562265170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.562265170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.3546302101 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 602817850 ps |
| CPU time | 15.08 seconds |
| Started | Oct 03 06:39:09 AM UTC 24 |
| Finished | Oct 03 06:39:26 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546302101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3546302101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.1677106417 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 350036935 ps |
| CPU time | 12.92 seconds |
| Started | Oct 03 06:39:06 AM UTC 24 |
| Finished | Oct 03 06:39:20 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677106417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1677106417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.4025647200 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1350364021 ps |
| CPU time | 22.86 seconds |
| Started | Oct 03 06:39:06 AM UTC 24 |
| Finished | Oct 03 06:39:30 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025647200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.4025647200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.4057517482 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1143647257 ps |
| CPU time | 16.8 seconds |
| Started | Oct 03 06:39:09 AM UTC 24 |
| Finished | Oct 03 06:39:27 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057517482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.4057517482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.4228378859 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 224683558 ps |
| CPU time | 8.31 seconds |
| Started | Oct 03 06:39:04 AM UTC 24 |
| Finished | Oct 03 06:39:13 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228378859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.4228378859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.1787890793 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1256806054 ps |
| CPU time | 44.68 seconds |
| Started | Oct 03 06:39:14 AM UTC 24 |
| Finished | Oct 03 06:40:00 AM UTC 24 |
| Peak memory | 253888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787890793 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.1787890793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.509653941 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 836082603 ps |
| CPU time | 32.66 seconds |
| Started | Oct 03 06:39:09 AM UTC 24 |
| Finished | Oct 03 06:39:43 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509653941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.509653941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.1185940194 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 790968480 ps |
| CPU time | 2.95 seconds |
| Started | Oct 03 06:39:27 AM UTC 24 |
| Finished | Oct 03 06:39:31 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185940194 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1185940194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.384850782 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 187483610 ps |
| CPU time | 8.29 seconds |
| Started | Oct 03 06:39:21 AM UTC 24 |
| Finished | Oct 03 06:39:30 AM UTC 24 |
| Peak memory | 251936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384850782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.384850782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.2482377765 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 412876567 ps |
| CPU time | 15.8 seconds |
| Started | Oct 03 06:39:21 AM UTC 24 |
| Finished | Oct 03 06:39:38 AM UTC 24 |
| Peak memory | 252132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482377765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2482377765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.3295917732 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 6674208232 ps |
| CPU time | 30.59 seconds |
| Started | Oct 03 06:39:21 AM UTC 24 |
| Finished | Oct 03 06:39:53 AM UTC 24 |
| Peak memory | 252132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295917732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.3295917732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.1372119788 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 335725205 ps |
| CPU time | 7.53 seconds |
| Started | Oct 03 06:39:18 AM UTC 24 |
| Finished | Oct 03 06:39:27 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372119788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.1372119788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.387559959 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 14287552864 ps |
| CPU time | 36.39 seconds |
| Started | Oct 03 06:39:24 AM UTC 24 |
| Finished | Oct 03 06:40:02 AM UTC 24 |
| Peak memory | 258200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387559959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.387559959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.2035264847 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 636633173 ps |
| CPU time | 12.91 seconds |
| Started | Oct 03 06:39:24 AM UTC 24 |
| Finished | Oct 03 06:39:38 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035264847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.2035264847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.56380586 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 339403897 ps |
| CPU time | 9.02 seconds |
| Started | Oct 03 06:39:21 AM UTC 24 |
| Finished | Oct 03 06:39:31 AM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56380586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.56380586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.283197961 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 432245090 ps |
| CPU time | 6.99 seconds |
| Started | Oct 03 06:39:18 AM UTC 24 |
| Finished | Oct 03 06:39:26 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283197961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.283197961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.2345623676 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 295155177 ps |
| CPU time | 10.2 seconds |
| Started | Oct 03 06:39:24 AM UTC 24 |
| Finished | Oct 03 06:39:36 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345623676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2345623676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.599435232 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 332856716 ps |
| CPU time | 7.8 seconds |
| Started | Oct 03 06:39:18 AM UTC 24 |
| Finished | Oct 03 06:39:27 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599435232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.599435232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.2984451078 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 34173783856 ps |
| CPU time | 264.33 seconds |
| Started | Oct 03 06:39:27 AM UTC 24 |
| Finished | Oct 03 06:43:55 AM UTC 24 |
| Peak memory | 274588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984451078 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.2984451078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.1199518318 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 1453069478 ps |
| CPU time | 41.1 seconds |
| Started | Oct 03 06:39:27 AM UTC 24 |
| Finished | Oct 03 06:40:09 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199518318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.1199518318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.129890011 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 923704563 ps |
| CPU time | 2.83 seconds |
| Started | Oct 03 06:39:40 AM UTC 24 |
| Finished | Oct 03 06:39:44 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129890011 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.129890011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.3427253120 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 543265052 ps |
| CPU time | 19.71 seconds |
| Started | Oct 03 06:39:31 AM UTC 24 |
| Finished | Oct 03 06:39:53 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427253120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3427253120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.1487603422 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 24352204835 ps |
| CPU time | 60.72 seconds |
| Started | Oct 03 06:39:31 AM UTC 24 |
| Finished | Oct 03 06:40:34 AM UTC 24 |
| Peak memory | 266404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487603422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1487603422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.1971521370 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1501853027 ps |
| CPU time | 29.64 seconds |
| Started | Oct 03 06:39:29 AM UTC 24 |
| Finished | Oct 03 06:40:01 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971521370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.1971521370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.941283895 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 374239866 ps |
| CPU time | 3.74 seconds |
| Started | Oct 03 06:39:29 AM UTC 24 |
| Finished | Oct 03 06:39:34 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941283895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.941283895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.2037867299 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 832198231 ps |
| CPU time | 22.5 seconds |
| Started | Oct 03 06:39:31 AM UTC 24 |
| Finished | Oct 03 06:39:55 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037867299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2037867299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.836819436 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 221577396 ps |
| CPU time | 4.61 seconds |
| Started | Oct 03 06:39:33 AM UTC 24 |
| Finished | Oct 03 06:39:39 AM UTC 24 |
| Peak memory | 251932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836819436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.836819436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.2190870256 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 337290627 ps |
| CPU time | 23.82 seconds |
| Started | Oct 03 06:39:29 AM UTC 24 |
| Finished | Oct 03 06:39:55 AM UTC 24 |
| Peak memory | 251900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190870256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2190870256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.1245211812 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 750627894 ps |
| CPU time | 20.49 seconds |
| Started | Oct 03 06:39:29 AM UTC 24 |
| Finished | Oct 03 06:39:51 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245211812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1245211812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.2921551562 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 192013993 ps |
| CPU time | 4.67 seconds |
| Started | Oct 03 06:39:33 AM UTC 24 |
| Finished | Oct 03 06:39:39 AM UTC 24 |
| Peak memory | 251944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921551562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2921551562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.3403880360 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 660573781 ps |
| CPU time | 14.35 seconds |
| Started | Oct 03 06:39:29 AM UTC 24 |
| Finished | Oct 03 06:39:45 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403880360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3403880360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.578513533 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1490489789 ps |
| CPU time | 12.58 seconds |
| Started | Oct 03 06:39:36 AM UTC 24 |
| Finished | Oct 03 06:39:49 AM UTC 24 |
| Peak memory | 251820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578513533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.578513533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.1303793282 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 46794947 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 06:39:47 AM UTC 24 |
| Finished | Oct 03 06:39:51 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303793282 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1303793282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.1398420315 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2712363770 ps |
| CPU time | 18.31 seconds |
| Started | Oct 03 06:39:43 AM UTC 24 |
| Finished | Oct 03 06:40:03 AM UTC 24 |
| Peak memory | 252108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398420315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1398420315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.301450676 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 575939214 ps |
| CPU time | 18.12 seconds |
| Started | Oct 03 06:39:43 AM UTC 24 |
| Finished | Oct 03 06:40:03 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301450676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.301450676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.1247929772 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 7715963239 ps |
| CPU time | 47.89 seconds |
| Started | Oct 03 06:39:41 AM UTC 24 |
| Finished | Oct 03 06:40:30 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247929772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1247929772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.3462469513 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 291346974 ps |
| CPU time | 4.57 seconds |
| Started | Oct 03 06:39:40 AM UTC 24 |
| Finished | Oct 03 06:39:46 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462469513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3462469513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.816099002 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 11386749895 ps |
| CPU time | 27.73 seconds |
| Started | Oct 03 06:39:43 AM UTC 24 |
| Finished | Oct 03 06:40:13 AM UTC 24 |
| Peak memory | 256080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816099002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.816099002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.2972799192 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 639420486 ps |
| CPU time | 27.05 seconds |
| Started | Oct 03 06:39:47 AM UTC 24 |
| Finished | Oct 03 06:40:16 AM UTC 24 |
| Peak memory | 253880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972799192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2972799192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2409310499 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 891832965 ps |
| CPU time | 21.18 seconds |
| Started | Oct 03 06:39:41 AM UTC 24 |
| Finished | Oct 03 06:40:03 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409310499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2409310499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.3483643928 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 825836056 ps |
| CPU time | 26.78 seconds |
| Started | Oct 03 06:39:41 AM UTC 24 |
| Finished | Oct 03 06:40:09 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483643928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.3483643928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.2469020892 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 303281483 ps |
| CPU time | 11.81 seconds |
| Started | Oct 03 06:39:47 AM UTC 24 |
| Finished | Oct 03 06:40:00 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469020892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.2469020892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.1604630922 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3610133943 ps |
| CPU time | 9.11 seconds |
| Started | Oct 03 06:39:40 AM UTC 24 |
| Finished | Oct 03 06:39:51 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604630922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1604630922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3718069450 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 20932588972 ps |
| CPU time | 240.89 seconds |
| Started | Oct 03 06:39:47 AM UTC 24 |
| Finished | Oct 03 06:43:52 AM UTC 24 |
| Peak memory | 258252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718069450 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.3718069450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.1025538078 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 5217945759 ps |
| CPU time | 38.79 seconds |
| Started | Oct 03 06:39:47 AM UTC 24 |
| Finished | Oct 03 06:40:28 AM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025538078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1025538078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.2029060812 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 54387387 ps |
| CPU time | 2.63 seconds |
| Started | Oct 03 06:40:03 AM UTC 24 |
| Finished | Oct 03 06:40:06 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029060812 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.2029060812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.115221649 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 606097360 ps |
| CPU time | 7.9 seconds |
| Started | Oct 03 06:39:55 AM UTC 24 |
| Finished | Oct 03 06:40:04 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115221649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.115221649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.3025555231 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 9099261053 ps |
| CPU time | 24.82 seconds |
| Started | Oct 03 06:39:55 AM UTC 24 |
| Finished | Oct 03 06:40:21 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025555231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.3025555231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.311161595 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 729440651 ps |
| CPU time | 15.2 seconds |
| Started | Oct 03 06:39:55 AM UTC 24 |
| Finished | Oct 03 06:40:11 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311161595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.311161595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.1842217293 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 654290469 ps |
| CPU time | 5.95 seconds |
| Started | Oct 03 06:39:50 AM UTC 24 |
| Finished | Oct 03 06:39:57 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842217293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.1842217293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.259130843 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 1058963950 ps |
| CPU time | 32.92 seconds |
| Started | Oct 03 06:39:55 AM UTC 24 |
| Finished | Oct 03 06:40:29 AM UTC 24 |
| Peak memory | 254176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259130843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.259130843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.3857310281 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 553102078 ps |
| CPU time | 17.11 seconds |
| Started | Oct 03 06:39:55 AM UTC 24 |
| Finished | Oct 03 06:40:13 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857310281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3857310281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.1473711242 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 862242703 ps |
| CPU time | 18.22 seconds |
| Started | Oct 03 06:39:55 AM UTC 24 |
| Finished | Oct 03 06:40:14 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473711242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.1473711242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.1929565715 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1353710831 ps |
| CPU time | 34.24 seconds |
| Started | Oct 03 06:39:55 AM UTC 24 |
| Finished | Oct 03 06:40:30 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929565715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1929565715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.4199663128 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 246055595 ps |
| CPU time | 10.26 seconds |
| Started | Oct 03 06:39:55 AM UTC 24 |
| Finished | Oct 03 06:40:06 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199663128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.4199663128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.4045636621 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 773579315 ps |
| CPU time | 16.67 seconds |
| Started | Oct 03 06:39:49 AM UTC 24 |
| Finished | Oct 03 06:40:07 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045636621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.4045636621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.4090062446 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 976281981 ps |
| CPU time | 23.38 seconds |
| Started | Oct 03 06:40:03 AM UTC 24 |
| Finished | Oct 03 06:40:27 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090062446 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.4090062446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.2386414730 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 620321498 ps |
| CPU time | 6.06 seconds |
| Started | Oct 03 06:39:57 AM UTC 24 |
| Finished | Oct 03 06:40:04 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386414730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.2386414730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.3127323567 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 99940248 ps |
| CPU time | 3.13 seconds |
| Started | Oct 03 06:30:45 AM UTC 24 |
| Finished | Oct 03 06:30:49 AM UTC 24 |
| Peak memory | 251652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127323567 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3127323567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.2340520442 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1891737042 ps |
| CPU time | 23.19 seconds |
| Started | Oct 03 06:30:28 AM UTC 24 |
| Finished | Oct 03 06:30:52 AM UTC 24 |
| Peak memory | 252104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340520442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2340520442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.3384646459 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1420646247 ps |
| CPU time | 31.8 seconds |
| Started | Oct 03 06:30:36 AM UTC 24 |
| Finished | Oct 03 06:31:09 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384646459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3384646459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.3132815862 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1127469501 ps |
| CPU time | 32.64 seconds |
| Started | Oct 03 06:30:36 AM UTC 24 |
| Finished | Oct 03 06:31:10 AM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132815862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3132815862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.3159106257 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2052557194 ps |
| CPU time | 29.76 seconds |
| Started | Oct 03 06:30:30 AM UTC 24 |
| Finished | Oct 03 06:31:02 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159106257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3159106257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.57703128 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 794971825 ps |
| CPU time | 15.43 seconds |
| Started | Oct 03 06:30:37 AM UTC 24 |
| Finished | Oct 03 06:30:54 AM UTC 24 |
| Peak memory | 254104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57703128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.57703128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.3885808547 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1057205753 ps |
| CPU time | 18.13 seconds |
| Started | Oct 03 06:30:39 AM UTC 24 |
| Finished | Oct 03 06:30:59 AM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885808547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3885808547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.430532254 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 793173740 ps |
| CPU time | 13.85 seconds |
| Started | Oct 03 06:30:30 AM UTC 24 |
| Finished | Oct 03 06:30:45 AM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430532254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.430532254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.2700465931 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 10724248833 ps |
| CPU time | 45.69 seconds |
| Started | Oct 03 06:30:28 AM UTC 24 |
| Finished | Oct 03 06:31:15 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700465931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.2700465931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.1260191869 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 149598239 ps |
| CPU time | 5.14 seconds |
| Started | Oct 03 06:30:39 AM UTC 24 |
| Finished | Oct 03 06:30:45 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260191869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.1260191869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.817333400 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 628181349 ps |
| CPU time | 14.64 seconds |
| Started | Oct 03 06:30:25 AM UTC 24 |
| Finished | Oct 03 06:30:41 AM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817333400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.817333400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.3471403426 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 530927867 ps |
| CPU time | 3.81 seconds |
| Started | Oct 03 06:40:03 AM UTC 24 |
| Finished | Oct 03 06:40:08 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471403426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.3471403426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.4197766609 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 287723024 ps |
| CPU time | 3.22 seconds |
| Started | Oct 03 06:40:03 AM UTC 24 |
| Finished | Oct 03 06:40:07 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197766609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.4197766609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1667748663 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3500353475 ps |
| CPU time | 87.63 seconds |
| Started | Oct 03 06:40:03 AM UTC 24 |
| Finished | Oct 03 06:41:32 AM UTC 24 |
| Peak memory | 257968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1667748663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 50.otp_ctrl_stress_all_with_rand_reset.1667748663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.2302202446 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 107533577 ps |
| CPU time | 4.62 seconds |
| Started | Oct 03 06:40:03 AM UTC 24 |
| Finished | Oct 03 06:40:09 AM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302202446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2302202446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.3611499483 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 4177182167 ps |
| CPU time | 20.77 seconds |
| Started | Oct 03 06:40:05 AM UTC 24 |
| Finished | Oct 03 06:40:27 AM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611499483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3611499483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.107478132 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 7214507401 ps |
| CPU time | 63.03 seconds |
| Started | Oct 03 06:40:05 AM UTC 24 |
| Finished | Oct 03 06:41:10 AM UTC 24 |
| Peak memory | 268480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=107478132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.107478132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.864765249 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 138585233 ps |
| CPU time | 4.47 seconds |
| Started | Oct 03 06:40:05 AM UTC 24 |
| Finished | Oct 03 06:40:10 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864765249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.864765249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.277982406 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3953652723 ps |
| CPU time | 20.5 seconds |
| Started | Oct 03 06:40:05 AM UTC 24 |
| Finished | Oct 03 06:40:27 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277982406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.277982406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.3165831572 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1698176473 ps |
| CPU time | 6.7 seconds |
| Started | Oct 03 06:40:05 AM UTC 24 |
| Finished | Oct 03 06:40:13 AM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165831572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3165831572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.2063836014 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 643640335 ps |
| CPU time | 9.01 seconds |
| Started | Oct 03 06:40:09 AM UTC 24 |
| Finished | Oct 03 06:40:19 AM UTC 24 |
| Peak memory | 251840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063836014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.2063836014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.1479155380 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 124888556 ps |
| CPU time | 5.49 seconds |
| Started | Oct 03 06:40:09 AM UTC 24 |
| Finished | Oct 03 06:40:16 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479155380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1479155380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.2814767647 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 314249974 ps |
| CPU time | 8.86 seconds |
| Started | Oct 03 06:40:09 AM UTC 24 |
| Finished | Oct 03 06:40:19 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814767647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2814767647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.225343971 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 19412318889 ps |
| CPU time | 101.99 seconds |
| Started | Oct 03 06:40:09 AM UTC 24 |
| Finished | Oct 03 06:41:54 AM UTC 24 |
| Peak memory | 258160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=225343971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.225343971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.1702033907 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 448885359 ps |
| CPU time | 3.98 seconds |
| Started | Oct 03 06:40:09 AM UTC 24 |
| Finished | Oct 03 06:40:14 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702033907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1702033907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.1008032576 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3194273700 ps |
| CPU time | 16.9 seconds |
| Started | Oct 03 06:40:09 AM UTC 24 |
| Finished | Oct 03 06:40:27 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008032576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1008032576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.172061133 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 18433473282 ps |
| CPU time | 88.34 seconds |
| Started | Oct 03 06:40:09 AM UTC 24 |
| Finished | Oct 03 06:41:40 AM UTC 24 |
| Peak memory | 258256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=172061133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.172061133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.2792487477 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 430282519 ps |
| CPU time | 6.03 seconds |
| Started | Oct 03 06:40:12 AM UTC 24 |
| Finished | Oct 03 06:40:19 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792487477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2792487477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.855121550 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 409683959 ps |
| CPU time | 7.97 seconds |
| Started | Oct 03 06:40:12 AM UTC 24 |
| Finished | Oct 03 06:40:21 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855121550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.855121550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2095721876 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 16449459884 ps |
| CPU time | 72.39 seconds |
| Started | Oct 03 06:40:12 AM UTC 24 |
| Finished | Oct 03 06:41:26 AM UTC 24 |
| Peak memory | 257944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2095721876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 56.otp_ctrl_stress_all_with_rand_reset.2095721876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.172431201 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 184812967 ps |
| CPU time | 4.02 seconds |
| Started | Oct 03 06:40:12 AM UTC 24 |
| Finished | Oct 03 06:40:17 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172431201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.172431201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.877631490 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 208281222 ps |
| CPU time | 12.27 seconds |
| Started | Oct 03 06:40:15 AM UTC 24 |
| Finished | Oct 03 06:40:28 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877631490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.877631490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.247719918 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 30613412003 ps |
| CPU time | 72.6 seconds |
| Started | Oct 03 06:40:15 AM UTC 24 |
| Finished | Oct 03 06:41:29 AM UTC 24 |
| Peak memory | 274524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=247719918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.247719918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.4268163591 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 2698533560 ps |
| CPU time | 10.42 seconds |
| Started | Oct 03 06:40:15 AM UTC 24 |
| Finished | Oct 03 06:40:26 AM UTC 24 |
| Peak memory | 251828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268163591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.4268163591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.3811270091 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 3626100087 ps |
| CPU time | 11.93 seconds |
| Started | Oct 03 06:40:15 AM UTC 24 |
| Finished | Oct 03 06:40:28 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811270091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3811270091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2739154099 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 33874110217 ps |
| CPU time | 162.78 seconds |
| Started | Oct 03 06:40:16 AM UTC 24 |
| Finished | Oct 03 06:43:02 AM UTC 24 |
| Peak memory | 272724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2739154099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 58.otp_ctrl_stress_all_with_rand_reset.2739154099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.1075948396 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 151991218 ps |
| CPU time | 4.42 seconds |
| Started | Oct 03 06:40:16 AM UTC 24 |
| Finished | Oct 03 06:40:22 AM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075948396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1075948396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.129519611 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 409434789 ps |
| CPU time | 14.3 seconds |
| Started | Oct 03 06:40:16 AM UTC 24 |
| Finished | Oct 03 06:40:32 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129519611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.129519611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.2389814648 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 635183317 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 06:31:09 AM UTC 24 |
| Finished | Oct 03 06:31:12 AM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389814648 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2389814648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.1047424133 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 22504607897 ps |
| CPU time | 91.45 seconds |
| Started | Oct 03 06:30:55 AM UTC 24 |
| Finished | Oct 03 06:32:29 AM UTC 24 |
| Peak memory | 262148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047424133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1047424133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.1459470942 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 461630740 ps |
| CPU time | 14.05 seconds |
| Started | Oct 03 06:30:54 AM UTC 24 |
| Finished | Oct 03 06:31:09 AM UTC 24 |
| Peak memory | 251884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459470942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1459470942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.3054416851 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 174048490 ps |
| CPU time | 5.23 seconds |
| Started | Oct 03 06:30:46 AM UTC 24 |
| Finished | Oct 03 06:30:53 AM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054416851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3054416851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.2576055863 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 317640209 ps |
| CPU time | 13.85 seconds |
| Started | Oct 03 06:31:00 AM UTC 24 |
| Finished | Oct 03 06:31:15 AM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576055863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2576055863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.2244327258 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 425269670 ps |
| CPU time | 11.06 seconds |
| Started | Oct 03 06:31:00 AM UTC 24 |
| Finished | Oct 03 06:31:13 AM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244327258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2244327258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.2334351747 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 592189255 ps |
| CPU time | 20.45 seconds |
| Started | Oct 03 06:30:54 AM UTC 24 |
| Finished | Oct 03 06:31:16 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334351747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.2334351747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.2637694580 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3448717311 ps |
| CPU time | 9.76 seconds |
| Started | Oct 03 06:31:01 AM UTC 24 |
| Finished | Oct 03 06:31:12 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637694580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2637694580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.2696370826 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 894363920 ps |
| CPU time | 12.45 seconds |
| Started | Oct 03 06:30:46 AM UTC 24 |
| Finished | Oct 03 06:31:00 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696370826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2696370826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.2314000204 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 33322333873 ps |
| CPU time | 100.42 seconds |
| Started | Oct 03 06:31:04 AM UTC 24 |
| Finished | Oct 03 06:32:47 AM UTC 24 |
| Peak memory | 268416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2314000204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.otp_ctrl_stress_all_with_rand_reset.2314000204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.2943620303 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 236412760 ps |
| CPU time | 7.69 seconds |
| Started | Oct 03 06:31:02 AM UTC 24 |
| Finished | Oct 03 06:31:11 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943620303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2943620303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.4065990651 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 140659690 ps |
| CPU time | 4.52 seconds |
| Started | Oct 03 06:40:18 AM UTC 24 |
| Finished | Oct 03 06:40:24 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065990651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.4065990651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.1864309572 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 12248182855 ps |
| CPU time | 36.33 seconds |
| Started | Oct 03 06:40:19 AM UTC 24 |
| Finished | Oct 03 06:40:57 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864309572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1864309572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.586885439 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 251080707 ps |
| CPU time | 5.56 seconds |
| Started | Oct 03 06:40:21 AM UTC 24 |
| Finished | Oct 03 06:40:28 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586885439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.586885439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.237175516 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 132442445 ps |
| CPU time | 4.4 seconds |
| Started | Oct 03 06:40:24 AM UTC 24 |
| Finished | Oct 03 06:40:30 AM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237175516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.237175516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.1065302142 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 251559107 ps |
| CPU time | 5.77 seconds |
| Started | Oct 03 06:40:24 AM UTC 24 |
| Finished | Oct 03 06:40:31 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065302142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1065302142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.2723702969 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 122980749 ps |
| CPU time | 4.97 seconds |
| Started | Oct 03 06:40:24 AM UTC 24 |
| Finished | Oct 03 06:40:30 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723702969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.2723702969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.1931743414 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 293083336 ps |
| CPU time | 4.39 seconds |
| Started | Oct 03 06:40:28 AM UTC 24 |
| Finished | Oct 03 06:40:33 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931743414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.1931743414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.1360439804 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 666517797 ps |
| CPU time | 9.15 seconds |
| Started | Oct 03 06:40:28 AM UTC 24 |
| Finished | Oct 03 06:40:38 AM UTC 24 |
| Peak memory | 251796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360439804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1360439804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.239821160 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3221552431 ps |
| CPU time | 17.24 seconds |
| Started | Oct 03 06:40:30 AM UTC 24 |
| Finished | Oct 03 06:40:49 AM UTC 24 |
| Peak memory | 258100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=239821160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.239821160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.2682171203 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 175209116 ps |
| CPU time | 5.57 seconds |
| Started | Oct 03 06:40:30 AM UTC 24 |
| Finished | Oct 03 06:40:37 AM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682171203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2682171203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.2915451650 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 27431696155 ps |
| CPU time | 97.14 seconds |
| Started | Oct 03 06:40:31 AM UTC 24 |
| Finished | Oct 03 06:42:10 AM UTC 24 |
| Peak memory | 268496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2915451650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 64.otp_ctrl_stress_all_with_rand_reset.2915451650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3921681451 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 457749631 ps |
| CPU time | 3.6 seconds |
| Started | Oct 03 06:40:31 AM UTC 24 |
| Finished | Oct 03 06:40:35 AM UTC 24 |
| Peak memory | 251804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921681451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3921681451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.2793039816 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 891304624 ps |
| CPU time | 30.78 seconds |
| Started | Oct 03 06:40:31 AM UTC 24 |
| Finished | Oct 03 06:41:03 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793039816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2793039816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.969783744 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 19111990512 ps |
| CPU time | 177.12 seconds |
| Started | Oct 03 06:40:31 AM UTC 24 |
| Finished | Oct 03 06:43:31 AM UTC 24 |
| Peak memory | 268500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=969783744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.969783744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.3735366128 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 662853669 ps |
| CPU time | 5.65 seconds |
| Started | Oct 03 06:40:31 AM UTC 24 |
| Finished | Oct 03 06:40:37 AM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735366128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3735366128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.1992445141 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 322716041 ps |
| CPU time | 9.94 seconds |
| Started | Oct 03 06:40:31 AM UTC 24 |
| Finished | Oct 03 06:40:42 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992445141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.1992445141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.3516864944 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1403641394 ps |
| CPU time | 6.49 seconds |
| Started | Oct 03 06:40:38 AM UTC 24 |
| Finished | Oct 03 06:40:46 AM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516864944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3516864944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.577058904 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 326987623 ps |
| CPU time | 11.14 seconds |
| Started | Oct 03 06:40:38 AM UTC 24 |
| Finished | Oct 03 06:40:51 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577058904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.577058904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.3289808280 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 423718650 ps |
| CPU time | 4.88 seconds |
| Started | Oct 03 06:40:39 AM UTC 24 |
| Finished | Oct 03 06:40:44 AM UTC 24 |
| Peak memory | 251812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289808280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3289808280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.2208604277 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 666758010 ps |
| CPU time | 12.49 seconds |
| Started | Oct 03 06:40:39 AM UTC 24 |
| Finished | Oct 03 06:40:52 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208604277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.2208604277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.3690457725 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 470522769 ps |
| CPU time | 4.96 seconds |
| Started | Oct 03 06:40:39 AM UTC 24 |
| Finished | Oct 03 06:40:45 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690457725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3690457725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.2709996214 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 235112984 ps |
| CPU time | 8.05 seconds |
| Started | Oct 03 06:40:39 AM UTC 24 |
| Finished | Oct 03 06:40:48 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709996214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2709996214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.944348941 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 910498158 ps |
| CPU time | 2.96 seconds |
| Started | Oct 03 06:31:19 AM UTC 24 |
| Finished | Oct 03 06:31:23 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944348941 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.944348941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.3806519862 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 3210368719 ps |
| CPU time | 19.53 seconds |
| Started | Oct 03 06:31:11 AM UTC 24 |
| Finished | Oct 03 06:31:32 AM UTC 24 |
| Peak memory | 251968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806519862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3806519862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.1295325664 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1869005546 ps |
| CPU time | 22.34 seconds |
| Started | Oct 03 06:31:14 AM UTC 24 |
| Finished | Oct 03 06:31:38 AM UTC 24 |
| Peak memory | 253964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295325664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.1295325664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.2633252144 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 236717594 ps |
| CPU time | 9.08 seconds |
| Started | Oct 03 06:31:14 AM UTC 24 |
| Finished | Oct 03 06:31:24 AM UTC 24 |
| Peak memory | 252064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633252144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2633252144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.2774462957 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2389084654 ps |
| CPU time | 22.99 seconds |
| Started | Oct 03 06:31:14 AM UTC 24 |
| Finished | Oct 03 06:31:38 AM UTC 24 |
| Peak memory | 251896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774462957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2774462957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.1338371929 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 465923739 ps |
| CPU time | 13.21 seconds |
| Started | Oct 03 06:31:14 AM UTC 24 |
| Finished | Oct 03 06:31:28 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338371929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.1338371929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.570412326 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4394927916 ps |
| CPU time | 51.2 seconds |
| Started | Oct 03 06:31:14 AM UTC 24 |
| Finished | Oct 03 06:32:07 AM UTC 24 |
| Peak memory | 254152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570412326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.570412326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3287660185 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 629181757 ps |
| CPU time | 11.52 seconds |
| Started | Oct 03 06:31:14 AM UTC 24 |
| Finished | Oct 03 06:31:27 AM UTC 24 |
| Peak memory | 251892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287660185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3287660185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.2829865316 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 924881102 ps |
| CPU time | 9.19 seconds |
| Started | Oct 03 06:31:14 AM UTC 24 |
| Finished | Oct 03 06:31:24 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829865316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2829865316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.3221465030 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 528008079 ps |
| CPU time | 8.28 seconds |
| Started | Oct 03 06:31:09 AM UTC 24 |
| Finished | Oct 03 06:31:18 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221465030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3221465030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.2947736349 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1794560751 ps |
| CPU time | 14.36 seconds |
| Started | Oct 03 06:31:17 AM UTC 24 |
| Finished | Oct 03 06:31:33 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947736349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2947736349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.1536446637 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 283156975 ps |
| CPU time | 4.4 seconds |
| Started | Oct 03 06:40:39 AM UTC 24 |
| Finished | Oct 03 06:40:44 AM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536446637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1536446637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.780521074 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 284737417 ps |
| CPU time | 9.06 seconds |
| Started | Oct 03 06:40:39 AM UTC 24 |
| Finished | Oct 03 06:40:49 AM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780521074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.780521074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.3756763793 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 253355291 ps |
| CPU time | 5.17 seconds |
| Started | Oct 03 06:40:40 AM UTC 24 |
| Finished | Oct 03 06:40:47 AM UTC 24 |
| Peak memory | 251736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756763793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3756763793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.3976678985 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 229319349 ps |
| CPU time | 7.99 seconds |
| Started | Oct 03 06:40:40 AM UTC 24 |
| Finished | Oct 03 06:40:49 AM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976678985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.3976678985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.4017298275 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 190485473 ps |
| CPU time | 5.97 seconds |
| Started | Oct 03 06:40:43 AM UTC 24 |
| Finished | Oct 03 06:40:50 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017298275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.4017298275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.2106863704 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 4046362773 ps |
| CPU time | 25.49 seconds |
| Started | Oct 03 06:40:45 AM UTC 24 |
| Finished | Oct 03 06:41:12 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106863704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2106863704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.3211471282 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 17859439202 ps |
| CPU time | 134.2 seconds |
| Started | Oct 03 06:40:45 AM UTC 24 |
| Finished | Oct 03 06:43:02 AM UTC 24 |
| Peak memory | 270452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3211471282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 72.otp_ctrl_stress_all_with_rand_reset.3211471282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.3287102572 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 287504444 ps |
| CPU time | 4.15 seconds |
| Started | Oct 03 06:40:45 AM UTC 24 |
| Finished | Oct 03 06:40:50 AM UTC 24 |
| Peak memory | 251716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287102572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3287102572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.2471271947 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 135924312 ps |
| CPU time | 3.05 seconds |
| Started | Oct 03 06:40:46 AM UTC 24 |
| Finished | Oct 03 06:40:51 AM UTC 24 |
| Peak memory | 251588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471271947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2471271947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.1471238255 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 9501776563 ps |
| CPU time | 101.71 seconds |
| Started | Oct 03 06:40:49 AM UTC 24 |
| Finished | Oct 03 06:42:33 AM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1471238255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 73.otp_ctrl_stress_all_with_rand_reset.1471238255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.2283204033 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 314131978 ps |
| CPU time | 7.7 seconds |
| Started | Oct 03 06:40:49 AM UTC 24 |
| Finished | Oct 03 06:40:57 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283204033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2283204033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.1984945895 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 485435733 ps |
| CPU time | 5.34 seconds |
| Started | Oct 03 06:40:49 AM UTC 24 |
| Finished | Oct 03 06:40:55 AM UTC 24 |
| Peak memory | 251596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984945895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1984945895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1306055817 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 6141846351 ps |
| CPU time | 122.19 seconds |
| Started | Oct 03 06:40:49 AM UTC 24 |
| Finished | Oct 03 06:42:53 AM UTC 24 |
| Peak memory | 258196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1306055817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 74.otp_ctrl_stress_all_with_rand_reset.1306055817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.329810456 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 140576713 ps |
| CPU time | 5.17 seconds |
| Started | Oct 03 06:40:50 AM UTC 24 |
| Finished | Oct 03 06:40:56 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329810456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.329810456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.3902936785 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 279306428 ps |
| CPU time | 14.38 seconds |
| Started | Oct 03 06:40:50 AM UTC 24 |
| Finished | Oct 03 06:41:06 AM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902936785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3902936785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.3186119310 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 210649940 ps |
| CPU time | 5.88 seconds |
| Started | Oct 03 06:40:51 AM UTC 24 |
| Finished | Oct 03 06:40:57 AM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186119310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3186119310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.1752403318 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 196578243 ps |
| CPU time | 6.61 seconds |
| Started | Oct 03 06:40:52 AM UTC 24 |
| Finished | Oct 03 06:41:00 AM UTC 24 |
| Peak memory | 251852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752403318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1752403318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.447167241 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 124325559 ps |
| CPU time | 4.9 seconds |
| Started | Oct 03 06:40:52 AM UTC 24 |
| Finished | Oct 03 06:40:58 AM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447167241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.447167241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.1484258521 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 4230645746 ps |
| CPU time | 32.71 seconds |
| Started | Oct 03 06:40:53 AM UTC 24 |
| Finished | Oct 03 06:41:28 AM UTC 24 |
| Peak memory | 251832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484258521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1484258521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.148665042 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 181899172 ps |
| CPU time | 7.11 seconds |
| Started | Oct 03 06:40:56 AM UTC 24 |
| Finished | Oct 03 06:41:04 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148665042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.148665042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.21572030 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2041456787 ps |
| CPU time | 13.78 seconds |
| Started | Oct 03 06:40:56 AM UTC 24 |
| Finished | Oct 03 06:41:11 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21572030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.21572030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3202608794 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4115306711 ps |
| CPU time | 118.44 seconds |
| Started | Oct 03 06:40:57 AM UTC 24 |
| Finished | Oct 03 06:42:58 AM UTC 24 |
| Peak memory | 274676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3202608794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 78.otp_ctrl_stress_all_with_rand_reset.3202608794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.2310557351 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 126827715 ps |
| CPU time | 4.68 seconds |
| Started | Oct 03 06:40:59 AM UTC 24 |
| Finished | Oct 03 06:41:05 AM UTC 24 |
| Peak memory | 250556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310557351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2310557351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.1951786572 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2008242611 ps |
| CPU time | 10.34 seconds |
| Started | Oct 03 06:40:59 AM UTC 24 |
| Finished | Oct 03 06:41:10 AM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951786572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.1951786572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.4287830057 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 5508084947 ps |
| CPU time | 111.95 seconds |
| Started | Oct 03 06:40:59 AM UTC 24 |
| Finished | Oct 03 06:42:53 AM UTC 24 |
| Peak memory | 268552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4287830057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 79.otp_ctrl_stress_all_with_rand_reset.4287830057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.1462471332 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 135306284 ps |
| CPU time | 3.8 seconds |
| Started | Oct 03 06:31:38 AM UTC 24 |
| Finished | Oct 03 06:31:43 AM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462471332 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1462471332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.533566096 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3598569859 ps |
| CPU time | 35.62 seconds |
| Started | Oct 03 06:31:25 AM UTC 24 |
| Finished | Oct 03 06:32:02 AM UTC 24 |
| Peak memory | 254024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533566096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.533566096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.129998025 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 96457498 ps |
| CPU time | 4.15 seconds |
| Started | Oct 03 06:31:29 AM UTC 24 |
| Finished | Oct 03 06:31:34 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129998025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.129998025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.610286375 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1327556450 ps |
| CPU time | 35.4 seconds |
| Started | Oct 03 06:31:29 AM UTC 24 |
| Finished | Oct 03 06:32:06 AM UTC 24 |
| Peak memory | 255968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610286375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.610286375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.330736790 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 7937492309 ps |
| CPU time | 54.54 seconds |
| Started | Oct 03 06:31:27 AM UTC 24 |
| Finished | Oct 03 06:32:24 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330736790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.330736790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.3965964224 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 107392393 ps |
| CPU time | 5.32 seconds |
| Started | Oct 03 06:31:25 AM UTC 24 |
| Finished | Oct 03 06:31:31 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965964224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3965964224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.1775837285 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2875413115 ps |
| CPU time | 23.02 seconds |
| Started | Oct 03 06:31:25 AM UTC 24 |
| Finished | Oct 03 06:31:49 AM UTC 24 |
| Peak memory | 252084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775837285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.1775837285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.171068650 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1088245865 ps |
| CPU time | 17.84 seconds |
| Started | Oct 03 06:31:35 AM UTC 24 |
| Finished | Oct 03 06:31:54 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171068650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.171068650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.812140414 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 153950844 ps |
| CPU time | 5.78 seconds |
| Started | Oct 03 06:31:19 AM UTC 24 |
| Finished | Oct 03 06:31:26 AM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812140414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.812140414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.57730299 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2577199800 ps |
| CPU time | 32.13 seconds |
| Started | Oct 03 06:31:35 AM UTC 24 |
| Finished | Oct 03 06:32:08 AM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57730299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.57730299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.3384320964 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 1831926249 ps |
| CPU time | 6.22 seconds |
| Started | Oct 03 06:40:59 AM UTC 24 |
| Finished | Oct 03 06:41:06 AM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384320964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3384320964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.1860632260 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1237183332 ps |
| CPU time | 4.86 seconds |
| Started | Oct 03 06:41:00 AM UTC 24 |
| Finished | Oct 03 06:41:06 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860632260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.1860632260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.544545093 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 2597072251 ps |
| CPU time | 91.96 seconds |
| Started | Oct 03 06:41:06 AM UTC 24 |
| Finished | Oct 03 06:42:40 AM UTC 24 |
| Peak memory | 258192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=544545093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.544545093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.1720221170 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1561415702 ps |
| CPU time | 8.26 seconds |
| Started | Oct 03 06:41:06 AM UTC 24 |
| Finished | Oct 03 06:41:16 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720221170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1720221170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.3520157378 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 681333625 ps |
| CPU time | 12.01 seconds |
| Started | Oct 03 06:41:06 AM UTC 24 |
| Finished | Oct 03 06:41:19 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520157378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3520157378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.1041168175 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 161873347 ps |
| CPU time | 5.81 seconds |
| Started | Oct 03 06:41:06 AM UTC 24 |
| Finished | Oct 03 06:41:13 AM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041168175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1041168175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.1293553121 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 620891625 ps |
| CPU time | 5.82 seconds |
| Started | Oct 03 06:41:08 AM UTC 24 |
| Finished | Oct 03 06:41:15 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293553121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1293553121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.988731018 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1589775786 ps |
| CPU time | 7.95 seconds |
| Started | Oct 03 06:41:08 AM UTC 24 |
| Finished | Oct 03 06:41:17 AM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988731018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.988731018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.911441363 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 424039609 ps |
| CPU time | 16 seconds |
| Started | Oct 03 06:41:16 AM UTC 24 |
| Finished | Oct 03 06:41:33 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911441363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.911441363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.2950045817 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 15316754879 ps |
| CPU time | 110.3 seconds |
| Started | Oct 03 06:41:16 AM UTC 24 |
| Finished | Oct 03 06:43:09 AM UTC 24 |
| Peak memory | 268500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2950045817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 83.otp_ctrl_stress_all_with_rand_reset.2950045817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.230977590 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 428594820 ps |
| CPU time | 6.59 seconds |
| Started | Oct 03 06:41:16 AM UTC 24 |
| Finished | Oct 03 06:41:24 AM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230977590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.230977590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.3168418921 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 454537422 ps |
| CPU time | 12.24 seconds |
| Started | Oct 03 06:41:16 AM UTC 24 |
| Finished | Oct 03 06:41:30 AM UTC 24 |
| Peak memory | 251768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168418921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3168418921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1952815508 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 12252135018 ps |
| CPU time | 147.64 seconds |
| Started | Oct 03 06:41:16 AM UTC 24 |
| Finished | Oct 03 06:43:47 AM UTC 24 |
| Peak memory | 268500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1952815508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 84.otp_ctrl_stress_all_with_rand_reset.1952815508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.401991308 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 136613020 ps |
| CPU time | 5.55 seconds |
| Started | Oct 03 06:41:16 AM UTC 24 |
| Finished | Oct 03 06:41:23 AM UTC 24 |
| Peak memory | 251784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401991308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.401991308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.3948558628 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2415571945 ps |
| CPU time | 7.23 seconds |
| Started | Oct 03 06:41:16 AM UTC 24 |
| Finished | Oct 03 06:41:25 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948558628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3948558628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.1567091471 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 232786910 ps |
| CPU time | 6.19 seconds |
| Started | Oct 03 06:41:16 AM UTC 24 |
| Finished | Oct 03 06:41:24 AM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567091471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1567091471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.4174092162 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 647590818 ps |
| CPU time | 17.32 seconds |
| Started | Oct 03 06:41:18 AM UTC 24 |
| Finished | Oct 03 06:41:36 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174092162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.4174092162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.2685769203 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 156145350 ps |
| CPU time | 5.84 seconds |
| Started | Oct 03 06:41:18 AM UTC 24 |
| Finished | Oct 03 06:41:25 AM UTC 24 |
| Peak memory | 251712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685769203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2685769203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.3357993012 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 144075432 ps |
| CPU time | 4.96 seconds |
| Started | Oct 03 06:41:18 AM UTC 24 |
| Finished | Oct 03 06:41:24 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357993012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3357993012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1605212498 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1059452511 ps |
| CPU time | 49.53 seconds |
| Started | Oct 03 06:41:20 AM UTC 24 |
| Finished | Oct 03 06:42:11 AM UTC 24 |
| Peak memory | 258388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1605212498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 87.otp_ctrl_stress_all_with_rand_reset.1605212498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.29113692 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 148131762 ps |
| CPU time | 5.71 seconds |
| Started | Oct 03 06:41:26 AM UTC 24 |
| Finished | Oct 03 06:41:32 AM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29113692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.29113692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.2419912462 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3334554165 ps |
| CPU time | 24.24 seconds |
| Started | Oct 03 06:41:26 AM UTC 24 |
| Finished | Oct 03 06:41:51 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419912462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2419912462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.991492114 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 253546577 ps |
| CPU time | 6.88 seconds |
| Started | Oct 03 06:41:26 AM UTC 24 |
| Finished | Oct 03 06:41:34 AM UTC 24 |
| Peak memory | 251808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991492114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.991492114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.2034776875 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 728018405 ps |
| CPU time | 21.48 seconds |
| Started | Oct 03 06:41:26 AM UTC 24 |
| Finished | Oct 03 06:41:49 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034776875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.2034776875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.3521221091 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 160777382 ps |
| CPU time | 2.6 seconds |
| Started | Oct 03 06:32:07 AM UTC 24 |
| Finished | Oct 03 06:32:10 AM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521221091 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3521221091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.2310681593 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4035838362 ps |
| CPU time | 24.72 seconds |
| Started | Oct 03 06:31:44 AM UTC 24 |
| Finished | Oct 03 06:32:10 AM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310681593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2310681593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.2575299333 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 9370453332 ps |
| CPU time | 42.84 seconds |
| Started | Oct 03 06:31:57 AM UTC 24 |
| Finished | Oct 03 06:32:41 AM UTC 24 |
| Peak memory | 252000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575299333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2575299333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.53408613 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 603442270 ps |
| CPU time | 21.32 seconds |
| Started | Oct 03 06:31:56 AM UTC 24 |
| Finished | Oct 03 06:32:19 AM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53408613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.53408613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.4023770642 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 301097727 ps |
| CPU time | 6.57 seconds |
| Started | Oct 03 06:31:53 AM UTC 24 |
| Finished | Oct 03 06:32:00 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023770642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.4023770642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.2563876915 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 261918421 ps |
| CPU time | 10.14 seconds |
| Started | Oct 03 06:32:00 AM UTC 24 |
| Finished | Oct 03 06:32:11 AM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563876915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.2563876915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.829721524 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 806650962 ps |
| CPU time | 26.55 seconds |
| Started | Oct 03 06:32:00 AM UTC 24 |
| Finished | Oct 03 06:32:28 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829721524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.829721524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.1055823320 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 342585191 ps |
| CPU time | 7.91 seconds |
| Started | Oct 03 06:31:50 AM UTC 24 |
| Finished | Oct 03 06:31:59 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055823320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1055823320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.1331886395 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 442415040 ps |
| CPU time | 14.67 seconds |
| Started | Oct 03 06:32:01 AM UTC 24 |
| Finished | Oct 03 06:32:17 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331886395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1331886395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.2717859630 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 264713082 ps |
| CPU time | 12.32 seconds |
| Started | Oct 03 06:31:39 AM UTC 24 |
| Finished | Oct 03 06:31:52 AM UTC 24 |
| Peak memory | 251728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717859630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2717859630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.944905870 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 371349391 ps |
| CPU time | 5.24 seconds |
| Started | Oct 03 06:32:01 AM UTC 24 |
| Finished | Oct 03 06:32:07 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944905870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.944905870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.87517216 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2178662889 ps |
| CPU time | 5.18 seconds |
| Started | Oct 03 06:41:26 AM UTC 24 |
| Finished | Oct 03 06:41:32 AM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87517216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.87517216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.2228469514 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1022160100 ps |
| CPU time | 8.25 seconds |
| Started | Oct 03 06:41:27 AM UTC 24 |
| Finished | Oct 03 06:41:36 AM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228469514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2228469514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.1740173678 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2221807615 ps |
| CPU time | 82.35 seconds |
| Started | Oct 03 06:41:29 AM UTC 24 |
| Finished | Oct 03 06:42:53 AM UTC 24 |
| Peak memory | 268532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1740173678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 90.otp_ctrl_stress_all_with_rand_reset.1740173678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.3180946685 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 669929257 ps |
| CPU time | 5.8 seconds |
| Started | Oct 03 06:41:31 AM UTC 24 |
| Finished | Oct 03 06:41:38 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180946685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3180946685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.1752813317 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 485727512 ps |
| CPU time | 6.02 seconds |
| Started | Oct 03 06:41:31 AM UTC 24 |
| Finished | Oct 03 06:41:38 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752813317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1752813317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.604730362 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 215954216 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 06:41:33 AM UTC 24 |
| Finished | Oct 03 06:41:37 AM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604730362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.604730362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.2321737099 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 372300266 ps |
| CPU time | 12.09 seconds |
| Started | Oct 03 06:41:35 AM UTC 24 |
| Finished | Oct 03 06:41:48 AM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321737099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2321737099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.4100517749 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2306555290 ps |
| CPU time | 9.68 seconds |
| Started | Oct 03 06:41:35 AM UTC 24 |
| Finished | Oct 03 06:41:46 AM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100517749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.4100517749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.2853846538 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 823247438 ps |
| CPU time | 7.29 seconds |
| Started | Oct 03 06:41:35 AM UTC 24 |
| Finished | Oct 03 06:41:43 AM UTC 24 |
| Peak memory | 251780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853846538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2853846538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.3170860612 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 131776194 ps |
| CPU time | 4.85 seconds |
| Started | Oct 03 06:41:38 AM UTC 24 |
| Finished | Oct 03 06:41:44 AM UTC 24 |
| Peak memory | 251668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170860612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3170860612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.3370106966 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 277543883 ps |
| CPU time | 7.37 seconds |
| Started | Oct 03 06:41:42 AM UTC 24 |
| Finished | Oct 03 06:41:50 AM UTC 24 |
| Peak memory | 251792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370106966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3370106966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.463972171 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 524617755 ps |
| CPU time | 6.13 seconds |
| Started | Oct 03 06:41:42 AM UTC 24 |
| Finished | Oct 03 06:41:49 AM UTC 24 |
| Peak memory | 251660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463972171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.463972171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.2715237983 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 437206703 ps |
| CPU time | 7.61 seconds |
| Started | Oct 03 06:41:42 AM UTC 24 |
| Finished | Oct 03 06:41:50 AM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715237983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2715237983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.2014637600 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 132662427 ps |
| CPU time | 5.51 seconds |
| Started | Oct 03 06:41:42 AM UTC 24 |
| Finished | Oct 03 06:41:48 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014637600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2014637600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.3853411589 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 3722690499 ps |
| CPU time | 15.02 seconds |
| Started | Oct 03 06:41:44 AM UTC 24 |
| Finished | Oct 03 06:42:00 AM UTC 24 |
| Peak memory | 251836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853411589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3853411589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2082121896 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 19713989981 ps |
| CPU time | 96.8 seconds |
| Started | Oct 03 06:41:44 AM UTC 24 |
| Finished | Oct 03 06:43:23 AM UTC 24 |
| Peak memory | 258012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2082121896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 96.otp_ctrl_stress_all_with_rand_reset.2082121896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.2613966137 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 187600884 ps |
| CPU time | 5.37 seconds |
| Started | Oct 03 06:41:44 AM UTC 24 |
| Finished | Oct 03 06:41:51 AM UTC 24 |
| Peak memory | 251740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613966137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2613966137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.538355780 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 542437310 ps |
| CPU time | 15.22 seconds |
| Started | Oct 03 06:41:47 AM UTC 24 |
| Finished | Oct 03 06:42:03 AM UTC 24 |
| Peak memory | 251916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538355780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.538355780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.4174256912 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 8124584136 ps |
| CPU time | 110.06 seconds |
| Started | Oct 03 06:41:47 AM UTC 24 |
| Finished | Oct 03 06:43:39 AM UTC 24 |
| Peak memory | 258196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4174256912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 97.otp_ctrl_stress_all_with_rand_reset.4174256912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.645883816 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 146995529 ps |
| CPU time | 4.12 seconds |
| Started | Oct 03 06:41:47 AM UTC 24 |
| Finished | Oct 03 06:41:52 AM UTC 24 |
| Peak memory | 251732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645883816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.645883816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.4053577564 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1543361202 ps |
| CPU time | 8.17 seconds |
| Started | Oct 03 06:41:47 AM UTC 24 |
| Finished | Oct 03 06:41:56 AM UTC 24 |
| Peak memory | 251772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053577564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.4053577564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.2922230675 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 456649754 ps |
| CPU time | 7.42 seconds |
| Started | Oct 03 06:41:52 AM UTC 24 |
| Finished | Oct 03 06:42:01 AM UTC 24 |
| Peak memory | 251824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922230675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2922230675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.3453807530 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 377230798 ps |
| CPU time | 4.24 seconds |
| Started | Oct 03 06:41:52 AM UTC 24 |
| Finished | Oct 03 06:41:58 AM UTC 24 |
| Peak memory | 251776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453807530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3453807530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.2768228972 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 14503564487 ps |
| CPU time | 205.85 seconds |
| Started | Oct 03 06:41:53 AM UTC 24 |
| Finished | Oct 03 06:45:22 AM UTC 24 |
| Peak memory | 274400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2768228972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 99.otp_ctrl_stress_all_with_rand_reset.2768228972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest |
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