Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
otbn_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
otbn_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
otbn_req_during_lc_esc 2 0 2 100.00 100 1 1 0
otbn_req_during_otp_idle 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
otbn_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable otbn_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12892 1 T1 18 T4 81 T5 12
auto[1] 1050 1 T4 13 T6 6 T7 9



Summary for Variable otbn_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12919 1 T1 18 T4 84 T5 12
auto[1] 1023 1 T4 10 T6 8 T7 14



Summary for Variable otbn_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for otbn_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13906 1 T1 18 T4 94 T5 12
lc_esc_on 36 1 T141 1 T347 1 T341 1



Summary for Variable otbn_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2527 1 T1 3 T4 6 T5 3
auto[1] 11415 1 T1 15 T4 88 T5 9



Summary for Variable otbn_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12924 1 T1 18 T4 80 T5 12
auto[1] 1018 1 T4 14 T6 9 T7 13



Summary for Variable otbn_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13588 1 T1 18 T4 82 T5 12
auto[1] 354 1 T4 12 T6 2 T31 17

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