Testbench Group List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
1304 1399 93.21 1304 1399 93.21 1


Total groups in report: 38
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
otp_ctrl_env_pkg::otp_ctrl_env_cov::lci_err_code_cg 3 4 75.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg 5 6 83.33 69.44 1 100 1 1 64 64
otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg 76 90 84.44 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg 6 7 85.71 77.14 1 100 1 1 64 64
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 13 15 86.67 96.15 1 100 1 1 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1} 14 14 100.00 1 100 1 0 64 64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1} 14 14 100.00 1 100 1 0 64 64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1} 20 20 100.00 1 100 1 0 64 64
cip_base_pkg::resets_cg 4 4 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 14 14 100.00 96.43 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg 24 24 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg 2 2 100.00 59.38 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg 6 6 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg 10 10 100.00 88.75 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 98.53 1 100 1 1 64 64
tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg 12 12 100.00 1 100 1 0 64 64
tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg 12 12 100.00 1 100 1 0 64 64
tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg 14 14 100.00 1 100 1 0 64 64
tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg 14 14 100.00 1 100 1 0 64 64
tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg 12 12 100.00 1 100 1 0 64 64
tb.dut.u_otp_ctrl_cov_if::sram_0_req_condition_cg 12 12 100.00 1 100 1 0 64 64
tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg 12 12 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_csr_rd_after_alert_cg_wrap::csr_rd_after_alert_cg 6 6 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_access_secret2_cg 11 11 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg 8 8 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_env_cov::issue_checks_after_alert_cg 2 2 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg 8 8 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg 22 22 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_env_cov::req_dai_access_after_alert_cg 3 3 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg 14 14 100.00 1 100 1 0 64 64
otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg 14 14 100.00 100.00 1 100 1 1 64 64
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg 2 2 100.00 100.00 1 100 1 1 64 64
tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg 2 2 100.00 100.00 1 100 1 1 64 64
push_pull_agent_pkg::req_ack_cg 3 3 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%