Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.89 93.81 96.15 95.69 91.89 97.10 96.34 93.28


Total tests in report: 1318
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
70.84 70.84 89.00 89.00 78.86 78.86 61.97 61.97 53.94 53.94 83.75 83.75 89.37 89.37 38.96 38.96 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.3969361644
74.68 3.85 89.76 0.77 83.88 5.02 69.21 7.23 54.42 0.48 87.99 4.24 89.71 0.34 47.82 8.86 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.3081214303
77.39 2.70 90.22 0.46 85.07 1.19 73.13 3.92 58.47 4.06 88.95 0.95 90.05 0.34 55.83 8.01 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.3780169675
79.58 2.20 90.37 0.15 85.37 0.30 77.69 4.57 61.81 3.34 89.33 0.38 90.32 0.27 62.19 6.36 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.2078978544
81.72 2.14 90.73 0.36 88.97 3.60 79.45 1.76 62.29 0.48 90.76 1.43 90.93 0.61 68.91 6.72 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.1568631655
82.96 1.24 90.73 0.00 90.48 1.52 82.00 2.55 64.92 2.63 91.00 0.24 91.06 0.14 70.55 1.64 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.2206012731
83.99 1.03 90.76 0.03 90.78 0.30 83.22 1.22 66.11 1.19 91.19 0.19 91.13 0.07 74.77 4.22 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.4247062096
84.93 0.94 91.02 0.26 91.88 1.09 83.73 0.51 66.11 0.00 92.81 1.62 93.43 2.30 75.55 0.79 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.4199834987
85.82 0.89 91.22 0.20 92.07 0.20 83.84 0.11 70.88 4.77 93.19 0.38 93.70 0.27 75.84 0.29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.522296452
86.60 0.78 91.94 0.72 92.62 0.55 86.02 2.18 71.36 0.48 93.81 0.62 93.70 0.00 76.77 0.93 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2118361328
87.29 0.69 91.94 0.00 93.42 0.80 88.34 2.31 71.36 0.00 94.24 0.43 93.77 0.07 77.98 1.22 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.2193426230
87.90 0.61 92.04 0.10 93.71 0.30 89.68 1.35 72.08 0.72 94.47 0.24 93.77 0.00 79.56 1.57 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.3889671130
88.42 0.51 92.23 0.20 93.81 0.10 90.11 0.42 73.51 1.43 94.71 0.24 93.97 0.20 80.56 1.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.1157454580
88.83 0.41 92.35 0.11 93.86 0.05 90.58 0.47 74.70 1.19 94.85 0.14 93.97 0.00 81.49 0.93 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.455274909
89.19 0.36 92.36 0.02 94.11 0.25 90.58 0.00 74.70 0.00 94.90 0.05 93.97 0.00 83.70 2.22 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3299308206
89.54 0.35 92.46 0.10 94.21 0.10 90.58 0.00 76.61 1.91 95.14 0.24 93.97 0.00 83.77 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.1728714865
89.86 0.32 92.46 0.00 94.24 0.02 90.84 0.26 77.09 0.48 95.14 0.00 93.97 0.00 85.28 1.50 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.2754010898
90.14 0.28 92.53 0.07 94.29 0.05 90.88 0.04 78.76 1.67 95.28 0.14 93.97 0.00 85.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.2416333989
90.40 0.26 92.53 0.00 94.36 0.07 90.88 0.00 78.76 0.00 95.33 0.05 94.85 0.88 86.06 0.79 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.254530964
90.64 0.24 92.58 0.05 94.39 0.02 90.95 0.07 80.19 1.43 95.38 0.05 94.85 0.00 86.13 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.144202691
90.84 0.21 92.69 0.11 94.41 0.02 91.21 0.27 80.67 0.48 95.52 0.14 94.99 0.14 86.42 0.29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.1141337025
91.04 0.19 92.69 0.00 94.41 0.00 91.98 0.77 80.67 0.00 95.52 0.00 94.99 0.00 86.99 0.57 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.3369656590
91.22 0.18 92.69 0.00 94.43 0.02 92.73 0.75 80.67 0.00 95.52 0.00 94.99 0.00 87.49 0.50 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1468198801
91.38 0.16 92.74 0.05 94.46 0.02 92.97 0.24 81.38 0.72 95.57 0.05 94.99 0.00 87.56 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.2493735074
91.54 0.16 92.74 0.00 94.46 0.00 92.97 0.00 81.86 0.48 95.57 0.00 95.33 0.34 87.85 0.29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.626761526
91.69 0.15 92.74 0.00 94.48 0.02 93.24 0.27 82.34 0.48 95.57 0.00 95.33 0.00 88.13 0.29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.3450788864
91.84 0.15 92.81 0.07 94.51 0.02 93.24 0.00 83.05 0.72 95.66 0.10 95.33 0.00 88.28 0.14 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.1948074613
91.98 0.14 92.81 0.00 94.51 0.00 93.64 0.40 83.29 0.24 95.66 0.00 95.40 0.07 88.56 0.29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.2394637618
92.10 0.12 92.85 0.05 94.56 0.05 93.67 0.03 83.77 0.48 95.76 0.10 95.46 0.07 88.63 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.3979053799
92.22 0.11 92.90 0.05 94.58 0.02 93.75 0.08 84.25 0.48 95.86 0.10 95.53 0.07 88.63 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.3318273084
92.33 0.11 92.95 0.05 94.61 0.02 93.86 0.11 84.73 0.48 95.90 0.05 95.53 0.00 88.71 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.3688448843
92.44 0.11 92.95 0.00 94.63 0.02 93.86 0.00 84.73 0.00 95.90 0.00 96.21 0.68 88.78 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3569300860
92.54 0.10 93.00 0.05 94.66 0.02 93.92 0.06 85.20 0.48 95.95 0.05 96.21 0.00 88.85 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.688029414
92.65 0.10 93.18 0.18 94.93 0.27 93.98 0.06 85.20 0.00 95.95 0.00 96.21 0.00 89.06 0.21 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.576581440
92.75 0.10 93.23 0.05 94.96 0.02 93.98 0.00 85.68 0.48 96.05 0.10 96.21 0.00 89.14 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.1246261579
92.84 0.10 93.28 0.05 94.98 0.02 93.98 0.00 86.16 0.48 96.09 0.05 96.21 0.00 89.21 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.2285850389
92.94 0.09 93.35 0.07 95.01 0.02 93.98 0.00 86.63 0.48 96.19 0.10 96.21 0.00 89.21 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.3760851024
93.03 0.09 93.39 0.05 95.01 0.00 94.02 0.04 87.11 0.48 96.24 0.05 96.21 0.00 89.21 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.2299804438
93.11 0.09 93.43 0.03 95.03 0.02 94.03 0.01 87.59 0.48 96.28 0.05 96.21 0.00 89.21 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.4241764853
93.20 0.08 93.43 0.00 95.06 0.02 94.14 0.11 87.83 0.24 96.28 0.00 96.21 0.00 89.42 0.21 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.2918523915
93.28 0.08 93.43 0.00 95.11 0.05 94.14 0.00 88.07 0.24 96.28 0.00 96.21 0.00 89.71 0.29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3220187691
93.36 0.08 93.46 0.03 95.11 0.00 94.14 0.00 88.54 0.48 96.33 0.05 96.21 0.00 89.71 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.1936138336
93.43 0.08 93.46 0.00 95.13 0.02 94.42 0.28 88.54 0.00 96.57 0.24 96.21 0.00 89.71 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3770123960
93.51 0.07 93.46 0.00 95.13 0.00 94.42 0.00 88.78 0.24 96.57 0.00 96.21 0.00 89.99 0.29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.3578475514
93.58 0.07 93.46 0.00 95.13 0.00 94.42 0.00 89.26 0.48 96.57 0.00 96.21 0.00 89.99 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.524971248
93.64 0.07 93.46 0.00 95.16 0.02 94.81 0.38 89.26 0.00 96.62 0.05 96.21 0.00 89.99 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.914818381
93.70 0.06 93.51 0.05 95.20 0.05 94.81 0.00 89.50 0.24 96.71 0.10 96.21 0.00 89.99 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.1817103808
93.77 0.06 93.51 0.00 95.20 0.00 94.81 0.00 89.50 0.00 96.71 0.00 96.21 0.00 90.42 0.43 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2306043857
93.83 0.06 93.53 0.02 95.35 0.15 94.81 0.00 89.50 0.00 96.76 0.05 96.21 0.00 90.64 0.21 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.2504348681
93.88 0.06 93.53 0.00 95.38 0.02 94.83 0.02 89.50 0.00 96.76 0.00 96.21 0.00 90.99 0.36 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.523704401
93.94 0.06 93.53 0.00 95.38 0.00 95.09 0.26 89.50 0.00 96.76 0.00 96.21 0.00 91.14 0.14 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.2582516245
94.00 0.06 93.54 0.02 95.40 0.02 95.09 0.00 89.74 0.24 96.81 0.05 96.21 0.00 91.21 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.3752616532
94.04 0.04 93.54 0.00 95.40 0.00 95.10 0.01 89.98 0.24 96.81 0.00 96.21 0.00 91.28 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.3002508422
94.09 0.04 93.54 0.00 95.40 0.00 95.10 0.00 90.21 0.24 96.81 0.00 96.21 0.00 91.35 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.4110466646
94.13 0.04 93.54 0.00 95.40 0.00 95.10 0.00 90.45 0.24 96.81 0.00 96.21 0.00 91.42 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.1356239231
94.18 0.04 93.54 0.00 95.40 0.00 95.10 0.00 90.69 0.24 96.81 0.00 96.21 0.00 91.49 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.456567641
94.22 0.04 93.54 0.00 95.40 0.00 95.10 0.00 90.69 0.00 96.81 0.00 96.21 0.00 91.78 0.29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2607922669
94.26 0.04 93.54 0.00 95.40 0.00 95.12 0.02 90.93 0.24 96.81 0.00 96.21 0.00 91.78 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.2014507565
94.29 0.03 93.54 0.00 95.40 0.00 95.12 0.00 91.17 0.24 96.81 0.00 96.21 0.00 91.78 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.296948127
94.32 0.03 93.54 0.00 95.40 0.00 95.12 0.00 91.41 0.24 96.81 0.00 96.21 0.00 91.78 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.2302788459
94.36 0.03 93.54 0.00 95.40 0.00 95.12 0.00 91.65 0.24 96.81 0.00 96.21 0.00 91.78 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.1014687493
94.39 0.03 93.54 0.00 95.40 0.00 95.12 0.00 91.89 0.24 96.81 0.00 96.21 0.00 91.78 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.3594271047
94.42 0.03 93.54 0.00 95.40 0.00 95.13 0.02 91.89 0.00 96.81 0.00 96.21 0.00 91.99 0.21 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.2583224032
94.46 0.03 93.54 0.00 95.40 0.00 95.14 0.01 91.89 0.00 96.81 0.00 96.21 0.00 92.21 0.21 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.548513094
94.49 0.03 93.54 0.00 95.40 0.00 95.15 0.01 91.89 0.00 96.81 0.00 96.21 0.00 92.42 0.21 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.2050641725
94.51 0.03 93.54 0.00 95.40 0.00 95.26 0.11 91.89 0.00 96.81 0.00 96.21 0.00 92.49 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.3692995867
94.54 0.02 93.56 0.02 95.43 0.02 95.26 0.00 91.89 0.00 96.86 0.05 96.21 0.00 92.57 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.134936914
94.56 0.02 93.57 0.02 95.45 0.02 95.26 0.00 91.89 0.00 96.90 0.05 96.21 0.00 92.64 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.3906686453
94.58 0.02 93.57 0.00 95.45 0.00 95.26 0.00 91.89 0.00 96.90 0.00 96.21 0.00 92.78 0.14 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.1563701093
94.60 0.02 93.57 0.00 95.45 0.00 95.26 0.00 91.89 0.00 96.90 0.00 96.21 0.00 92.92 0.14 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.3933220727
94.62 0.02 93.57 0.00 95.45 0.00 95.26 0.00 91.89 0.00 96.90 0.00 96.34 0.14 92.92 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.734106972
94.64 0.02 93.57 0.00 95.45 0.00 95.36 0.11 91.89 0.00 96.90 0.00 96.34 0.00 92.92 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.507072494
94.65 0.01 93.62 0.05 95.45 0.00 95.37 0.01 91.89 0.00 96.95 0.05 96.34 0.00 92.92 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.2493942858
94.66 0.01 93.67 0.05 95.45 0.00 95.37 0.00 91.89 0.00 97.00 0.05 96.34 0.00 92.92 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.812580261
94.68 0.01 93.67 0.00 95.48 0.02 95.37 0.00 91.89 0.00 97.00 0.00 96.34 0.00 92.99 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2654358706
94.69 0.01 93.69 0.02 95.50 0.02 95.37 0.00 91.89 0.00 97.05 0.05 96.34 0.00 92.99 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.590728226
94.70 0.01 93.69 0.00 95.50 0.00 95.39 0.02 91.89 0.00 97.05 0.00 96.34 0.00 93.07 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.1661516649
94.72 0.01 93.69 0.00 95.50 0.00 95.40 0.01 91.89 0.00 97.05 0.00 96.34 0.00 93.14 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.728443881
94.73 0.01 93.69 0.00 95.50 0.00 95.41 0.01 91.89 0.00 97.05 0.00 96.34 0.00 93.21 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.1010156864
94.74 0.01 93.72 0.03 95.50 0.00 95.41 0.00 91.89 0.00 97.09 0.05 96.34 0.00 93.21 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.2896015654
94.75 0.01 93.75 0.03 95.50 0.00 95.41 0.00 91.89 0.00 97.14 0.05 96.34 0.00 93.21 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.1507929706
94.76 0.01 93.79 0.03 95.50 0.00 95.41 0.00 91.89 0.00 97.19 0.05 96.34 0.00 93.21 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.3622397877
94.77 0.01 93.79 0.00 95.50 0.00 95.49 0.08 91.89 0.00 97.19 0.00 96.34 0.00 93.21 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.3288943436
94.78 0.01 93.79 0.00 95.50 0.00 95.49 0.00 91.89 0.00 97.19 0.00 96.34 0.00 93.28 0.07 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2361480225
94.79 0.01 93.79 0.00 95.50 0.00 95.54 0.05 91.89 0.00 97.19 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.1435676768
94.80 0.01 93.79 0.00 95.50 0.00 95.54 0.00 91.89 0.00 97.24 0.05 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.2040067212
94.80 0.01 93.79 0.00 95.50 0.00 95.59 0.04 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.2450819700
94.81 0.01 93.79 0.00 95.50 0.00 95.62 0.03 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1453539398
94.81 0.01 93.79 0.00 95.53 0.02 95.62 0.00 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2820661968
94.82 0.01 93.79 0.00 95.55 0.02 95.62 0.00 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.3318512195
94.82 0.01 93.79 0.00 95.55 0.00 95.64 0.02 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.957857520
94.82 0.01 93.79 0.00 95.55 0.00 95.65 0.01 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.1269839455
94.82 0.01 93.79 0.00 95.55 0.00 95.67 0.01 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.1288852204
94.82 0.01 93.79 0.00 95.55 0.00 95.68 0.01 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.3052144840
94.82 0.01 93.79 0.00 95.55 0.00 95.68 0.01 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.1307490682
94.82 0.01 93.79 0.00 95.55 0.00 95.69 0.01 91.89 0.00 97.24 0.00 96.34 0.00 93.28 0.00 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.802658142

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1255076202
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1146451742
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2213655702
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2179749933
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1532609237
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3778042900
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4211570675
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1851141003
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4030063762
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1074832571
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2290677472
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.501805913
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3990385358
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.2069978683
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4025183025
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4268151310
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2230849170
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3035337271
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2787160511
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1636521852
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.3916977142
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2935692377
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3712676762
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1261253236
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2669847944
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3072730268
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.2795564675
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1719075985
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4225921463
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4263374648
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.747455482
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4192225275
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3277271982
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2697781097
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.12853153
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3891494869
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.325489807
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1534073782
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.2674841990
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3541049533
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.4215431301
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4119524843
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1545411968
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3198527519
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.446724063
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.4062902864
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1420565498
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3091693019
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4189903515
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.419582899
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.833156297
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3748413334
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.364028173
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3873105023
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3885250975
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3471694487
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.117123234
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3903382276
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.549741156
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2475395380
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.841434136
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.732789481
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1513433100
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.623920543
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1872840269
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.120668044
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2068201461
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.495154198
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.757043490
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.476224606
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2166682976
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3568695949
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3300219334
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.265158479
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1731490123
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.862658299
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2633616265
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1883733316
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3715419005
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1816519949
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1251361030
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.4128567688
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1889650961
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.1239591618
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2902439695
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3405555247
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3442856103
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3817557727
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.940844914
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.3488594594
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.3368840069
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3655755188
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.3654621106
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.1866212786
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.2210083633
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1464445980
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.2034349509
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.3874917429
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3513842527
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2139212680
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2736245173
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2128046504
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2279253190
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.715993489
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.4272614552
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.850801355
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2840963785
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3729889700
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1120763568
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.326987264
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1216702483
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2599450847
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.848346243
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.2609084348
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.1226457745
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.2190704558
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.195902679
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.3448091772
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1994368864
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2897851438
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2600207970
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1210284834
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1749169219
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.972950091
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.668111220
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1415047612
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2849372198
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1046289036
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/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.3152542179
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1407630960
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.1886953483
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.1902207756
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3666117749
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.1395955454
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.297637111
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.69444039
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.3518284037
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.467280496
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.429020731
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.1194729060
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.3379021776
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.500966755
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.56420076
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.4085045664
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.555960414
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.3257886595
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.307902325
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.531584426
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.494644255
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1152889154
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.4126049140
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.50185831
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3899683662
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.3983623919
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.1785941121
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3001393752
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.2546703580
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.620866716
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.1848493202
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.3323135213
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.3105740484
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.419302178
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.1820091629
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.2392520809
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.2098385710
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3644164915
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.2738584952
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.3790617586
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.3541488398
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.2292825073
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.2426092005
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.2337381157
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1645129350
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.3574142944
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.1454131258
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2070051016
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.1204446198
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.2861204416
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.2647003319
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.1710810075
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1243367884
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.3787007197
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.2137593875
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.663295381
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.1819040
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3687963709
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.2760635290
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.2769049874
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1815118846
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.3460724368
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.2728688292
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.426919371
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.1196923791
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.639587539
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.77759094



Total test records in report: 1318
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.77457133 Feb 09 04:13:33 AM UTC 25 Feb 09 04:13:47 AM UTC 25 230360625 ps
T2 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.2040067212 Feb 09 04:11:39 AM UTC 25 Feb 09 04:11:43 AM UTC 25 737252867 ps
T3 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.4241764853 Feb 09 04:11:40 AM UTC 25 Feb 09 04:11:48 AM UTC 25 1463775533 ps
T4 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.3243031740 Feb 09 04:11:40 AM UTC 25 Feb 09 04:11:51 AM UTC 25 571660309 ps
T10 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.576581440 Feb 09 04:11:49 AM UTC 25 Feb 09 04:11:52 AM UTC 25 52583885 ps
T5 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.3879644639 Feb 09 04:11:42 AM UTC 25 Feb 09 04:11:54 AM UTC 25 1040669997 ps
T6 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.3920141150 Feb 09 04:11:42 AM UTC 25 Feb 09 04:11:55 AM UTC 25 508683019 ps
T11 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.3969361644 Feb 09 04:11:40 AM UTC 25 Feb 09 04:11:55 AM UTC 25 831706417 ps
T12 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.2206012731 Feb 09 04:11:41 AM UTC 25 Feb 09 04:11:55 AM UTC 25 564988782 ps
T13 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.2104768277 Feb 09 04:11:40 AM UTC 25 Feb 09 04:11:59 AM UTC 25 2817601823 ps
T99 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.3369656590 Feb 09 04:11:41 AM UTC 25 Feb 09 04:12:00 AM UTC 25 509107097 ps
T100 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.2973872616 Feb 09 04:11:41 AM UTC 25 Feb 09 04:12:00 AM UTC 25 1367023539 ps
T131 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.2917264224 Feb 09 04:11:40 AM UTC 25 Feb 09 04:12:01 AM UTC 25 6939130359 ps
T40 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.2493735074 Feb 09 04:11:53 AM UTC 25 Feb 09 04:12:02 AM UTC 25 500173598 ps
T132 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.1726825469 Feb 09 04:11:57 AM UTC 25 Feb 09 04:12:04 AM UTC 25 324613915 ps
T103 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.1923932026 Feb 09 04:11:56 AM UTC 25 Feb 09 04:12:06 AM UTC 25 359124023 ps
T133 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.4019182897 Feb 09 04:12:01 AM UTC 25 Feb 09 04:12:08 AM UTC 25 257787545 ps
T134 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.1806196909 Feb 09 04:11:52 AM UTC 25 Feb 09 04:12:09 AM UTC 25 5103130646 ps
T135 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.1961878789 Feb 09 04:12:02 AM UTC 25 Feb 09 04:12:10 AM UTC 25 156023062 ps
T97 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.3780169675 Feb 09 04:11:41 AM UTC 25 Feb 09 04:12:11 AM UTC 25 1019068921 ps
T17 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.1434838460 Feb 09 04:12:08 AM UTC 25 Feb 09 04:12:13 AM UTC 25 301594218 ps
T94 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.4090597726 Feb 09 04:11:41 AM UTC 25 Feb 09 04:12:16 AM UTC 25 8860900978 ps
T95 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.1362397603 Feb 09 04:11:56 AM UTC 25 Feb 09 04:12:16 AM UTC 25 1119826950 ps
T101 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.3622397877 Feb 09 04:12:10 AM UTC 25 Feb 09 04:12:17 AM UTC 25 97649885 ps
T7 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.4198120878 Feb 09 04:11:58 AM UTC 25 Feb 09 04:12:17 AM UTC 25 936973823 ps
T18 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.1642310420 Feb 09 04:12:03 AM UTC 25 Feb 09 04:12:18 AM UTC 25 304757593 ps
T104 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.612966852 Feb 09 04:12:10 AM UTC 25 Feb 09 04:12:18 AM UTC 25 201020962 ps
T96 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.2193426230 Feb 09 04:11:40 AM UTC 25 Feb 09 04:12:19 AM UTC 25 1679951979 ps
T130 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.3749672448 Feb 09 04:11:42 AM UTC 25 Feb 09 04:12:20 AM UTC 25 833001503 ps
T124 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.1269839455 Feb 09 04:11:57 AM UTC 25 Feb 09 04:12:23 AM UTC 25 13500518996 ps
T98 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.4148231948 Feb 09 04:12:19 AM UTC 25 Feb 09 04:12:24 AM UTC 25 376113207 ps
T230 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.2716388121 Feb 09 04:12:25 AM UTC 25 Feb 09 04:12:30 AM UTC 25 191519229 ps
T231 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.1751850113 Feb 09 04:12:19 AM UTC 25 Feb 09 04:12:31 AM UTC 25 691743397 ps
T51 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.455274909 Feb 09 04:12:01 AM UTC 25 Feb 09 04:12:32 AM UTC 25 13574035067 ps
T152 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.3121896771 Feb 09 04:12:19 AM UTC 25 Feb 09 04:12:33 AM UTC 25 561718797 ps
T266 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.914818381 Feb 09 04:12:09 AM UTC 25 Feb 09 04:12:34 AM UTC 25 7768396444 ps
T125 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.1435676768 Feb 09 04:12:12 AM UTC 25 Feb 09 04:12:38 AM UTC 25 2182109122 ps
T53 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3182610151 Feb 09 04:12:32 AM UTC 25 Feb 09 04:12:40 AM UTC 25 120044980 ps
T180 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.3162399300 Feb 09 04:12:19 AM UTC 25 Feb 09 04:12:41 AM UTC 25 1675168924 ps
T509 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.760905444 Feb 09 04:12:35 AM UTC 25 Feb 09 04:12:43 AM UTC 25 245879904 ps
T126 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.966567859 Feb 09 04:12:19 AM UTC 25 Feb 09 04:12:46 AM UTC 25 1780792859 ps
T127 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.1585437377 Feb 09 04:12:01 AM UTC 25 Feb 09 04:12:48 AM UTC 25 1488096426 ps
T238 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.2226661064 Feb 09 04:12:40 AM UTC 25 Feb 09 04:12:48 AM UTC 25 3706584829 ps
T141 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.2767792686 Feb 09 04:12:42 AM UTC 25 Feb 09 04:12:55 AM UTC 25 331724001 ps
T265 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.1146075033 Feb 09 04:12:13 AM UTC 25 Feb 09 04:12:55 AM UTC 25 1710279924 ps
T301 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.2863889449 Feb 09 04:12:30 AM UTC 25 Feb 09 04:12:56 AM UTC 25 6528072227 ps
T510 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.4116754665 Feb 09 04:12:57 AM UTC 25 Feb 09 04:13:01 AM UTC 25 145301197 ps
T128 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.1360043595 Feb 09 04:12:16 AM UTC 25 Feb 09 04:13:03 AM UTC 25 1481907137 ps
T129 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.4078816930 Feb 09 04:12:35 AM UTC 25 Feb 09 04:13:03 AM UTC 25 1522482133 ps
T19 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.3704639778 Feb 09 04:12:19 AM UTC 25 Feb 09 04:13:05 AM UTC 25 5006173751 ps
T511 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.1957730903 Feb 09 04:12:57 AM UTC 25 Feb 09 04:13:09 AM UTC 25 296255420 ps
T185 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.2636854516 Feb 09 04:13:02 AM UTC 25 Feb 09 04:13:10 AM UTC 25 523710306 ps
T232 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.4131488780 Feb 09 04:12:49 AM UTC 25 Feb 09 04:13:13 AM UTC 25 4476146289 ps
T107 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.2078978544 Feb 09 04:12:05 AM UTC 25 Feb 09 04:13:14 AM UTC 25 22286032434 ps
T142 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.1432497022 Feb 09 04:12:34 AM UTC 25 Feb 09 04:13:16 AM UTC 25 2119802561 ps
T233 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.2164510541 Feb 09 04:13:07 AM UTC 25 Feb 09 04:13:18 AM UTC 25 270243058 ps
T234 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.2727431262 Feb 09 04:13:05 AM UTC 25 Feb 09 04:13:21 AM UTC 25 493705079 ps
T177 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.1157454580 Feb 09 04:12:43 AM UTC 25 Feb 09 04:13:24 AM UTC 25 1008868050 ps
T181 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.2865004542 Feb 09 04:13:11 AM UTC 25 Feb 09 04:13:25 AM UTC 25 868557037 ps
T235 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.1511619582 Feb 09 04:13:16 AM UTC 25 Feb 09 04:13:27 AM UTC 25 183692081 ps
T182 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.352590254 Feb 09 04:13:16 AM UTC 25 Feb 09 04:13:28 AM UTC 25 2037693976 ps
T255 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.1863170057 Feb 09 04:12:54 AM UTC 25 Feb 09 04:13:29 AM UTC 25 7048429632 ps
T8 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.1461328009 Feb 09 04:12:41 AM UTC 25 Feb 09 04:13:30 AM UTC 25 4837256088 ps
T256 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.2503775891 Feb 09 04:13:26 AM UTC 25 Feb 09 04:13:30 AM UTC 25 576515387 ps
T149 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2118361328 Feb 09 04:12:49 AM UTC 25 Feb 09 04:13:30 AM UTC 25 24584136951 ps
T236 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.1063072155 Feb 09 04:13:16 AM UTC 25 Feb 09 04:13:35 AM UTC 25 6311303247 ps
T102 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.4046854792 Feb 09 04:13:28 AM UTC 25 Feb 09 04:13:36 AM UTC 25 379660849 ps
T48 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1785924492 Feb 09 04:13:14 AM UTC 25 Feb 09 04:13:38 AM UTC 25 1332825401 ps
T417 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.1908687709 Feb 09 04:13:28 AM UTC 25 Feb 09 04:13:41 AM UTC 25 560433706 ps
T512 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.3903213159 Feb 09 04:13:36 AM UTC 25 Feb 09 04:13:44 AM UTC 25 266130475 ps
T143 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.1136658816 Feb 09 04:13:04 AM UTC 25 Feb 09 04:13:50 AM UTC 25 2164279944 ps
T150 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.3096529182 Feb 09 04:13:30 AM UTC 25 Feb 09 04:13:51 AM UTC 25 1217610178 ps
T237 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.3876354999 Feb 09 04:13:17 AM UTC 25 Feb 09 04:13:51 AM UTC 25 1096729318 ps
T257 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.2581927695 Feb 09 04:13:33 AM UTC 25 Feb 09 04:13:52 AM UTC 25 1943317670 ps
T447 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.3366401859 Feb 09 04:13:45 AM UTC 25 Feb 09 04:13:53 AM UTC 25 274053589 ps
T456 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.211302541 Feb 09 04:13:33 AM UTC 25 Feb 09 04:13:54 AM UTC 25 749807973 ps
T415 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.2450819700 Feb 09 04:12:47 AM UTC 25 Feb 09 04:13:57 AM UTC 25 11322642533 ps
T513 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.1228714771 Feb 09 04:13:54 AM UTC 25 Feb 09 04:13:58 AM UTC 25 215662449 ps
T186 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.1122402784 Feb 09 04:13:54 AM UTC 25 Feb 09 04:13:59 AM UTC 25 215497211 ps
T258 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.2213461529 Feb 09 04:13:09 AM UTC 25 Feb 09 04:13:59 AM UTC 25 1606911868 ps
T463 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.1208092067 Feb 09 04:13:42 AM UTC 25 Feb 09 04:14:00 AM UTC 25 4853564502 ps
T9 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.2514476251 Feb 09 04:13:36 AM UTC 25 Feb 09 04:14:02 AM UTC 25 2901481133 ps
T162 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.3180072427 Feb 09 04:13:59 AM UTC 25 Feb 09 04:14:07 AM UTC 25 196823870 ps
T514 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.1560931674 Feb 09 04:14:01 AM UTC 25 Feb 09 04:14:08 AM UTC 25 148962684 ps
T462 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.1095424396 Feb 09 04:13:55 AM UTC 25 Feb 09 04:14:11 AM UTC 25 1713532528 ps
T300 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.82999547 Feb 09 04:13:54 AM UTC 25 Feb 09 04:14:14 AM UTC 25 4687116216 ps
T418 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.4283267955 Feb 09 04:14:06 AM UTC 25 Feb 09 04:14:17 AM UTC 25 2282924854 ps
T188 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.1546845504 Feb 09 04:14:01 AM UTC 25 Feb 09 04:14:18 AM UTC 25 1417622471 ps
T200 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.3472763508 Feb 09 04:13:40 AM UTC 25 Feb 09 04:14:18 AM UTC 25 1695851230 ps
T515 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.396199278 Feb 09 04:14:15 AM UTC 25 Feb 09 04:14:18 AM UTC 25 183040191 ps
T317 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.327105646 Feb 09 04:14:07 AM UTC 25 Feb 09 04:14:19 AM UTC 25 584448888 ps
T516 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.421338229 Feb 09 04:14:16 AM UTC 25 Feb 09 04:14:22 AM UTC 25 184735464 ps
T106 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.4051000384 Feb 09 04:14:01 AM UTC 25 Feb 09 04:14:23 AM UTC 25 1716647557 ps
T316 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.1780230085 Feb 09 04:13:47 AM UTC 25 Feb 09 04:14:25 AM UTC 25 5981870690 ps
T54 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.144202691 Feb 09 04:14:19 AM UTC 25 Feb 09 04:14:27 AM UTC 25 184331959 ps
T517 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3575678910 Feb 09 04:14:20 AM UTC 25 Feb 09 04:14:28 AM UTC 25 303000400 ps
T264 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.681019945 Feb 09 04:14:01 AM UTC 25 Feb 09 04:14:28 AM UTC 25 994608569 ps
T518 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.51794015 Feb 09 04:14:24 AM UTC 25 Feb 09 04:14:32 AM UTC 25 385541084 ps
T281 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.2061214364 Feb 09 04:14:03 AM UTC 25 Feb 09 04:14:33 AM UTC 25 3926241277 ps
T295 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.2453863842 Feb 09 04:13:59 AM UTC 25 Feb 09 04:14:34 AM UTC 25 740177995 ps
T299 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.2040542605 Feb 09 04:14:27 AM UTC 25 Feb 09 04:14:34 AM UTC 25 170471432 ps
T416 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.892769891 Feb 09 04:14:26 AM UTC 25 Feb 09 04:14:35 AM UTC 25 497927618 ps
T519 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.2199371481 Feb 09 04:14:27 AM UTC 25 Feb 09 04:14:37 AM UTC 25 539646596 ps
T520 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.3973960464 Feb 09 04:14:35 AM UTC 25 Feb 09 04:14:39 AM UTC 25 221062082 ps
T521 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.1025019296 Feb 09 04:15:57 AM UTC 25 Feb 09 04:16:04 AM UTC 25 108102438 ps
T43 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.2416333989 Feb 09 04:14:35 AM UTC 25 Feb 09 04:14:41 AM UTC 25 196339145 ps
T259 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.3177328575 Feb 09 04:14:29 AM UTC 25 Feb 09 04:14:42 AM UTC 25 753123346 ps
T260 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.3081214303 Feb 09 04:11:45 AM UTC 25 Feb 09 04:14:42 AM UTC 25 21471357393 ps
T522 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.924797162 Feb 09 04:14:35 AM UTC 25 Feb 09 04:14:42 AM UTC 25 1918703166 ps
T460 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.1487535234 Feb 09 04:14:20 AM UTC 25 Feb 09 04:14:43 AM UTC 25 2171055833 ps
T458 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.3973946961 Feb 09 04:14:19 AM UTC 25 Feb 09 04:14:48 AM UTC 25 926269700 ps
T151 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.571124556 Feb 09 04:14:19 AM UTC 25 Feb 09 04:14:49 AM UTC 25 3687510495 ps
T523 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.2208796400 Feb 09 04:14:37 AM UTC 25 Feb 09 04:14:50 AM UTC 25 458202346 ps
T524 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.278455610 Feb 09 04:14:46 AM UTC 25 Feb 09 04:14:53 AM UTC 25 251170779 ps
T27 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.4199834987 Feb 09 04:11:47 AM UTC 25 Feb 09 04:14:55 AM UTC 25 10250508313 ps
T269 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.1470820367 Feb 09 04:14:54 AM UTC 25 Feb 09 04:14:58 AM UTC 25 138747211 ps
T270 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.3035975124 Feb 09 04:14:51 AM UTC 25 Feb 09 04:14:58 AM UTC 25 258761230 ps
T271 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.1063901944 Feb 09 04:14:36 AM UTC 25 Feb 09 04:14:58 AM UTC 25 932704749 ps
T272 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.2714376252 Feb 09 04:14:46 AM UTC 25 Feb 09 04:15:01 AM UTC 25 753715964 ps
T273 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.2738584952 Feb 09 04:14:56 AM UTC 25 Feb 09 04:15:01 AM UTC 25 424112531 ps
T274 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.3900578197 Feb 09 04:14:22 AM UTC 25 Feb 09 04:15:02 AM UTC 25 1872488269 ps
T275 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.3630880045 Feb 09 04:14:46 AM UTC 25 Feb 09 04:15:03 AM UTC 25 543639364 ps
T276 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.2760138244 Feb 09 04:14:50 AM UTC 25 Feb 09 04:15:03 AM UTC 25 2217084082 ps
T28 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3770123960 Feb 09 04:12:07 AM UTC 25 Feb 09 04:15:03 AM UTC 25 45065073100 ps
T87 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.688029414 Feb 09 04:14:57 AM UTC 25 Feb 09 04:15:04 AM UTC 25 557813673 ps
T165 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.2750272711 Feb 09 04:14:39 AM UTC 25 Feb 09 04:15:06 AM UTC 25 2377502526 ps
T308 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.4247062096 Feb 09 04:12:23 AM UTC 25 Feb 09 04:15:09 AM UTC 25 15356489135 ps
T407 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.620866716 Feb 09 04:14:59 AM UTC 25 Feb 09 04:15:14 AM UTC 25 1151819391 ps
T408 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.3105740484 Feb 09 04:15:01 AM UTC 25 Feb 09 04:15:15 AM UTC 25 1149101745 ps
T409 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.2546703580 Feb 09 04:15:12 AM UTC 25 Feb 09 04:15:16 AM UTC 25 93059806 ps
T410 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.3790617586 Feb 09 04:15:05 AM UTC 25 Feb 09 04:15:16 AM UTC 25 474916676 ps
T411 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.3323135213 Feb 09 04:15:01 AM UTC 25 Feb 09 04:15:16 AM UTC 25 884794819 ps
T412 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3644164915 Feb 09 04:15:04 AM UTC 25 Feb 09 04:15:19 AM UTC 25 528139864 ps
T413 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.3870039000 Feb 09 04:15:12 AM UTC 25 Feb 09 04:15:19 AM UTC 25 158849140 ps
T187 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.1936138336 Feb 09 04:15:15 AM UTC 25 Feb 09 04:15:21 AM UTC 25 98704024 ps
T414 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.3545908634 Feb 09 04:15:16 AM UTC 25 Feb 09 04:15:25 AM UTC 25 304371382 ps
T459 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.2098385710 Feb 09 04:14:59 AM UTC 25 Feb 09 04:15:25 AM UTC 25 8711476723 ps
T298 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.1820091629 Feb 09 04:15:04 AM UTC 25 Feb 09 04:15:27 AM UTC 25 436743093 ps
T84 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.2493942858 Feb 09 04:14:46 AM UTC 25 Feb 09 04:15:28 AM UTC 25 1473163282 ps
T448 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.523704401 Feb 09 04:15:24 AM UTC 25 Feb 09 04:15:32 AM UTC 25 296662572 ps
T422 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.2392520809 Feb 09 04:15:00 AM UTC 25 Feb 09 04:15:33 AM UTC 25 3218647322 ps
T108 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.3427821726 Feb 09 04:15:16 AM UTC 25 Feb 09 04:15:34 AM UTC 25 564307260 ps
T525 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.2098408533 Feb 09 04:15:30 AM UTC 25 Feb 09 04:15:34 AM UTC 25 66320397 ps
T425 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.30778116 Feb 09 04:15:18 AM UTC 25 Feb 09 04:15:38 AM UTC 25 951496834 ps
T457 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.2256600340 Feb 09 04:15:26 AM UTC 25 Feb 09 04:15:38 AM UTC 25 1174532399 ps
T195 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.802658142 Feb 09 04:15:20 AM UTC 25 Feb 09 04:15:40 AM UTC 25 567687484 ps
T45 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.1817103808 Feb 09 04:15:35 AM UTC 25 Feb 09 04:15:41 AM UTC 25 182656630 ps
T196 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.1285862436 Feb 09 04:15:20 AM UTC 25 Feb 09 04:15:42 AM UTC 25 6474635418 ps
T430 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.728443881 Feb 09 04:14:46 AM UTC 25 Feb 09 04:15:42 AM UTC 25 14268681389 ps
T526 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.419302178 Feb 09 04:15:04 AM UTC 25 Feb 09 04:15:42 AM UTC 25 8596949363 ps
T29 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.963577372 Feb 09 04:12:24 AM UTC 25 Feb 09 04:16:20 AM UTC 25 24088508563 ps
T494 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.2480057407 Feb 09 04:15:21 AM UTC 25 Feb 09 04:15:45 AM UTC 25 1174854279 ps
T262 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.3692995867 Feb 09 04:13:22 AM UTC 25 Feb 09 04:15:47 AM UTC 25 41703479942 ps
T451 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.680356440 Feb 09 04:15:43 AM UTC 25 Feb 09 04:15:50 AM UTC 25 539232892 ps
T527 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.3475360772 Feb 09 04:15:33 AM UTC 25 Feb 09 04:15:51 AM UTC 25 651897361 ps
T528 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.3593368442 Feb 09 04:15:35 AM UTC 25 Feb 09 04:15:54 AM UTC 25 3971216675 ps
T427 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.158008716 Feb 09 04:15:39 AM UTC 25 Feb 09 04:15:55 AM UTC 25 1088481923 ps
T529 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.4183803383 Feb 09 04:15:52 AM UTC 25 Feb 09 04:15:55 AM UTC 25 181155831 ps
T530 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.23151674 Feb 09 04:15:43 AM UTC 25 Feb 09 04:15:56 AM UTC 25 960405513 ps
T37 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.1848493202 Feb 09 04:15:04 AM UTC 25 Feb 09 04:15:57 AM UTC 25 4765776748 ps
T145 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.2186710807 Feb 09 04:15:41 AM UTC 25 Feb 09 04:16:00 AM UTC 25 572708614 ps
T285 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.2261880654 Feb 09 04:15:35 AM UTC 25 Feb 09 04:16:00 AM UTC 25 1254280078 ps
T461 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.4069944913 Feb 09 04:15:39 AM UTC 25 Feb 09 04:16:03 AM UTC 25 1675013534 ps
T41 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.1378251796 Feb 09 04:15:55 AM UTC 25 Feb 09 04:16:03 AM UTC 25 355070446 ps
T531 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.2588696956 Feb 09 04:15:53 AM UTC 25 Feb 09 04:16:05 AM UTC 25 594742751 ps
T532 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.4281671738 Feb 09 04:15:43 AM UTC 25 Feb 09 04:16:06 AM UTC 25 1110091813 ps
T137 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.2918523915 Feb 09 04:15:07 AM UTC 25 Feb 09 04:16:12 AM UTC 25 5224730602 ps
T431 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.1468198801 Feb 09 04:14:12 AM UTC 25 Feb 09 04:16:12 AM UTC 25 18654619092 ps
T533 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.2893856241 Feb 09 04:15:57 AM UTC 25 Feb 09 04:16:15 AM UTC 25 649151017 ps
T71 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.88756068 Feb 09 04:16:01 AM UTC 25 Feb 09 04:16:16 AM UTC 25 536144087 ps
T482 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.4091136616 Feb 09 04:15:18 AM UTC 25 Feb 09 04:16:17 AM UTC 25 11781944234 ps
T534 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.335989986 Feb 09 04:16:11 AM UTC 25 Feb 09 04:16:17 AM UTC 25 1088937068 ps
T445 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.1432869519 Feb 09 04:16:04 AM UTC 25 Feb 09 04:16:19 AM UTC 25 311686353 ps
T163 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.3450788864 Feb 09 04:15:28 AM UTC 25 Feb 09 04:16:22 AM UTC 25 2634135915 ps
T535 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.2116375153 Feb 09 04:16:16 AM UTC 25 Feb 09 04:16:25 AM UTC 25 354384029 ps
T536 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.3316633559 Feb 09 04:16:16 AM UTC 25 Feb 09 04:16:25 AM UTC 25 1852401305 ps
T224 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.9371992 Feb 09 04:16:16 AM UTC 25 Feb 09 04:16:26 AM UTC 25 2040361710 ps
T504 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.1010156864 Feb 09 04:16:04 AM UTC 25 Feb 09 04:16:27 AM UTC 25 3294086078 ps
T426 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.212439463 Feb 09 04:15:58 AM UTC 25 Feb 09 04:16:28 AM UTC 25 3116944847 ps
T537 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.4000533735 Feb 09 04:16:05 AM UTC 25 Feb 09 04:16:30 AM UTC 25 13501919243 ps
T440 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.2582516245 Feb 09 04:14:32 AM UTC 25 Feb 09 04:16:32 AM UTC 25 11855696106 ps
T466 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.2051753389 Feb 09 04:16:16 AM UTC 25 Feb 09 04:16:32 AM UTC 25 491627074 ps
T538 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.1484190589 Feb 09 04:16:29 AM UTC 25 Feb 09 04:16:33 AM UTC 25 197079571 ps
T539 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.2338997726 Feb 09 04:16:18 AM UTC 25 Feb 09 04:16:33 AM UTC 25 1654670027 ps
T540 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.944462635 Feb 09 04:15:58 AM UTC 25 Feb 09 04:16:35 AM UTC 25 3355216901 ps
T184 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.2144915636 Feb 09 04:16:30 AM UTC 25 Feb 09 04:16:36 AM UTC 25 290764510 ps
T541 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.1147130127 Feb 09 04:16:30 AM UTC 25 Feb 09 04:16:41 AM UTC 25 207903286 ps
T542 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.133376509 Feb 09 04:16:20 AM UTC 25 Feb 09 04:16:41 AM UTC 25 973517297 ps
T429 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.2073096814 Feb 09 04:16:18 AM UTC 25 Feb 09 04:16:41 AM UTC 25 4345428056 ps
T189 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.2807078891 Feb 09 04:16:02 AM UTC 25 Feb 09 04:16:42 AM UTC 25 885461229 ps
T446 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.548513094 Feb 09 04:16:26 AM UTC 25 Feb 09 04:16:43 AM UTC 25 327910724 ps
T543 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.1757783756 Feb 09 04:15:41 AM UTC 25 Feb 09 04:16:44 AM UTC 25 27417604940 ps
T296 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.3038800341 Feb 09 04:16:34 AM UTC 25 Feb 09 04:16:46 AM UTC 25 2663369615 ps
T303 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.4194379545 Feb 09 04:16:34 AM UTC 25 Feb 09 04:16:47 AM UTC 25 588067423 ps
T175 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.3889671130 Feb 09 04:14:53 AM UTC 25 Feb 09 04:16:48 AM UTC 25 10707602224 ps
T325 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.3052144840 Feb 09 04:16:26 AM UTC 25 Feb 09 04:16:49 AM UTC 25 1236373017 ps
T280 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.3373434919 Feb 09 04:16:25 AM UTC 25 Feb 09 04:16:49 AM UTC 25 7576195508 ps
T326 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.2448341049 Feb 09 04:16:46 AM UTC 25 Feb 09 04:16:51 AM UTC 25 80410738 ps
T327 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.503671082 Feb 09 04:16:42 AM UTC 25 Feb 09 04:16:51 AM UTC 25 155193794 ps
T328 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.2179244515 Feb 09 04:16:42 AM UTC 25 Feb 09 04:16:52 AM UTC 25 3810445060 ps
T263 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.3220661461 Feb 09 04:17:40 AM UTC 25 Feb 09 04:17:50 AM UTC 25 158999108 ps
T178 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.1141337025 Feb 09 04:16:21 AM UTC 25 Feb 09 04:16:53 AM UTC 25 4424666347 ps
T52 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.1189418868 Feb 09 04:16:36 AM UTC 25 Feb 09 04:16:53 AM UTC 25 4490171311 ps
T109 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.4258407282 Feb 09 04:16:48 AM UTC 25 Feb 09 04:16:55 AM UTC 25 368223780 ps
T208 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.1958711904 Feb 09 04:16:51 AM UTC 25 Feb 09 04:16:55 AM UTC 25 161375997 ps
T209 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.350037374 Feb 09 04:16:48 AM UTC 25 Feb 09 04:16:58 AM UTC 25 3247680186 ps
T210 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.3487453728 Feb 09 04:16:34 AM UTC 25 Feb 09 04:16:58 AM UTC 25 7187356344 ps
T211 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.618964945 Feb 09 04:16:52 AM UTC 25 Feb 09 04:17:00 AM UTC 25 341809346 ps
T212 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.2633312867 Feb 09 04:16:52 AM UTC 25 Feb 09 04:17:03 AM UTC 25 2109693116 ps
T213 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.1472037090 Feb 09 04:17:00 AM UTC 25 Feb 09 04:17:03 AM UTC 25 52350515 ps
T214 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.2319402996 Feb 09 04:16:54 AM UTC 25 Feb 09 04:17:05 AM UTC 25 619449511 ps
T33 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.2477167790 Feb 09 04:17:01 AM UTC 25 Feb 09 04:17:06 AM UTC 25 320785094 ps
T215 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.4276376644 Feb 09 04:16:56 AM UTC 25 Feb 09 04:17:07 AM UTC 25 710679927 ps
T267 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.2351369206 Feb 09 04:12:55 AM UTC 25 Feb 09 04:17:07 AM UTC 25 173708760611 ps
T268 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.3565078051 Feb 09 04:13:26 AM UTC 25 Feb 09 04:17:08 AM UTC 25 43402627035 ps
T544 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.1779782098 Feb 09 04:17:03 AM UTC 25 Feb 09 04:17:11 AM UTC 25 547949564 ps
T505 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.172057606 Feb 09 04:16:54 AM UTC 25 Feb 09 04:17:11 AM UTC 25 535700400 ps
T168 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.2014507565 Feb 09 04:17:04 AM UTC 25 Feb 09 04:17:12 AM UTC 25 2618876997 ps
T545 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.3519891999 Feb 09 04:17:09 AM UTC 25 Feb 09 04:17:16 AM UTC 25 275461595 ps
T483 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.3941832103 Feb 09 04:17:08 AM UTC 25 Feb 09 04:17:17 AM UTC 25 323548421 ps
T190 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.1776932828 Feb 09 04:16:38 AM UTC 25 Feb 09 04:17:18 AM UTC 25 3570633815 ps
T503 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.1643202087 Feb 09 04:17:01 AM UTC 25 Feb 09 04:17:18 AM UTC 25 1283972179 ps
T476 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.140818986 Feb 09 04:16:34 AM UTC 25 Feb 09 04:17:20 AM UTC 25 1653669129 ps
T197 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.323872388 Feb 09 04:17:08 AM UTC 25 Feb 09 04:17:20 AM UTC 25 442491738 ps
T546 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.160705057 Feb 09 04:17:17 AM UTC 25 Feb 09 04:17:21 AM UTC 25 94416647 ps
T547 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.3954430511 Feb 09 04:17:05 AM UTC 25 Feb 09 04:17:22 AM UTC 25 335874788 ps
T548 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.1356007683 Feb 09 04:16:51 AM UTC 25 Feb 09 04:17:24 AM UTC 25 10021902507 ps
T549 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.3073772265 Feb 09 04:16:51 AM UTC 25 Feb 09 04:17:26 AM UTC 25 12259489307 ps
T550 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.1098115754 Feb 09 04:17:19 AM UTC 25 Feb 09 04:17:27 AM UTC 25 184437127 ps
T55 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.1687036817 Feb 09 04:17:19 AM UTC 25 Feb 09 04:17:27 AM UTC 25 172053685 ps
T551 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1092078365 Feb 09 04:16:54 AM UTC 25 Feb 09 04:17:30 AM UTC 25 3873132001 ps
T478 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.1624663200 Feb 09 04:17:04 AM UTC 25 Feb 09 04:17:34 AM UTC 25 10357157862 ps
T492 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.882106596 Feb 09 04:17:09 AM UTC 25 Feb 09 04:17:37 AM UTC 25 603235868 ps
T552 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.3540758330 Feb 09 04:17:28 AM UTC 25 Feb 09 04:17:38 AM UTC 25 278111923 ps
T239 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.4110466646 Feb 09 04:17:21 AM UTC 25 Feb 09 04:17:38 AM UTC 25 298671392 ps
T553 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.203339797 Feb 09 04:17:53 AM UTC 25 Feb 09 04:18:01 AM UTC 25 556669031 ps
T554 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.2502609734 Feb 09 04:17:35 AM UTC 25 Feb 09 04:17:39 AM UTC 25 99564985 ps
T555 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.774785922 Feb 09 04:17:18 AM UTC 25 Feb 09 04:17:39 AM UTC 25 6840775270 ps
T556 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.215169832 Feb 09 04:17:37 AM UTC 25 Feb 09 04:17:45 AM UTC 25 830561650 ps
T110 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.397130432 Feb 09 04:17:38 AM UTC 25 Feb 09 04:17:46 AM UTC 25 156910586 ps
T216 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.3018521893 Feb 09 04:17:22 AM UTC 25 Feb 09 04:17:46 AM UTC 25 653178348 ps
T217 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.3247760525 Feb 09 04:17:40 AM UTC 25 Feb 09 04:17:47 AM UTC 25 1721320549 ps
T218 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.1828302960 Feb 09 04:17:42 AM UTC 25 Feb 09 04:17:52 AM UTC 25 645887900 ps
T219 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.3053483813 Feb 09 04:17:27 AM UTC 25 Feb 09 04:17:48 AM UTC 25 1644554648 ps
T220 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.2814139169 Feb 09 04:17:11 AM UTC 25 Feb 09 04:17:50 AM UTC 25 1103740619 ps
T221 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.4152378775 Feb 09 04:17:21 AM UTC 25 Feb 09 04:17:50 AM UTC 25 1198571299 ps
T179 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.103639227 Feb 09 04:17:25 AM UTC 25 Feb 09 04:17:50 AM UTC 25 862815974 ps
T222 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.3285920907 Feb 09 04:17:38 AM UTC 25 Feb 09 04:17:53 AM UTC 25 717434808 ps
T223 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.1125878244 Feb 09 04:17:46 AM UTC 25 Feb 09 04:17:55 AM UTC 25 401887529 ps
T449 /workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.2050422804 Feb 09 04:17:46 AM UTC 25 Feb 09 04:17:56 AM UTC 25 2688895600 ps