Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	2	0	2	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	8	0	8	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr_pin

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_pins[0]

172219

1

T1

67

T3

68

T4

64

all_pins[1]

172219

1

T1

67

T3

68

T4

64

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	281416	1			T1	105		T3	136		T4	128
values[0x1]	63022	1			T1	29		T5	91		T6	86
transitions[0x0=>0x1]	46007	1			T1	12		T5	91		T6	54
transitions[0x1=>0x0]	45937	1			T1	12		T5	91		T6	54

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	126415	1			T1	47		T3	68		T4	64
all_pins[0]	values[0x1]	45804	1			T1	20		T5	91		T6	70
all_pins[0]	transitions[0x0=>0x1]	37348	1			T1	11		T5	91		T6	54
all_pins[0]	transitions[0x1=>0x0]	8762	1			T99	2		T97	7		T94	7
all_pins[1]	values[0x0]	155001	1			T1	58		T3	68		T4	64
all_pins[1]	values[0x1]	17218	1			T1	9		T6	16		T11	21
all_pins[1]	transitions[0x0=>0x1]	8659	1			T1	1		T99	1		T97	7
all_pins[1]	transitions[0x1=>0x0]	37175	1			T1	12		T5	91		T6	54