Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	42444	1			T7	34		T13	153		T87	8
access_err	48817	1			T7	25		T17	3		T26	41
write_blank_err	394	1			T8	2		T9	3		T10	3
ecc_uncorr_err	56020	1			T6	13		T8	389		T9	532
ecc_corr_err	1250	1			T6	2		T7	7		T9	5
no_err	72096	1			T3	6		T4	27		T6	10

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	693	1			T8	10		T9	12		T10	9
secret2	17933	1			T4	3		T6	1		T7	10
secret1	25098	1			T4	5		T7	4		T73	3
secret0	29404	1			T4	5		T6	9		T7	6
hw_cfg1	29903	1			T4	2		T7	3		T73	2
hw_cfg0	18646	1			T3	1		T4	1		T7	4
rot_creator_auth_state	16781	1			T3	2		T4	2		T6	2
rot_creator_auth_codesign	18698	1			T3	2		T4	3		T7	6
owner_sw_cfg	16467	1			T4	2		T6	4		T7	3
creator_sw_cfg	16346	1			T4	2		T6	6		T7	12
vendor_test	31052	1			T3	1		T4	2		T6	3

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2927	1			T113	33		T114	24		T240	254
fsm_err	secret1	3605	1			T123	45		T229	409		T230	51
fsm_err	secret0	2795	1			T369	369		T370	475		T191	110
fsm_err	hw_cfg1	1363	1			T117	75		T222	143		T62	34
fsm_err	hw_cfg0	3071	1			T13	153		T79	133		T115	40
fsm_err	rot_creator_auth_state	2212	1			T60	96		T56	95		T58	42
fsm_err	rot_creator_auth_codesign	4144	1			T51	15		T268	551		T371	214
fsm_err	owner_sw_cfg	2803	1			T372	30		T267	35		T135	59
fsm_err	creator_sw_cfg	2457	1			T373	4		T29	58		T30	60
fsm_err	vendor_test	17067	1			T7	34		T87	8		T27	180
access_err	life_cycle	693	1			T8	10		T9	12		T10	9
access_err	secret2	8499	1			T7	5		T26	7		T38	1
access_err	secret1	5552	1			T7	4		T17	2		T26	6
access_err	secret0	4406	1			T7	2		T17	1		T26	10
access_err	hw_cfg1	1149	1			T7	2		T26	2		T38	2
access_err	hw_cfg0	2016	1			T26	2		T18	1		T48	7
access_err	rot_creator_auth_state	4191	1			T18	6		T9	1		T27	3
access_err	rot_creator_auth_codesign	5916	1			T7	3		T26	1		T18	7
access_err	owner_sw_cfg	4785	1			T26	5		T38	2		T48	4
access_err	creator_sw_cfg	5852	1			T7	6		T26	8		T18	14
access_err	vendor_test	5758	1			T7	3		T38	1		T18	8
write_blank_err	secret2	5	1			T374	1		T375	1		T376	1
write_blank_err	secret1	27	1			T9	1		T10	1		T99	1
write_blank_err	secret0	47	1			T377	1		T346	1		T374	1
write_blank_err	hw_cfg1	73	1			T8	1		T9	1		T64	2
write_blank_err	hw_cfg0	9	1			T378	1		T379	1		T380	1
write_blank_err	rot_creator_auth_state	114	1			T64	8		T110	3		T381	1
write_blank_err	rot_creator_auth_codesign	41	1			T10	2		T64	4		T377	1
write_blank_err	owner_sw_cfg	24	1			T110	3		T15	5		T216	1
write_blank_err	creator_sw_cfg	24	1			T382	1		T378	4		T383	1
write_blank_err	vendor_test	30	1			T8	1		T9	1		T64	1
ecc_uncorr_err	secret2	1850	1			T51	17		T384	13		T58	25
ecc_uncorr_err	secret1	9257	1			T198	6		T51	11		T10	339
ecc_uncorr_err	secret0	15891	1			T6	7		T118	58		T56	43
ecc_uncorr_err	hw_cfg1	18782	1			T8	389		T9	532		T198	5
ecc_uncorr_err	hw_cfg0	3578	1			T198	9		T51	14		T49	20
ecc_uncorr_err	rot_creator_auth_state	2772	1			T198	30		T56	55		T111	108
ecc_uncorr_err	rot_creator_auth_codesign	1142	1			T198	11		T56	38		T111	182
ecc_uncorr_err	owner_sw_cfg	1451	1			T58	77		T53	72		T385	43
ecc_uncorr_err	creator_sw_cfg	1297	1			T6	6		T198	10		T382	534
ecc_corr_err	secret2	96	1			T27	2		T28	2		T39	1
ecc_corr_err	secret1	92	1			T9	5		T27	3		T39	2
ecc_corr_err	secret0	108	1			T27	1		T51	1		T28	2
ecc_corr_err	hw_cfg1	256	1			T198	3		T64	1		T50	3
ecc_corr_err	hw_cfg0	231	1			T7	1		T27	5		T51	3
ecc_corr_err	rot_creator_auth_state	107	1			T6	1		T28	1		T49	1
ecc_corr_err	rot_creator_auth_codesign	109	1			T7	1		T51	1		T28	2
ecc_corr_err	owner_sw_cfg	125	1			T6	1		T7	1		T27	1
ecc_corr_err	creator_sw_cfg	126	1			T7	4		T27	1		T28	6
no_err	secret2	4556	1			T4	3		T6	1		T7	5
no_err	secret1	6565	1			T4	5		T73	3		T26	7
no_err	secret0	6157	1			T4	5		T6	2		T7	4
no_err	hw_cfg1	8280	1			T4	2		T7	1		T73	2
no_err	hw_cfg0	9741	1			T3	1		T4	1		T7	3
no_err	rot_creator_auth_state	7385	1			T3	2		T4	2		T6	1
no_err	rot_creator_auth_codesign	7346	1			T3	2		T4	3		T7	2
no_err	owner_sw_cfg	7279	1			T4	2		T6	3		T7	2
no_err	creator_sw_cfg	6590	1			T4	2		T7	2		T75	16
no_err	vendor_test	8197	1			T3	1		T4	2		T6	3

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded