Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47610	1			T132	60		T97	112		T98	19
access_err	61424	1			T1	38		T6	51		T11	71
write_blank_err	443	1			T100	4		T7	1		T152	1
ecc_uncorr_err	64051	1			T99	4		T100	110		T7	311
ecc_corr_err	1129	1			T99	1		T133	2		T97	31
no_err	90005	1			T1	65		T4	89		T5	142

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	626	1			T7	5		T8	8		T9	13
secret2	21846	1			T1	9		T4	2		T5	8
secret1	28492	1			T1	4		T4	10		T5	9
secret0	31818	1			T1	7		T4	11		T5	13
hw_cfg1	35982	1			T1	10		T4	7		T5	10
hw_cfg0	26154	1			T1	9		T4	3		T5	14
rot_creator_auth_state	22483	1			T1	23		T4	10		T5	6
rot_creator_auth_codesign	22583	1			T1	11		T4	2		T5	29
owner_sw_cfg	22618	1			T1	12		T4	17		T5	13
creator_sw_cfg	21840	1			T1	9		T4	15		T5	26
vendor_test	30220	1			T1	9		T4	12		T5	14

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2598	1			T178	23		T419	121		T420	19
fsm_err	secret1	2947	1			T162	3		T165	338		T308	54
fsm_err	secret0	2932	1			T200	27		T163	107		T179	37
fsm_err	hw_cfg1	5488	1			T265	573		T285	573		T163	264
fsm_err	hw_cfg0	5926	1			T137	188		T229	25		T421	268
fsm_err	rot_creator_auth_state	1051	1			T308	173		T175	3		T123	45
fsm_err	rot_creator_auth_codesign	4285	1			T177	20		T200	29		T178	14
fsm_err	owner_sw_cfg	4440	1			T422	391		T175	411		T178	8
fsm_err	creator_sw_cfg	4834	1			T233	194		T189	105		T190	56
fsm_err	vendor_test	13109	1			T132	60		T97	112		T98	19
access_err	life_cycle	626	1			T7	5		T8	8		T9	13
access_err	secret2	10396	1			T1	6		T6	5		T11	11
access_err	secret1	6082	1			T6	5		T97	26		T94	5
access_err	secret0	4527	1			T6	4		T133	2		T94	7
access_err	hw_cfg1	1314	1			T1	1		T6	4		T11	3
access_err	hw_cfg0	2342	1			T6	1		T11	6		T97	6
access_err	rot_creator_auth_state	6198	1			T1	16		T6	3		T11	6
access_err	rot_creator_auth_codesign	8174	1			T1	2		T6	3		T11	6
access_err	owner_sw_cfg	6513	1			T1	4		T6	4		T11	24
access_err	creator_sw_cfg	7766	1			T1	9		T6	11		T11	7
access_err	vendor_test	7486	1			T6	11		T11	8		T97	11
write_blank_err	secret2	7	1			T181	1		T423	1		T424	1
write_blank_err	secret1	23	1			T9	1		T274	1		T262	1
write_blank_err	secret0	48	1			T100	1		T8	1		T275	1
write_blank_err	hw_cfg1	64	1			T7	1		T152	1		T9	1
write_blank_err	hw_cfg0	16	1			T264	1		T425	1		T426	1
write_blank_err	rot_creator_auth_state	137	1			T264	1		T274	3		T308	2
write_blank_err	rot_creator_auth_codesign	83	1			T100	3		T264	3		T308	1
write_blank_err	owner_sw_cfg	15	1			T308	5		T427	4		T175	1
write_blank_err	creator_sw_cfg	28	1			T263	1		T241	1		T428	1
write_blank_err	vendor_test	22	1			T429	1		T175	1		T140	1
ecc_uncorr_err	secret2	3532	1			T181	346		T430	64		T178	21
ecc_uncorr_err	secret1	10193	1			T177	17		T200	31		T274	556
ecc_uncorr_err	secret0	15442	1			T100	110		T8	635		T275	259
ecc_uncorr_err	hw_cfg1	18337	1			T7	311		T152	126		T180	108
ecc_uncorr_err	hw_cfg0	5711	1			T182	14		T200	59		T264	243
ecc_uncorr_err	rot_creator_auth_state	6772	1			T180	70		T188	5		T431	544
ecc_uncorr_err	rot_creator_auth_codesign	1142	1			T177	18		T416	2		T189	57
ecc_uncorr_err	owner_sw_cfg	1994	1			T99	4		T177	18		T188	8
ecc_uncorr_err	creator_sw_cfg	928	1			T180	53		T177	39		T196	73
ecc_corr_err	secret2	59	1			T51	2		T84	3		T430	3
ecc_corr_err	secret1	80	1			T99	1		T180	4		T141	1
ecc_corr_err	secret0	135	1			T97	9		T51	1		T180	1
ecc_corr_err	hw_cfg1	225	1			T133	1		T97	5		T51	1
ecc_corr_err	hw_cfg0	239	1			T97	9		T51	4		T141	3
ecc_corr_err	rot_creator_auth_state	135	1			T97	5		T188	1		T416	1
ecc_corr_err	rot_creator_auth_codesign	77	1			T133	1		T177	4		T48	2
ecc_corr_err	owner_sw_cfg	82	1			T97	3		T84	1		T196	1
ecc_corr_err	creator_sw_cfg	97	1			T177	1		T182	1		T84	2
no_err	secret2	5254	1			T1	3		T4	2		T5	8
no_err	secret1	9167	1			T1	4		T4	10		T5	9
no_err	secret0	8734	1			T1	7		T4	11		T5	13
no_err	hw_cfg1	10554	1			T1	9		T4	7		T5	10
no_err	hw_cfg0	11920	1			T1	9		T4	3		T5	14
no_err	rot_creator_auth_state	8190	1			T1	7		T4	10		T5	6
no_err	rot_creator_auth_codesign	8822	1			T1	9		T4	2		T5	29
no_err	owner_sw_cfg	9574	1			T1	8		T4	17		T5	13
no_err	creator_sw_cfg	8187	1			T4	15		T5	26		T6	4
no_err	vendor_test	9603	1			T1	9		T4	12		T5	14

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded