9601d3bbdd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 13.000s | 1.226ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 3.000s | 165.998us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 8.000s | 12.425us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 4.000s | 100.706us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 54.181us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 8.000s | 24.352us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 8.000s | 12.425us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 54.181us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.717m | 4.115ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.950m | 10.501ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 8.000s | 16.578us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.733m | 17.177ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 12.000s | 13.870us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 13.000s | 38.663us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 9.000s | 37.894us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 9.000s | 37.894us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 3.000s | 165.998us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 8.000s | 12.425us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 54.181us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 4.000s | 21.182us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 3.000s | 165.998us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 8.000s | 12.425us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 54.181us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 4.000s | 21.182us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 9.000s | 42.173us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 3.000s | 228.603us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 9.000s | 42.173us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 29.417m | 151.898ms | 46 | 50 | 92.00 |
| V3 | TOTAL | 46 | 50 | 92.00 | |||
| TOTAL | 516 | 520 | 99.23 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
4.pattgen_stress_all_with_rand_reset.93171584824508831077890005168843722399705635422479402439626497063603535948327
Line 722, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27466510038 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
16.pattgen_stress_all_with_rand_reset.75857764867657095730161250867440420036871439138757295363042961616870777275585
Line 519, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9701551343 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 2 more failures.