Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.23 89.23 100.00 100.00 95.83 95.83 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/18.prim_async_alert.335499176
91.76 2.53 100.00 0.00 95.83 0.00 100.00 0.00 82.14 3.57 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/11.prim_sync_alert.2153231028
93.52 1.76 100.00 0.00 95.83 0.00 100.00 0.00 85.71 3.57 95.83 0.00 83.72 6.98 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3048961198
94.50 0.98 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 2.33 /workspace/coverage/default/11.prim_async_alert.2035961348
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.652192820
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2287179443

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1516307234
/workspace/coverage/default/1.prim_async_alert.2530529596
/workspace/coverage/default/10.prim_async_alert.1034265476
/workspace/coverage/default/12.prim_async_alert.1342614608
/workspace/coverage/default/13.prim_async_alert.385367773
/workspace/coverage/default/14.prim_async_alert.2561090726
/workspace/coverage/default/15.prim_async_alert.2278088584
/workspace/coverage/default/16.prim_async_alert.2834434518
/workspace/coverage/default/17.prim_async_alert.3706441694
/workspace/coverage/default/19.prim_async_alert.3810258824
/workspace/coverage/default/2.prim_async_alert.3562768870
/workspace/coverage/default/3.prim_async_alert.160529734
/workspace/coverage/default/4.prim_async_alert.1902940849
/workspace/coverage/default/5.prim_async_alert.4283705723
/workspace/coverage/default/6.prim_async_alert.1555391368
/workspace/coverage/default/7.prim_async_alert.190970422
/workspace/coverage/default/8.prim_async_alert.4102649499
/workspace/coverage/default/9.prim_async_alert.2667071876
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2578916441
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2650710597
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3190664854
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.338058249
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3396465894
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4039518182
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4229651480
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2054816675
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1636187242
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3086274228
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1767943036
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2584172232
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1072931677
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.797509809
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3195182551
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2570883828
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.149924227
/workspace/coverage/sync_alert/0.prim_sync_alert.1141811453
/workspace/coverage/sync_alert/1.prim_sync_alert.3629326109
/workspace/coverage/sync_alert/10.prim_sync_alert.439944424
/workspace/coverage/sync_alert/12.prim_sync_alert.4039473763
/workspace/coverage/sync_alert/13.prim_sync_alert.296185899
/workspace/coverage/sync_alert/14.prim_sync_alert.3040740875
/workspace/coverage/sync_alert/15.prim_sync_alert.3807035062
/workspace/coverage/sync_alert/16.prim_sync_alert.2473165976
/workspace/coverage/sync_alert/17.prim_sync_alert.1497194828
/workspace/coverage/sync_alert/18.prim_sync_alert.2529638414
/workspace/coverage/sync_alert/19.prim_sync_alert.339400887
/workspace/coverage/sync_alert/2.prim_sync_alert.470612843
/workspace/coverage/sync_alert/3.prim_sync_alert.1799225928
/workspace/coverage/sync_alert/4.prim_sync_alert.949327154
/workspace/coverage/sync_alert/5.prim_sync_alert.495838104
/workspace/coverage/sync_alert/6.prim_sync_alert.3120022783
/workspace/coverage/sync_alert/7.prim_sync_alert.3164220092
/workspace/coverage/sync_alert/8.prim_sync_alert.3688639033
/workspace/coverage/sync_alert/9.prim_sync_alert.3873844342
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2210565861
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2992945818
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1118441326
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2097024683
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3349483333
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2271965414
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2718186627
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3105133984
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2188261493
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1732898272
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3115807515
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1699717403
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.713991376
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1542943718
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.20024259
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2403812254
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3590947696
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.804007178
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3442750858



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/4.prim_async_alert.1902940849 Sep 27 12:38:20 PM PDT 23 Sep 27 12:38:21 PM PDT 23 11009746 ps
T2 /workspace/coverage/default/18.prim_async_alert.335499176 Sep 27 12:32:21 PM PDT 23 Sep 27 12:32:22 PM PDT 23 11370329 ps
T3 /workspace/coverage/default/3.prim_async_alert.160529734 Sep 27 12:33:07 PM PDT 23 Sep 27 12:33:07 PM PDT 23 10821192 ps
T8 /workspace/coverage/default/17.prim_async_alert.3706441694 Sep 27 12:32:17 PM PDT 23 Sep 27 12:32:18 PM PDT 23 12070817 ps
T15 /workspace/coverage/default/14.prim_async_alert.2561090726 Sep 27 12:33:41 PM PDT 23 Sep 27 12:33:41 PM PDT 23 11999112 ps
T7 /workspace/coverage/default/19.prim_async_alert.3810258824 Sep 27 12:40:17 PM PDT 23 Sep 27 12:40:17 PM PDT 23 11806492 ps
T17 /workspace/coverage/default/9.prim_async_alert.2667071876 Sep 27 12:43:23 PM PDT 23 Sep 27 12:43:23 PM PDT 23 10335554 ps
T18 /workspace/coverage/default/5.prim_async_alert.4283705723 Sep 27 12:50:06 PM PDT 23 Sep 27 12:50:07 PM PDT 23 10563743 ps
T19 /workspace/coverage/default/8.prim_async_alert.4102649499 Sep 27 12:45:42 PM PDT 23 Sep 27 12:45:42 PM PDT 23 11621325 ps
T13 /workspace/coverage/default/11.prim_async_alert.2035961348 Sep 27 12:43:07 PM PDT 23 Sep 27 12:43:08 PM PDT 23 11159246 ps
T16 /workspace/coverage/default/16.prim_async_alert.2834434518 Sep 27 12:43:07 PM PDT 23 Sep 27 12:43:07 PM PDT 23 10279389 ps
T10 /workspace/coverage/default/12.prim_async_alert.1342614608 Sep 27 12:30:29 PM PDT 23 Sep 27 12:30:29 PM PDT 23 12280473 ps
T11 /workspace/coverage/default/15.prim_async_alert.2278088584 Sep 27 12:32:20 PM PDT 23 Sep 27 12:32:20 PM PDT 23 10249889 ps
T32 /workspace/coverage/default/0.prim_async_alert.1516307234 Sep 27 12:39:21 PM PDT 23 Sep 27 12:39:22 PM PDT 23 10761768 ps
T42 /workspace/coverage/default/6.prim_async_alert.1555391368 Sep 27 12:37:11 PM PDT 23 Sep 27 12:37:12 PM PDT 23 11467496 ps
T14 /workspace/coverage/default/13.prim_async_alert.385367773 Sep 27 12:30:31 PM PDT 23 Sep 27 12:30:32 PM PDT 23 11189279 ps
T43 /workspace/coverage/default/1.prim_async_alert.2530529596 Sep 27 12:31:07 PM PDT 23 Sep 27 12:31:07 PM PDT 23 10871479 ps
T44 /workspace/coverage/default/10.prim_async_alert.1034265476 Sep 27 12:31:44 PM PDT 23 Sep 27 12:31:45 PM PDT 23 11562967 ps
T12 /workspace/coverage/default/2.prim_async_alert.3562768870 Sep 27 12:41:44 PM PDT 23 Sep 27 12:41:45 PM PDT 23 13261738 ps
T20 /workspace/coverage/default/7.prim_async_alert.190970422 Sep 27 12:39:26 PM PDT 23 Sep 27 12:39:27 PM PDT 23 11055484 ps
T33 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3190664854 Sep 27 12:56:40 PM PDT 23 Sep 27 12:56:41 PM PDT 23 29974540 ps
T34 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1072931677 Sep 27 12:56:49 PM PDT 23 Sep 27 12:56:50 PM PDT 23 30773639 ps
T35 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1636187242 Sep 27 12:56:48 PM PDT 23 Sep 27 12:56:49 PM PDT 23 32153208 ps
T36 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2570883828 Sep 27 12:56:37 PM PDT 23 Sep 27 12:56:37 PM PDT 23 31044378 ps
T37 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2054816675 Sep 27 12:56:41 PM PDT 23 Sep 27 12:56:41 PM PDT 23 29916641 ps
T38 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.149924227 Sep 27 12:56:59 PM PDT 23 Sep 27 12:57:00 PM PDT 23 29715786 ps
T4 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.652192820 Sep 27 12:56:49 PM PDT 23 Sep 27 12:56:49 PM PDT 23 29330376 ps
T39 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3048961198 Sep 27 12:56:59 PM PDT 23 Sep 27 12:56:59 PM PDT 23 30007415 ps
T40 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4039518182 Sep 27 12:56:49 PM PDT 23 Sep 27 12:56:50 PM PDT 23 31463489 ps
T41 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1767943036 Sep 27 12:56:49 PM PDT 23 Sep 27 12:56:50 PM PDT 23 29751860 ps
T45 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.797509809 Sep 27 12:56:49 PM PDT 23 Sep 27 12:56:50 PM PDT 23 28832728 ps
T46 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3396465894 Sep 27 12:56:48 PM PDT 23 Sep 27 12:56:49 PM PDT 23 33599088 ps
T47 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4229651480 Sep 27 12:56:44 PM PDT 23 Sep 27 12:56:45 PM PDT 23 29249121 ps
T48 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3195182551 Sep 27 12:56:36 PM PDT 23 Sep 27 12:56:36 PM PDT 23 28472223 ps
T49 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.338058249 Sep 27 12:56:51 PM PDT 23 Sep 27 12:56:52 PM PDT 23 32558252 ps
T50 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2584172232 Sep 27 12:56:38 PM PDT 23 Sep 27 12:56:39 PM PDT 23 28515976 ps
T51 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3086274228 Sep 27 12:56:50 PM PDT 23 Sep 27 12:56:51 PM PDT 23 29777153 ps
T52 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2650710597 Sep 27 12:56:39 PM PDT 23 Sep 27 12:56:40 PM PDT 23 29157620 ps
T53 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2578916441 Sep 27 12:56:49 PM PDT 23 Sep 27 12:56:50 PM PDT 23 29626967 ps
T30 /workspace/coverage/sync_alert/9.prim_sync_alert.3873844342 Sep 27 12:20:08 PM PDT 23 Sep 27 12:20:09 PM PDT 23 9992820 ps
T31 /workspace/coverage/sync_alert/13.prim_sync_alert.296185899 Sep 27 12:19:53 PM PDT 23 Sep 27 12:19:55 PM PDT 23 8233912 ps
T21 /workspace/coverage/sync_alert/4.prim_sync_alert.949327154 Sep 27 12:24:25 PM PDT 23 Sep 27 12:24:27 PM PDT 23 8725055 ps
T22 /workspace/coverage/sync_alert/17.prim_sync_alert.1497194828 Sep 27 12:19:54 PM PDT 23 Sep 27 12:19:55 PM PDT 23 8754770 ps
T23 /workspace/coverage/sync_alert/2.prim_sync_alert.470612843 Sep 27 12:12:48 PM PDT 23 Sep 27 12:12:49 PM PDT 23 8836789 ps
T24 /workspace/coverage/sync_alert/5.prim_sync_alert.495838104 Sep 27 12:20:09 PM PDT 23 Sep 27 12:20:09 PM PDT 23 8442054 ps
T25 /workspace/coverage/sync_alert/10.prim_sync_alert.439944424 Sep 27 12:13:39 PM PDT 23 Sep 27 12:13:40 PM PDT 23 8800704 ps
T26 /workspace/coverage/sync_alert/11.prim_sync_alert.2153231028 Sep 27 12:13:10 PM PDT 23 Sep 27 12:13:10 PM PDT 23 9661494 ps
T27 /workspace/coverage/sync_alert/14.prim_sync_alert.3040740875 Sep 27 12:19:49 PM PDT 23 Sep 27 12:19:49 PM PDT 23 8548582 ps
T28 /workspace/coverage/sync_alert/19.prim_sync_alert.339400887 Sep 27 12:12:49 PM PDT 23 Sep 27 12:12:50 PM PDT 23 9888065 ps
T29 /workspace/coverage/sync_alert/0.prim_sync_alert.1141811453 Sep 27 12:19:28 PM PDT 23 Sep 27 12:19:29 PM PDT 23 9573553 ps
T54 /workspace/coverage/sync_alert/12.prim_sync_alert.4039473763 Sep 27 12:17:30 PM PDT 23 Sep 27 12:17:31 PM PDT 23 8528417 ps
T55 /workspace/coverage/sync_alert/3.prim_sync_alert.1799225928 Sep 27 12:12:49 PM PDT 23 Sep 27 12:12:50 PM PDT 23 9434337 ps
T56 /workspace/coverage/sync_alert/16.prim_sync_alert.2473165976 Sep 27 12:20:05 PM PDT 23 Sep 27 12:20:06 PM PDT 23 9427597 ps
T57 /workspace/coverage/sync_alert/18.prim_sync_alert.2529638414 Sep 27 12:19:53 PM PDT 23 Sep 27 12:19:55 PM PDT 23 9513070 ps
T58 /workspace/coverage/sync_alert/6.prim_sync_alert.3120022783 Sep 27 12:12:49 PM PDT 23 Sep 27 12:12:49 PM PDT 23 8541703 ps
T59 /workspace/coverage/sync_alert/8.prim_sync_alert.3688639033 Sep 27 12:19:21 PM PDT 23 Sep 27 12:19:22 PM PDT 23 8922638 ps
T60 /workspace/coverage/sync_alert/15.prim_sync_alert.3807035062 Sep 27 12:19:55 PM PDT 23 Sep 27 12:19:56 PM PDT 23 9637215 ps
T61 /workspace/coverage/sync_alert/1.prim_sync_alert.3629326109 Sep 27 12:15:15 PM PDT 23 Sep 27 12:15:16 PM PDT 23 9000145 ps
T62 /workspace/coverage/sync_alert/7.prim_sync_alert.3164220092 Sep 27 12:19:27 PM PDT 23 Sep 27 12:19:27 PM PDT 23 8937242 ps
T9 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2287179443 Sep 27 12:58:04 PM PDT 23 Sep 27 12:58:04 PM PDT 23 29923055 ps
T5 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3349483333 Sep 27 12:58:36 PM PDT 23 Sep 27 12:58:37 PM PDT 23 28292160 ps
T63 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2718186627 Sep 27 12:58:07 PM PDT 23 Sep 27 12:58:08 PM PDT 23 26798792 ps
T64 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3115807515 Sep 27 12:58:05 PM PDT 23 Sep 27 12:58:06 PM PDT 23 26196941 ps
T65 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.713991376 Sep 27 12:58:12 PM PDT 23 Sep 27 12:58:13 PM PDT 23 27631358 ps
T66 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3442750858 Sep 27 12:58:49 PM PDT 23 Sep 27 12:58:49 PM PDT 23 26887516 ps
T67 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2097024683 Sep 27 12:58:23 PM PDT 23 Sep 27 12:58:24 PM PDT 23 28117578 ps
T68 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2188261493 Sep 27 12:58:48 PM PDT 23 Sep 27 12:58:49 PM PDT 23 25412024 ps
T69 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2992945818 Sep 27 12:58:07 PM PDT 23 Sep 27 12:58:07 PM PDT 23 26777565 ps
T70 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.804007178 Sep 27 12:58:44 PM PDT 23 Sep 27 12:58:45 PM PDT 23 27022302 ps
T71 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2403812254 Sep 27 12:57:55 PM PDT 23 Sep 27 12:57:55 PM PDT 23 29263254 ps
T72 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1542943718 Sep 27 12:58:15 PM PDT 23 Sep 27 12:58:16 PM PDT 23 27731641 ps
T73 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1699717403 Sep 27 12:58:02 PM PDT 23 Sep 27 12:58:03 PM PDT 23 26265178 ps
T6 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1118441326 Sep 27 12:58:11 PM PDT 23 Sep 27 12:58:12 PM PDT 23 26337164 ps
T74 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2271965414 Sep 27 12:58:22 PM PDT 23 Sep 27 12:58:33 PM PDT 23 28529290 ps
T75 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3590947696 Sep 27 12:58:14 PM PDT 23 Sep 27 12:58:14 PM PDT 23 27624154 ps
T76 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3105133984 Sep 27 12:58:09 PM PDT 23 Sep 27 12:58:10 PM PDT 23 27516863 ps
T77 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1732898272 Sep 27 12:58:15 PM PDT 23 Sep 27 12:58:16 PM PDT 23 28617064 ps
T78 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.20024259 Sep 27 12:58:45 PM PDT 23 Sep 27 12:58:46 PM PDT 23 28330019 ps
T79 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2210565861 Sep 27 12:58:15 PM PDT 23 Sep 27 12:58:16 PM PDT 23 28905795 ps

Test location /workspace/coverage/default/18.prim_async_alert.335499176
Short name T2
Test name
Test status
Simulation time 11370329 ps
CPU time 0.39 seconds
Started Sep 27 12:32:21 PM PDT 23
Finished Sep 27 12:32:22 PM PDT 23
Peak memory 145388 kb
Host smart-ec67a66d-8908-430d-b5dd-7467d486b6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335499176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.335499176
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2153231028
Short name T26
Test name
Test status
Simulation time 9661494 ps
CPU time 0.38 seconds
Started Sep 27 12:13:10 PM PDT 23
Finished Sep 27 12:13:10 PM PDT 23
Peak memory 145116 kb
Host smart-0a3d689b-6edd-4506-b4da-98019072497e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2153231028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2153231028
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3048961198
Short name T39
Test name
Test status
Simulation time 30007415 ps
CPU time 0.4 seconds
Started Sep 27 12:56:59 PM PDT 23
Finished Sep 27 12:56:59 PM PDT 23
Peak memory 145572 kb
Host smart-e3c18028-3f07-48d9-873b-5980a2a19c97
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3048961198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3048961198
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.2035961348
Short name T13
Test name
Test status
Simulation time 11159246 ps
CPU time 0.38 seconds
Started Sep 27 12:43:07 PM PDT 23
Finished Sep 27 12:43:08 PM PDT 23
Peak memory 145448 kb
Host smart-2d1cf3eb-62fc-4820-aa3d-6fb56c767502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035961348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.2035961348
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.652192820
Short name T4
Test name
Test status
Simulation time 29330376 ps
CPU time 0.39 seconds
Started Sep 27 12:56:49 PM PDT 23
Finished Sep 27 12:56:49 PM PDT 23
Peak memory 145556 kb
Host smart-802b313a-10a7-4379-a927-9bef3d977a85
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=652192820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.652192820
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2287179443
Short name T9
Test name
Test status
Simulation time 29923055 ps
CPU time 0.38 seconds
Started Sep 27 12:58:04 PM PDT 23
Finished Sep 27 12:58:04 PM PDT 23
Peak memory 145004 kb
Host smart-c6311b94-8c0f-4ca0-b7b7-4cc398cb2ed9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2287179443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2287179443
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1516307234
Short name T32
Test name
Test status
Simulation time 10761768 ps
CPU time 0.36 seconds
Started Sep 27 12:39:21 PM PDT 23
Finished Sep 27 12:39:22 PM PDT 23
Peak memory 145392 kb
Host smart-57ba8b2f-bc76-4ca5-a18c-db893e2db9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516307234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1516307234
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2530529596
Short name T43
Test name
Test status
Simulation time 10871479 ps
CPU time 0.37 seconds
Started Sep 27 12:31:07 PM PDT 23
Finished Sep 27 12:31:07 PM PDT 23
Peak memory 145376 kb
Host smart-2a017fe7-8960-4e8e-a4dd-e3ed7a41b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530529596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2530529596
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1034265476
Short name T44
Test name
Test status
Simulation time 11562967 ps
CPU time 0.4 seconds
Started Sep 27 12:31:44 PM PDT 23
Finished Sep 27 12:31:45 PM PDT 23
Peak memory 145468 kb
Host smart-58c0853e-e6ea-4ba5-a26e-36327dbc3a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034265476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1034265476
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1342614608
Short name T10
Test name
Test status
Simulation time 12280473 ps
CPU time 0.39 seconds
Started Sep 27 12:30:29 PM PDT 23
Finished Sep 27 12:30:29 PM PDT 23
Peak memory 145400 kb
Host smart-de2e8397-3626-4782-831b-17931b2f78d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342614608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1342614608
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.385367773
Short name T14
Test name
Test status
Simulation time 11189279 ps
CPU time 0.37 seconds
Started Sep 27 12:30:31 PM PDT 23
Finished Sep 27 12:30:32 PM PDT 23
Peak memory 145388 kb
Host smart-c86e522d-3980-4edc-b5c8-a8a67f17bad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385367773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.385367773
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2561090726
Short name T15
Test name
Test status
Simulation time 11999112 ps
CPU time 0.38 seconds
Started Sep 27 12:33:41 PM PDT 23
Finished Sep 27 12:33:41 PM PDT 23
Peak memory 145468 kb
Host smart-a85be1f9-c106-49cc-b954-d3083605d72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561090726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2561090726
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2278088584
Short name T11
Test name
Test status
Simulation time 10249889 ps
CPU time 0.37 seconds
Started Sep 27 12:32:20 PM PDT 23
Finished Sep 27 12:32:20 PM PDT 23
Peak memory 145476 kb
Host smart-67c47b45-855b-4dae-a30b-663e284fd906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278088584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2278088584
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2834434518
Short name T16
Test name
Test status
Simulation time 10279389 ps
CPU time 0.37 seconds
Started Sep 27 12:43:07 PM PDT 23
Finished Sep 27 12:43:07 PM PDT 23
Peak memory 145504 kb
Host smart-8063bb2c-e6ff-4549-afcc-5ebec989a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834434518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2834434518
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3706441694
Short name T8
Test name
Test status
Simulation time 12070817 ps
CPU time 0.38 seconds
Started Sep 27 12:32:17 PM PDT 23
Finished Sep 27 12:32:18 PM PDT 23
Peak memory 145424 kb
Host smart-c04e27ab-12ad-4b57-baaa-ab520a402f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706441694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3706441694
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3810258824
Short name T7
Test name
Test status
Simulation time 11806492 ps
CPU time 0.39 seconds
Started Sep 27 12:40:17 PM PDT 23
Finished Sep 27 12:40:17 PM PDT 23
Peak memory 145564 kb
Host smart-927ab9b9-0c66-477e-b819-a70300c9b0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810258824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3810258824
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3562768870
Short name T12
Test name
Test status
Simulation time 13261738 ps
CPU time 0.38 seconds
Started Sep 27 12:41:44 PM PDT 23
Finished Sep 27 12:41:45 PM PDT 23
Peak memory 145408 kb
Host smart-0ef45c74-e38d-4fb8-9f3d-39446a737e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562768870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3562768870
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.160529734
Short name T3
Test name
Test status
Simulation time 10821192 ps
CPU time 0.39 seconds
Started Sep 27 12:33:07 PM PDT 23
Finished Sep 27 12:33:07 PM PDT 23
Peak memory 145432 kb
Host smart-47e03dff-c38f-4e10-b9eb-206f64214d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160529734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.160529734
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1902940849
Short name T1
Test name
Test status
Simulation time 11009746 ps
CPU time 0.38 seconds
Started Sep 27 12:38:20 PM PDT 23
Finished Sep 27 12:38:21 PM PDT 23
Peak memory 145392 kb
Host smart-fcf78671-263b-44aa-8f59-e59326d5039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902940849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1902940849
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.4283705723
Short name T18
Test name
Test status
Simulation time 10563743 ps
CPU time 0.41 seconds
Started Sep 27 12:50:06 PM PDT 23
Finished Sep 27 12:50:07 PM PDT 23
Peak memory 145460 kb
Host smart-80f74176-1d60-4aad-993e-1f0efb5f3afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283705723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.4283705723
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1555391368
Short name T42
Test name
Test status
Simulation time 11467496 ps
CPU time 0.38 seconds
Started Sep 27 12:37:11 PM PDT 23
Finished Sep 27 12:37:12 PM PDT 23
Peak memory 145404 kb
Host smart-0b99b8ee-b1b7-4156-aa09-697b37bdc65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555391368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1555391368
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.190970422
Short name T20
Test name
Test status
Simulation time 11055484 ps
CPU time 0.38 seconds
Started Sep 27 12:39:26 PM PDT 23
Finished Sep 27 12:39:27 PM PDT 23
Peak memory 145492 kb
Host smart-12465d6e-5fd9-4c40-a2e4-b4d284f9c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190970422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.190970422
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.4102649499
Short name T19
Test name
Test status
Simulation time 11621325 ps
CPU time 0.39 seconds
Started Sep 27 12:45:42 PM PDT 23
Finished Sep 27 12:45:42 PM PDT 23
Peak memory 145440 kb
Host smart-5c0b80a0-d5ed-48dd-a295-ee81a349753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102649499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.4102649499
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.2667071876
Short name T17
Test name
Test status
Simulation time 10335554 ps
CPU time 0.38 seconds
Started Sep 27 12:43:23 PM PDT 23
Finished Sep 27 12:43:23 PM PDT 23
Peak memory 145412 kb
Host smart-b2fd7652-53da-4262-9f1a-96acf84648b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667071876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2667071876
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2578916441
Short name T53
Test name
Test status
Simulation time 29626967 ps
CPU time 0.4 seconds
Started Sep 27 12:56:49 PM PDT 23
Finished Sep 27 12:56:50 PM PDT 23
Peak memory 145588 kb
Host smart-69eb565f-967d-4cf1-971c-1805ea57019b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2578916441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2578916441
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2650710597
Short name T52
Test name
Test status
Simulation time 29157620 ps
CPU time 0.46 seconds
Started Sep 27 12:56:39 PM PDT 23
Finished Sep 27 12:56:40 PM PDT 23
Peak memory 145576 kb
Host smart-0f87f41e-c972-4023-a466-f982ef79c4e2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2650710597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2650710597
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3190664854
Short name T33
Test name
Test status
Simulation time 29974540 ps
CPU time 0.45 seconds
Started Sep 27 12:56:40 PM PDT 23
Finished Sep 27 12:56:41 PM PDT 23
Peak memory 145604 kb
Host smart-a2a91ca0-a590-4761-a4ea-6d5b112b2276
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3190664854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3190664854
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.338058249
Short name T49
Test name
Test status
Simulation time 32558252 ps
CPU time 0.41 seconds
Started Sep 27 12:56:51 PM PDT 23
Finished Sep 27 12:56:52 PM PDT 23
Peak memory 145588 kb
Host smart-1dee7a49-0d4a-42db-8f8e-90de0c404768
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=338058249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.338058249
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3396465894
Short name T46
Test name
Test status
Simulation time 33599088 ps
CPU time 0.39 seconds
Started Sep 27 12:56:48 PM PDT 23
Finished Sep 27 12:56:49 PM PDT 23
Peak memory 145556 kb
Host smart-8dedf2a2-8a73-4ad0-a50f-3ff5dfaca306
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3396465894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3396465894
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4039518182
Short name T40
Test name
Test status
Simulation time 31463489 ps
CPU time 0.4 seconds
Started Sep 27 12:56:49 PM PDT 23
Finished Sep 27 12:56:50 PM PDT 23
Peak memory 145124 kb
Host smart-8863bb38-1ddd-4150-9bdc-f7a2cabc42e4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4039518182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4039518182
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.4229651480
Short name T47
Test name
Test status
Simulation time 29249121 ps
CPU time 0.39 seconds
Started Sep 27 12:56:44 PM PDT 23
Finished Sep 27 12:56:45 PM PDT 23
Peak memory 145596 kb
Host smart-d0ba2265-81fa-4db8-8a88-fd9b6c02f3bc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4229651480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.4229651480
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2054816675
Short name T37
Test name
Test status
Simulation time 29916641 ps
CPU time 0.42 seconds
Started Sep 27 12:56:41 PM PDT 23
Finished Sep 27 12:56:41 PM PDT 23
Peak memory 145676 kb
Host smart-b6102056-4113-48f5-bd66-e206b875a34a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2054816675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2054816675
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1636187242
Short name T35
Test name
Test status
Simulation time 32153208 ps
CPU time 0.4 seconds
Started Sep 27 12:56:48 PM PDT 23
Finished Sep 27 12:56:49 PM PDT 23
Peak memory 145564 kb
Host smart-df7d7a50-3749-4124-a951-32c058bc3bf9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1636187242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1636187242
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3086274228
Short name T51
Test name
Test status
Simulation time 29777153 ps
CPU time 0.42 seconds
Started Sep 27 12:56:50 PM PDT 23
Finished Sep 27 12:56:51 PM PDT 23
Peak memory 145564 kb
Host smart-670d201d-fcfc-42cb-9d18-9f840c52a8af
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3086274228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3086274228
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1767943036
Short name T41
Test name
Test status
Simulation time 29751860 ps
CPU time 0.41 seconds
Started Sep 27 12:56:49 PM PDT 23
Finished Sep 27 12:56:50 PM PDT 23
Peak memory 145396 kb
Host smart-c834f401-368d-4990-8838-2a62011907da
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1767943036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1767943036
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2584172232
Short name T50
Test name
Test status
Simulation time 28515976 ps
CPU time 0.39 seconds
Started Sep 27 12:56:38 PM PDT 23
Finished Sep 27 12:56:39 PM PDT 23
Peak memory 145592 kb
Host smart-427e2293-0ada-4d79-a5c6-86fb3fc0caca
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2584172232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2584172232
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1072931677
Short name T34
Test name
Test status
Simulation time 30773639 ps
CPU time 0.39 seconds
Started Sep 27 12:56:49 PM PDT 23
Finished Sep 27 12:56:50 PM PDT 23
Peak memory 145396 kb
Host smart-48187e6c-3720-4394-9ae8-8044b0877032
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1072931677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1072931677
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.797509809
Short name T45
Test name
Test status
Simulation time 28832728 ps
CPU time 0.41 seconds
Started Sep 27 12:56:49 PM PDT 23
Finished Sep 27 12:56:50 PM PDT 23
Peak memory 145088 kb
Host smart-f722e1db-6cde-4659-8aa3-f33537439f52
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=797509809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.797509809
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3195182551
Short name T48
Test name
Test status
Simulation time 28472223 ps
CPU time 0.39 seconds
Started Sep 27 12:56:36 PM PDT 23
Finished Sep 27 12:56:36 PM PDT 23
Peak memory 145664 kb
Host smart-c9ef36ba-d61c-4b4a-89e5-60d2eabbc654
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3195182551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3195182551
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2570883828
Short name T36
Test name
Test status
Simulation time 31044378 ps
CPU time 0.42 seconds
Started Sep 27 12:56:37 PM PDT 23
Finished Sep 27 12:56:37 PM PDT 23
Peak memory 145632 kb
Host smart-3143672e-a900-4ad1-8de8-bdfeb890d1ce
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2570883828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2570883828
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.149924227
Short name T38
Test name
Test status
Simulation time 29715786 ps
CPU time 0.4 seconds
Started Sep 27 12:56:59 PM PDT 23
Finished Sep 27 12:57:00 PM PDT 23
Peak memory 145556 kb
Host smart-e9874649-a238-425b-a7e2-516318278a32
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=149924227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.149924227
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1141811453
Short name T29
Test name
Test status
Simulation time 9573553 ps
CPU time 0.42 seconds
Started Sep 27 12:19:28 PM PDT 23
Finished Sep 27 12:19:29 PM PDT 23
Peak memory 144960 kb
Host smart-71ea8e4b-4d50-48ad-9db7-8884072041aa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1141811453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1141811453
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3629326109
Short name T61
Test name
Test status
Simulation time 9000145 ps
CPU time 0.38 seconds
Started Sep 27 12:15:15 PM PDT 23
Finished Sep 27 12:15:16 PM PDT 23
Peak memory 145156 kb
Host smart-6ea9068e-4eff-49ab-a4bb-0441abfc9013
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3629326109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3629326109
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.439944424
Short name T25
Test name
Test status
Simulation time 8800704 ps
CPU time 0.38 seconds
Started Sep 27 12:13:39 PM PDT 23
Finished Sep 27 12:13:40 PM PDT 23
Peak memory 145120 kb
Host smart-88e5567e-ca2c-41d9-9813-07f83332870a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=439944424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.439944424
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.4039473763
Short name T54
Test name
Test status
Simulation time 8528417 ps
CPU time 0.45 seconds
Started Sep 27 12:17:30 PM PDT 23
Finished Sep 27 12:17:31 PM PDT 23
Peak memory 144944 kb
Host smart-934ecc19-63eb-4094-8af1-ac5d9eb4584d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4039473763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.4039473763
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.296185899
Short name T31
Test name
Test status
Simulation time 8233912 ps
CPU time 0.48 seconds
Started Sep 27 12:19:53 PM PDT 23
Finished Sep 27 12:19:55 PM PDT 23
Peak memory 144428 kb
Host smart-d9808e29-ac20-460e-9539-77208b65fca1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=296185899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.296185899
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3040740875
Short name T27
Test name
Test status
Simulation time 8548582 ps
CPU time 0.36 seconds
Started Sep 27 12:19:49 PM PDT 23
Finished Sep 27 12:19:49 PM PDT 23
Peak memory 144728 kb
Host smart-df22308a-f6bb-4822-8903-2e896579505b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3040740875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3040740875
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.3807035062
Short name T60
Test name
Test status
Simulation time 9637215 ps
CPU time 0.37 seconds
Started Sep 27 12:19:55 PM PDT 23
Finished Sep 27 12:19:56 PM PDT 23
Peak memory 144920 kb
Host smart-8daaae07-1d1c-4f8d-b513-3ef3a246de97
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3807035062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.3807035062
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2473165976
Short name T56
Test name
Test status
Simulation time 9427597 ps
CPU time 0.37 seconds
Started Sep 27 12:20:05 PM PDT 23
Finished Sep 27 12:20:06 PM PDT 23
Peak memory 144928 kb
Host smart-0e28e1eb-f765-4137-91bb-bddf6ac7c784
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2473165976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2473165976
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1497194828
Short name T22
Test name
Test status
Simulation time 8754770 ps
CPU time 0.37 seconds
Started Sep 27 12:19:54 PM PDT 23
Finished Sep 27 12:19:55 PM PDT 23
Peak memory 143968 kb
Host smart-1b0e0fdc-b619-4863-8821-7e6e82cfb61e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1497194828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1497194828
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.2529638414
Short name T57
Test name
Test status
Simulation time 9513070 ps
CPU time 0.43 seconds
Started Sep 27 12:19:53 PM PDT 23
Finished Sep 27 12:19:55 PM PDT 23
Peak memory 144912 kb
Host smart-316af717-f186-41dd-842a-350c4142d540
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2529638414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2529638414
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.339400887
Short name T28
Test name
Test status
Simulation time 9888065 ps
CPU time 0.4 seconds
Started Sep 27 12:12:49 PM PDT 23
Finished Sep 27 12:12:50 PM PDT 23
Peak memory 145120 kb
Host smart-e16e2878-8e12-4589-9e64-f175a9c23aed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=339400887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.339400887
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.470612843
Short name T23
Test name
Test status
Simulation time 8836789 ps
CPU time 0.39 seconds
Started Sep 27 12:12:48 PM PDT 23
Finished Sep 27 12:12:49 PM PDT 23
Peak memory 145120 kb
Host smart-402b5aec-9d61-4e39-82a8-def0a1edc2aa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=470612843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.470612843
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1799225928
Short name T55
Test name
Test status
Simulation time 9434337 ps
CPU time 0.41 seconds
Started Sep 27 12:12:49 PM PDT 23
Finished Sep 27 12:12:50 PM PDT 23
Peak memory 145116 kb
Host smart-7330b262-9157-4781-934c-d74758f135d0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1799225928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1799225928
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.949327154
Short name T21
Test name
Test status
Simulation time 8725055 ps
CPU time 0.38 seconds
Started Sep 27 12:24:25 PM PDT 23
Finished Sep 27 12:24:27 PM PDT 23
Peak memory 144944 kb
Host smart-15fae48f-3222-4785-a94c-24493672db15
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=949327154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.949327154
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.495838104
Short name T24
Test name
Test status
Simulation time 8442054 ps
CPU time 0.37 seconds
Started Sep 27 12:20:09 PM PDT 23
Finished Sep 27 12:20:09 PM PDT 23
Peak memory 144932 kb
Host smart-aea1d0cd-9263-41a8-9ddd-a00394087bb0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=495838104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.495838104
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3120022783
Short name T58
Test name
Test status
Simulation time 8541703 ps
CPU time 0.4 seconds
Started Sep 27 12:12:49 PM PDT 23
Finished Sep 27 12:12:49 PM PDT 23
Peak memory 145116 kb
Host smart-48882e57-32b9-4a20-bba5-6b468809f974
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3120022783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3120022783
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3164220092
Short name T62
Test name
Test status
Simulation time 8937242 ps
CPU time 0.37 seconds
Started Sep 27 12:19:27 PM PDT 23
Finished Sep 27 12:19:27 PM PDT 23
Peak memory 144748 kb
Host smart-b7036dcd-df89-42cf-b900-321a9851672e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3164220092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3164220092
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3688639033
Short name T59
Test name
Test status
Simulation time 8922638 ps
CPU time 0.38 seconds
Started Sep 27 12:19:21 PM PDT 23
Finished Sep 27 12:19:22 PM PDT 23
Peak memory 144784 kb
Host smart-824ecfe9-244e-40dc-8ff2-67d2f567647a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3688639033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3688639033
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.3873844342
Short name T30
Test name
Test status
Simulation time 9992820 ps
CPU time 0.36 seconds
Started Sep 27 12:20:08 PM PDT 23
Finished Sep 27 12:20:09 PM PDT 23
Peak memory 144928 kb
Host smart-34df2b8c-c86a-4f36-b5f9-fd5eb0f8dc9d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3873844342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3873844342
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2210565861
Short name T79
Test name
Test status
Simulation time 28905795 ps
CPU time 0.39 seconds
Started Sep 27 12:58:15 PM PDT 23
Finished Sep 27 12:58:16 PM PDT 23
Peak memory 145012 kb
Host smart-150d8e9a-5a5b-4f6a-bfab-69e7973e8397
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2210565861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2210565861
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2992945818
Short name T69
Test name
Test status
Simulation time 26777565 ps
CPU time 0.4 seconds
Started Sep 27 12:58:07 PM PDT 23
Finished Sep 27 12:58:07 PM PDT 23
Peak memory 145012 kb
Host smart-2b02a038-2b6e-43e6-b49f-3d47e572008f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2992945818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2992945818
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.1118441326
Short name T6
Test name
Test status
Simulation time 26337164 ps
CPU time 0.38 seconds
Started Sep 27 12:58:11 PM PDT 23
Finished Sep 27 12:58:12 PM PDT 23
Peak memory 145004 kb
Host smart-dadd4b9f-e1df-4a67-9a2f-369cc3c112d7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1118441326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.1118441326
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.2097024683
Short name T67
Test name
Test status
Simulation time 28117578 ps
CPU time 0.39 seconds
Started Sep 27 12:58:23 PM PDT 23
Finished Sep 27 12:58:24 PM PDT 23
Peak memory 144968 kb
Host smart-a61941aa-3f38-4cb9-aab7-bc3accc4fd5f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2097024683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.2097024683
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3349483333
Short name T5
Test name
Test status
Simulation time 28292160 ps
CPU time 0.42 seconds
Started Sep 27 12:58:36 PM PDT 23
Finished Sep 27 12:58:37 PM PDT 23
Peak memory 145000 kb
Host smart-ef90602e-b533-4ab1-97fa-efe517bc4e28
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3349483333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3349483333
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2271965414
Short name T74
Test name
Test status
Simulation time 28529290 ps
CPU time 0.4 seconds
Started Sep 27 12:58:22 PM PDT 23
Finished Sep 27 12:58:33 PM PDT 23
Peak memory 145000 kb
Host smart-a1e366ba-82b8-4bd5-9875-377de1f38118
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2271965414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2271965414
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2718186627
Short name T63
Test name
Test status
Simulation time 26798792 ps
CPU time 0.38 seconds
Started Sep 27 12:58:07 PM PDT 23
Finished Sep 27 12:58:08 PM PDT 23
Peak memory 144968 kb
Host smart-b149c070-3686-4fdb-bead-9b86ff58b6ca
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2718186627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2718186627
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.3105133984
Short name T76
Test name
Test status
Simulation time 27516863 ps
CPU time 0.38 seconds
Started Sep 27 12:58:09 PM PDT 23
Finished Sep 27 12:58:10 PM PDT 23
Peak memory 144988 kb
Host smart-16f29560-6f59-4f9b-b214-61ef8567daea
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3105133984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.3105133984
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2188261493
Short name T68
Test name
Test status
Simulation time 25412024 ps
CPU time 0.4 seconds
Started Sep 27 12:58:48 PM PDT 23
Finished Sep 27 12:58:49 PM PDT 23
Peak memory 145060 kb
Host smart-97f3b9be-c25b-4890-87cd-00db1b1af737
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2188261493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2188261493
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1732898272
Short name T77
Test name
Test status
Simulation time 28617064 ps
CPU time 0.43 seconds
Started Sep 27 12:58:15 PM PDT 23
Finished Sep 27 12:58:16 PM PDT 23
Peak memory 145012 kb
Host smart-ca81ab8a-19aa-4ee3-8cf9-62888633038b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1732898272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1732898272
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3115807515
Short name T64
Test name
Test status
Simulation time 26196941 ps
CPU time 0.39 seconds
Started Sep 27 12:58:05 PM PDT 23
Finished Sep 27 12:58:06 PM PDT 23
Peak memory 145020 kb
Host smart-f390e12c-e65f-470f-bfa2-afcc3c858f57
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3115807515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3115807515
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.1699717403
Short name T73
Test name
Test status
Simulation time 26265178 ps
CPU time 0.38 seconds
Started Sep 27 12:58:02 PM PDT 23
Finished Sep 27 12:58:03 PM PDT 23
Peak memory 145048 kb
Host smart-7c9c454a-2b24-4ad6-97d5-fe14fd2bbb81
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1699717403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.1699717403
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.713991376
Short name T65
Test name
Test status
Simulation time 27631358 ps
CPU time 0.42 seconds
Started Sep 27 12:58:12 PM PDT 23
Finished Sep 27 12:58:13 PM PDT 23
Peak memory 144968 kb
Host smart-5b18052d-357f-49c9-ab1e-c35a209c21c5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=713991376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.713991376
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1542943718
Short name T72
Test name
Test status
Simulation time 27731641 ps
CPU time 0.4 seconds
Started Sep 27 12:58:15 PM PDT 23
Finished Sep 27 12:58:16 PM PDT 23
Peak memory 144952 kb
Host smart-eb9cdb31-bdf6-45ae-ae99-318c6aaae8ff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1542943718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1542943718
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.20024259
Short name T78
Test name
Test status
Simulation time 28330019 ps
CPU time 0.38 seconds
Started Sep 27 12:58:45 PM PDT 23
Finished Sep 27 12:58:46 PM PDT 23
Peak memory 144972 kb
Host smart-0029eaf5-5656-4149-af4b-2ac8e0cebd59
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=20024259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.20024259
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2403812254
Short name T71
Test name
Test status
Simulation time 29263254 ps
CPU time 0.43 seconds
Started Sep 27 12:57:55 PM PDT 23
Finished Sep 27 12:57:55 PM PDT 23
Peak memory 144964 kb
Host smart-b33f832f-b7f8-4ec0-8c84-fb47bcb35131
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2403812254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2403812254
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3590947696
Short name T75
Test name
Test status
Simulation time 27624154 ps
CPU time 0.38 seconds
Started Sep 27 12:58:14 PM PDT 23
Finished Sep 27 12:58:14 PM PDT 23
Peak memory 145076 kb
Host smart-bfa19d0a-0408-4996-87b9-e8b2eceb0657
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3590947696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3590947696
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.804007178
Short name T70
Test name
Test status
Simulation time 27022302 ps
CPU time 0.39 seconds
Started Sep 27 12:58:44 PM PDT 23
Finished Sep 27 12:58:45 PM PDT 23
Peak memory 144992 kb
Host smart-9ec4e464-fe54-480c-b812-1bbc127d2bb8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=804007178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.804007178
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3442750858
Short name T66
Test name
Test status
Simulation time 26887516 ps
CPU time 0.38 seconds
Started Sep 27 12:58:49 PM PDT 23
Finished Sep 27 12:58:49 PM PDT 23
Peak memory 145012 kb
Host smart-71c0b890-df6a-4cec-90c1-78e785023c3c
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3442750858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3442750858
Directory /workspace/9.prim_sync_fatal_alert/latest
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