Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.51 89.51 100.00 100.00 91.67 91.67 100.00 100.00 82.14 82.14 95.83 95.83 67.44 67.44 /workspace/coverage/default/12.prim_async_alert.406597710
92.64 3.13 100.00 0.00 91.67 0.00 100.00 0.00 89.29 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/18.prim_sync_alert.352142973
94.50 1.86 100.00 0.00 95.83 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2201286510
95.19 0.69 100.00 0.00 100.00 4.17 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1960903598

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.4153116686
/workspace/coverage/default/1.prim_async_alert.2275886674
/workspace/coverage/default/10.prim_async_alert.478001313
/workspace/coverage/default/11.prim_async_alert.48870126
/workspace/coverage/default/13.prim_async_alert.1481897649
/workspace/coverage/default/14.prim_async_alert.1374605829
/workspace/coverage/default/15.prim_async_alert.739424789
/workspace/coverage/default/16.prim_async_alert.665795118
/workspace/coverage/default/17.prim_async_alert.3688498926
/workspace/coverage/default/18.prim_async_alert.3383822218
/workspace/coverage/default/19.prim_async_alert.238272284
/workspace/coverage/default/2.prim_async_alert.2742105269
/workspace/coverage/default/3.prim_async_alert.3219371425
/workspace/coverage/default/4.prim_async_alert.1448345984
/workspace/coverage/default/5.prim_async_alert.481292296
/workspace/coverage/default/6.prim_async_alert.3802975355
/workspace/coverage/default/7.prim_async_alert.2494589554
/workspace/coverage/default/8.prim_async_alert.3296067964
/workspace/coverage/default/9.prim_async_alert.3202956667
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3696466389
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2236424861
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1621974833
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4075274072
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3898360114
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.700925048
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1820561299
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3708273404
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3101125225
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1637327768
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1454094902
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1859618348
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1130802960
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3146044623
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2799520519
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2248429768
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3133972382
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3958827553
/workspace/coverage/sync_alert/0.prim_sync_alert.1593658872
/workspace/coverage/sync_alert/1.prim_sync_alert.3833827159
/workspace/coverage/sync_alert/10.prim_sync_alert.1046944823
/workspace/coverage/sync_alert/11.prim_sync_alert.2106432522
/workspace/coverage/sync_alert/12.prim_sync_alert.3374560358
/workspace/coverage/sync_alert/13.prim_sync_alert.1943490340
/workspace/coverage/sync_alert/14.prim_sync_alert.3609504970
/workspace/coverage/sync_alert/15.prim_sync_alert.73900447
/workspace/coverage/sync_alert/16.prim_sync_alert.2015193478
/workspace/coverage/sync_alert/17.prim_sync_alert.3257581074
/workspace/coverage/sync_alert/19.prim_sync_alert.1265283681
/workspace/coverage/sync_alert/2.prim_sync_alert.3442382817
/workspace/coverage/sync_alert/3.prim_sync_alert.407675151
/workspace/coverage/sync_alert/4.prim_sync_alert.2359985312
/workspace/coverage/sync_alert/5.prim_sync_alert.1230095035
/workspace/coverage/sync_alert/6.prim_sync_alert.2680824152
/workspace/coverage/sync_alert/7.prim_sync_alert.1212240537
/workspace/coverage/sync_alert/8.prim_sync_alert.1052974541
/workspace/coverage/sync_alert/9.prim_sync_alert.1102427712
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.927833813
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.884842250
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2699305725
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3759687365
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3223274574
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3784596429
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4081367550
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.121379678
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.295037840
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.61481329
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3386058026
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.54576385
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4044886051
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2641996345
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1659657022
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3942527248
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2586682789
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4076590391
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3344758044



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/17.prim_async_alert.3688498926 Oct 04 12:48:59 PM PDT 23 Oct 04 12:49:00 PM PDT 23 11700612 ps
T2 /workspace/coverage/default/16.prim_async_alert.665795118 Oct 04 12:22:10 PM PDT 23 Oct 04 12:22:10 PM PDT 23 11359876 ps
T3 /workspace/coverage/default/15.prim_async_alert.739424789 Oct 04 12:46:13 PM PDT 23 Oct 04 12:46:14 PM PDT 23 11069061 ps
T14 /workspace/coverage/default/14.prim_async_alert.1374605829 Oct 04 12:21:20 PM PDT 23 Oct 04 12:21:20 PM PDT 23 11435173 ps
T16 /workspace/coverage/default/2.prim_async_alert.2742105269 Oct 04 12:38:18 PM PDT 23 Oct 04 12:38:19 PM PDT 23 10901443 ps
T8 /workspace/coverage/default/8.prim_async_alert.3296067964 Oct 04 12:44:05 PM PDT 23 Oct 04 12:44:07 PM PDT 23 11639132 ps
T22 /workspace/coverage/default/18.prim_async_alert.3383822218 Oct 04 12:43:05 PM PDT 23 Oct 04 12:43:06 PM PDT 23 11670725 ps
T7 /workspace/coverage/default/4.prim_async_alert.1448345984 Oct 04 12:35:23 PM PDT 23 Oct 04 12:35:24 PM PDT 23 10525936 ps
T9 /workspace/coverage/default/13.prim_async_alert.1481897649 Oct 04 12:16:40 PM PDT 23 Oct 04 12:16:41 PM PDT 23 11499889 ps
T15 /workspace/coverage/default/12.prim_async_alert.406597710 Oct 04 12:34:33 PM PDT 23 Oct 04 12:34:34 PM PDT 23 11428885 ps
T19 /workspace/coverage/default/3.prim_async_alert.3219371425 Oct 04 12:21:12 PM PDT 23 Oct 04 12:21:12 PM PDT 23 11426802 ps
T10 /workspace/coverage/default/11.prim_async_alert.48870126 Oct 04 12:21:04 PM PDT 23 Oct 04 12:21:05 PM PDT 23 10356552 ps
T47 /workspace/coverage/default/7.prim_async_alert.2494589554 Oct 04 12:21:20 PM PDT 23 Oct 04 12:21:21 PM PDT 23 10557248 ps
T48 /workspace/coverage/default/19.prim_async_alert.238272284 Oct 04 12:19:43 PM PDT 23 Oct 04 12:19:43 PM PDT 23 12151230 ps
T20 /workspace/coverage/default/5.prim_async_alert.481292296 Oct 04 12:16:37 PM PDT 23 Oct 04 12:16:37 PM PDT 23 12585569 ps
T23 /workspace/coverage/default/9.prim_async_alert.3202956667 Oct 04 12:46:46 PM PDT 23 Oct 04 12:46:46 PM PDT 23 11160853 ps
T18 /workspace/coverage/default/6.prim_async_alert.3802975355 Oct 04 12:17:37 PM PDT 23 Oct 04 12:17:38 PM PDT 23 11241060 ps
T21 /workspace/coverage/default/10.prim_async_alert.478001313 Oct 04 12:21:11 PM PDT 23 Oct 04 12:21:12 PM PDT 23 10924420 ps
T24 /workspace/coverage/default/0.prim_async_alert.4153116686 Oct 04 12:40:56 PM PDT 23 Oct 04 12:40:56 PM PDT 23 10859849 ps
T25 /workspace/coverage/default/1.prim_async_alert.2275886674 Oct 04 12:38:18 PM PDT 23 Oct 04 12:38:19 PM PDT 23 11039146 ps
T37 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3146044623 Oct 04 12:42:57 PM PDT 23 Oct 04 12:42:58 PM PDT 23 31702861 ps
T38 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1859618348 Oct 04 12:16:45 PM PDT 23 Oct 04 12:16:46 PM PDT 23 31263495 ps
T39 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3101125225 Oct 04 12:27:35 PM PDT 23 Oct 04 12:27:36 PM PDT 23 29059473 ps
T40 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3898360114 Oct 04 12:23:02 PM PDT 23 Oct 04 12:23:03 PM PDT 23 30678529 ps
T41 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2201286510 Oct 04 12:23:50 PM PDT 23 Oct 04 12:23:51 PM PDT 23 32180207 ps
T42 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3133972382 Oct 04 12:38:49 PM PDT 23 Oct 04 12:38:49 PM PDT 23 30137275 ps
T43 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2799520519 Oct 04 12:21:05 PM PDT 23 Oct 04 12:21:06 PM PDT 23 30476574 ps
T44 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3708273404 Oct 04 12:29:55 PM PDT 23 Oct 04 12:29:56 PM PDT 23 30415226 ps
T45 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.700925048 Oct 04 12:17:41 PM PDT 23 Oct 04 12:17:43 PM PDT 23 30177149 ps
T46 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3958827553 Oct 04 12:21:30 PM PDT 23 Oct 04 12:21:31 PM PDT 23 29590796 ps
T4 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1820561299 Oct 04 12:39:43 PM PDT 23 Oct 04 12:39:44 PM PDT 23 29542231 ps
T49 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3696466389 Oct 04 12:19:56 PM PDT 23 Oct 04 12:19:57 PM PDT 23 30203286 ps
T50 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1130802960 Oct 04 12:39:13 PM PDT 23 Oct 04 12:39:13 PM PDT 23 31047578 ps
T51 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1454094902 Oct 04 12:16:35 PM PDT 23 Oct 04 12:16:36 PM PDT 23 32150940 ps
T52 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1621974833 Oct 04 12:28:38 PM PDT 23 Oct 04 12:28:39 PM PDT 23 30980377 ps
T5 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4075274072 Oct 04 12:39:42 PM PDT 23 Oct 04 12:39:43 PM PDT 23 27976719 ps
T53 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1637327768 Oct 04 12:16:36 PM PDT 23 Oct 04 12:16:37 PM PDT 23 27604492 ps
T36 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2236424861 Oct 04 12:26:28 PM PDT 23 Oct 04 12:26:28 PM PDT 23 30077640 ps
T54 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2248429768 Oct 04 12:47:26 PM PDT 23 Oct 04 12:47:27 PM PDT 23 30622341 ps
T26 /workspace/coverage/sync_alert/9.prim_sync_alert.1102427712 Oct 04 02:44:10 PM PDT 23 Oct 04 02:44:11 PM PDT 23 9405402 ps
T27 /workspace/coverage/sync_alert/18.prim_sync_alert.352142973 Oct 04 02:34:58 PM PDT 23 Oct 04 02:34:58 PM PDT 23 9834458 ps
T28 /workspace/coverage/sync_alert/2.prim_sync_alert.3442382817 Oct 04 02:46:57 PM PDT 23 Oct 04 02:46:58 PM PDT 23 9865737 ps
T29 /workspace/coverage/sync_alert/10.prim_sync_alert.1046944823 Oct 04 02:41:48 PM PDT 23 Oct 04 02:41:49 PM PDT 23 9831137 ps
T30 /workspace/coverage/sync_alert/16.prim_sync_alert.2015193478 Oct 04 02:34:59 PM PDT 23 Oct 04 02:35:00 PM PDT 23 8223979 ps
T31 /workspace/coverage/sync_alert/0.prim_sync_alert.1593658872 Oct 04 02:34:54 PM PDT 23 Oct 04 02:34:55 PM PDT 23 9526006 ps
T32 /workspace/coverage/sync_alert/3.prim_sync_alert.407675151 Oct 04 02:36:51 PM PDT 23 Oct 04 02:36:52 PM PDT 23 9153720 ps
T33 /workspace/coverage/sync_alert/17.prim_sync_alert.3257581074 Oct 04 02:35:00 PM PDT 23 Oct 04 02:35:01 PM PDT 23 9293308 ps
T34 /workspace/coverage/sync_alert/14.prim_sync_alert.3609504970 Oct 04 02:36:53 PM PDT 23 Oct 04 02:36:54 PM PDT 23 9538856 ps
T11 /workspace/coverage/sync_alert/13.prim_sync_alert.1943490340 Oct 04 02:40:49 PM PDT 23 Oct 04 02:40:49 PM PDT 23 9468344 ps
T35 /workspace/coverage/sync_alert/5.prim_sync_alert.1230095035 Oct 04 02:34:55 PM PDT 23 Oct 04 02:34:56 PM PDT 23 9439699 ps
T55 /workspace/coverage/sync_alert/15.prim_sync_alert.73900447 Oct 04 02:35:07 PM PDT 23 Oct 04 02:35:08 PM PDT 23 9047404 ps
T56 /workspace/coverage/sync_alert/6.prim_sync_alert.2680824152 Oct 04 02:34:55 PM PDT 23 Oct 04 02:34:56 PM PDT 23 9089211 ps
T57 /workspace/coverage/sync_alert/8.prim_sync_alert.1052974541 Oct 04 02:38:33 PM PDT 23 Oct 04 02:38:34 PM PDT 23 8567646 ps
T58 /workspace/coverage/sync_alert/4.prim_sync_alert.2359985312 Oct 04 02:34:55 PM PDT 23 Oct 04 02:34:55 PM PDT 23 9606424 ps
T59 /workspace/coverage/sync_alert/7.prim_sync_alert.1212240537 Oct 04 02:34:54 PM PDT 23 Oct 04 02:34:55 PM PDT 23 9408580 ps
T60 /workspace/coverage/sync_alert/12.prim_sync_alert.3374560358 Oct 04 02:39:32 PM PDT 23 Oct 04 02:39:32 PM PDT 23 8710227 ps
T61 /workspace/coverage/sync_alert/19.prim_sync_alert.1265283681 Oct 04 02:35:01 PM PDT 23 Oct 04 02:35:03 PM PDT 23 8464262 ps
T62 /workspace/coverage/sync_alert/1.prim_sync_alert.3833827159 Oct 04 02:36:51 PM PDT 23 Oct 04 02:36:52 PM PDT 23 10310075 ps
T63 /workspace/coverage/sync_alert/11.prim_sync_alert.2106432522 Oct 04 02:34:55 PM PDT 23 Oct 04 02:34:55 PM PDT 23 8932026 ps
T64 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2699305725 Oct 04 12:36:50 PM PDT 23 Oct 04 12:36:51 PM PDT 23 27340720 ps
T65 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4044886051 Oct 04 12:16:35 PM PDT 23 Oct 04 12:16:36 PM PDT 23 27044839 ps
T66 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3386058026 Oct 04 12:26:17 PM PDT 23 Oct 04 12:26:18 PM PDT 23 28357641 ps
T67 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2586682789 Oct 04 12:32:51 PM PDT 23 Oct 04 12:32:52 PM PDT 23 26201806 ps
T68 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.121379678 Oct 04 12:30:47 PM PDT 23 Oct 04 12:30:48 PM PDT 23 27582393 ps
T69 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.61481329 Oct 04 12:46:45 PM PDT 23 Oct 04 12:46:46 PM PDT 23 28794159 ps
T70 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4076590391 Oct 04 12:18:45 PM PDT 23 Oct 04 12:18:46 PM PDT 23 28226857 ps
T71 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3223274574 Oct 04 12:18:07 PM PDT 23 Oct 04 12:18:08 PM PDT 23 28121673 ps
T72 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3942527248 Oct 04 12:26:16 PM PDT 23 Oct 04 12:26:17 PM PDT 23 25630303 ps
T6 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.295037840 Oct 04 12:16:37 PM PDT 23 Oct 04 12:16:38 PM PDT 23 27056564 ps
T73 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.927833813 Oct 04 12:33:41 PM PDT 23 Oct 04 12:33:42 PM PDT 23 28709524 ps
T12 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1960903598 Oct 04 12:32:34 PM PDT 23 Oct 04 12:32:36 PM PDT 23 26332498 ps
T74 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3344758044 Oct 04 12:22:16 PM PDT 23 Oct 04 12:22:17 PM PDT 23 26328251 ps
T75 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1659657022 Oct 04 12:36:46 PM PDT 23 Oct 04 12:36:48 PM PDT 23 27553915 ps
T17 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3759687365 Oct 04 12:31:01 PM PDT 23 Oct 04 12:31:02 PM PDT 23 26978757 ps
T76 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2641996345 Oct 04 12:33:17 PM PDT 23 Oct 04 12:33:18 PM PDT 23 29073651 ps
T13 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4081367550 Oct 04 12:21:20 PM PDT 23 Oct 04 12:21:20 PM PDT 23 28512678 ps
T77 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.884842250 Oct 04 12:24:45 PM PDT 23 Oct 04 12:24:46 PM PDT 23 27269043 ps
T78 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3784596429 Oct 04 12:21:02 PM PDT 23 Oct 04 12:21:04 PM PDT 23 26400708 ps
T79 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.54576385 Oct 04 12:23:31 PM PDT 23 Oct 04 12:23:32 PM PDT 23 27141221 ps

Test location /workspace/coverage/default/12.prim_async_alert.406597710
Short name T15
Test name
Test status
Simulation time 11428885 ps
CPU time 0.38 seconds
Started Oct 04 12:34:33 PM PDT 23
Finished Oct 04 12:34:34 PM PDT 23
Peak memory 145488 kb
Host smart-0435822b-6d48-43e9-8d3a-22a572732f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406597710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.406597710
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.352142973
Short name T27
Test name
Test status
Simulation time 9834458 ps
CPU time 0.38 seconds
Started Oct 04 02:34:58 PM PDT 23
Finished Oct 04 02:34:58 PM PDT 23
Peak memory 145068 kb
Host smart-ee688a63-0b77-49fc-aac4-1931f33f7f40
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=352142973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.352142973
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2201286510
Short name T41
Test name
Test status
Simulation time 32180207 ps
CPU time 0.4 seconds
Started Oct 04 12:23:50 PM PDT 23
Finished Oct 04 12:23:51 PM PDT 23
Peak memory 145596 kb
Host smart-ce2a7907-4709-45ea-a116-d8f314d87cee
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2201286510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2201286510
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1960903598
Short name T12
Test name
Test status
Simulation time 26332498 ps
CPU time 0.5 seconds
Started Oct 04 12:32:34 PM PDT 23
Finished Oct 04 12:32:36 PM PDT 23
Peak memory 142936 kb
Host smart-e9a61fb9-68ac-4e0b-ad76-a9f49094d3e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1960903598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1960903598
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.4153116686
Short name T24
Test name
Test status
Simulation time 10859849 ps
CPU time 0.4 seconds
Started Oct 04 12:40:56 PM PDT 23
Finished Oct 04 12:40:56 PM PDT 23
Peak memory 145608 kb
Host smart-088e32fd-cc17-4997-a957-b6eb40017a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153116686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4153116686
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2275886674
Short name T25
Test name
Test status
Simulation time 11039146 ps
CPU time 0.37 seconds
Started Oct 04 12:38:18 PM PDT 23
Finished Oct 04 12:38:19 PM PDT 23
Peak memory 145376 kb
Host smart-73c275f0-8da7-45bc-958e-03098083eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275886674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2275886674
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.478001313
Short name T21
Test name
Test status
Simulation time 10924420 ps
CPU time 0.39 seconds
Started Oct 04 12:21:11 PM PDT 23
Finished Oct 04 12:21:12 PM PDT 23
Peak memory 145504 kb
Host smart-5f4d6bb1-5fd7-49aa-8dc9-67461ff61c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478001313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.478001313
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.48870126
Short name T10
Test name
Test status
Simulation time 10356552 ps
CPU time 0.38 seconds
Started Oct 04 12:21:04 PM PDT 23
Finished Oct 04 12:21:05 PM PDT 23
Peak memory 145088 kb
Host smart-d1c8894c-e9fc-495c-9a07-6b21f62bee6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48870126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.48870126
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1481897649
Short name T9
Test name
Test status
Simulation time 11499889 ps
CPU time 0.39 seconds
Started Oct 04 12:16:40 PM PDT 23
Finished Oct 04 12:16:41 PM PDT 23
Peak memory 145608 kb
Host smart-eef32f47-30ed-40cd-832b-66012b12aca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481897649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1481897649
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1374605829
Short name T14
Test name
Test status
Simulation time 11435173 ps
CPU time 0.39 seconds
Started Oct 04 12:21:20 PM PDT 23
Finished Oct 04 12:21:20 PM PDT 23
Peak memory 145344 kb
Host smart-1f0f3357-0129-4788-a89d-a18ead8a8ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374605829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1374605829
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.739424789
Short name T3
Test name
Test status
Simulation time 11069061 ps
CPU time 0.38 seconds
Started Oct 04 12:46:13 PM PDT 23
Finished Oct 04 12:46:14 PM PDT 23
Peak memory 145444 kb
Host smart-1851a35d-ab70-4a27-a5e5-38f7714bd0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739424789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.739424789
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.665795118
Short name T2
Test name
Test status
Simulation time 11359876 ps
CPU time 0.39 seconds
Started Oct 04 12:22:10 PM PDT 23
Finished Oct 04 12:22:10 PM PDT 23
Peak memory 145356 kb
Host smart-1068d8ca-5cd0-4aed-8a70-6b57098192f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665795118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.665795118
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.3688498926
Short name T1
Test name
Test status
Simulation time 11700612 ps
CPU time 0.38 seconds
Started Oct 04 12:48:59 PM PDT 23
Finished Oct 04 12:49:00 PM PDT 23
Peak memory 145464 kb
Host smart-87d0106a-4bf9-4e69-bf12-be46b41d1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688498926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3688498926
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.3383822218
Short name T22
Test name
Test status
Simulation time 11670725 ps
CPU time 0.37 seconds
Started Oct 04 12:43:05 PM PDT 23
Finished Oct 04 12:43:06 PM PDT 23
Peak memory 144896 kb
Host smart-9840e121-bd4b-4672-91c0-25814a49bd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383822218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3383822218
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.238272284
Short name T48
Test name
Test status
Simulation time 12151230 ps
CPU time 0.39 seconds
Started Oct 04 12:19:43 PM PDT 23
Finished Oct 04 12:19:43 PM PDT 23
Peak memory 145492 kb
Host smart-494d8cf9-4857-45be-b202-a450ca805071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238272284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.238272284
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2742105269
Short name T16
Test name
Test status
Simulation time 10901443 ps
CPU time 0.38 seconds
Started Oct 04 12:38:18 PM PDT 23
Finished Oct 04 12:38:19 PM PDT 23
Peak memory 145376 kb
Host smart-c4afc085-473d-44d1-b341-4115e47f5c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742105269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2742105269
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3219371425
Short name T19
Test name
Test status
Simulation time 11426802 ps
CPU time 0.4 seconds
Started Oct 04 12:21:12 PM PDT 23
Finished Oct 04 12:21:12 PM PDT 23
Peak memory 145344 kb
Host smart-431f53b1-6744-4d87-bd6e-edb4900de2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219371425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3219371425
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1448345984
Short name T7
Test name
Test status
Simulation time 10525936 ps
CPU time 0.41 seconds
Started Oct 04 12:35:23 PM PDT 23
Finished Oct 04 12:35:24 PM PDT 23
Peak memory 145480 kb
Host smart-fae5e121-f7c9-4d64-8d8b-1d98d8c1e76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448345984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1448345984
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.481292296
Short name T20
Test name
Test status
Simulation time 12585569 ps
CPU time 0.43 seconds
Started Oct 04 12:16:37 PM PDT 23
Finished Oct 04 12:16:37 PM PDT 23
Peak memory 145864 kb
Host smart-558ba76c-567e-4b82-bde0-59d2ecf38f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481292296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.481292296
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3802975355
Short name T18
Test name
Test status
Simulation time 11241060 ps
CPU time 0.37 seconds
Started Oct 04 12:17:37 PM PDT 23
Finished Oct 04 12:17:38 PM PDT 23
Peak memory 145444 kb
Host smart-76079218-f082-4c70-8ac1-5ddb208b982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802975355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3802975355
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2494589554
Short name T47
Test name
Test status
Simulation time 10557248 ps
CPU time 0.38 seconds
Started Oct 04 12:21:20 PM PDT 23
Finished Oct 04 12:21:21 PM PDT 23
Peak memory 145344 kb
Host smart-949c2aa6-e0c9-4d22-88a3-f10200752eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494589554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2494589554
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3296067964
Short name T8
Test name
Test status
Simulation time 11639132 ps
CPU time 0.4 seconds
Started Oct 04 12:44:05 PM PDT 23
Finished Oct 04 12:44:07 PM PDT 23
Peak memory 145492 kb
Host smart-85e00cdd-b092-47bf-a3c8-cf423c168248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296067964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3296067964
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3202956667
Short name T23
Test name
Test status
Simulation time 11160853 ps
CPU time 0.38 seconds
Started Oct 04 12:46:46 PM PDT 23
Finished Oct 04 12:46:46 PM PDT 23
Peak memory 145556 kb
Host smart-219658ac-3c0e-4cbb-883b-dfa1afa4d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202956667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3202956667
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3696466389
Short name T49
Test name
Test status
Simulation time 30203286 ps
CPU time 0.41 seconds
Started Oct 04 12:19:56 PM PDT 23
Finished Oct 04 12:19:57 PM PDT 23
Peak memory 145476 kb
Host smart-6d3c3529-5544-4670-9001-bf0f47493fe4
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3696466389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3696466389
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2236424861
Short name T36
Test name
Test status
Simulation time 30077640 ps
CPU time 0.41 seconds
Started Oct 04 12:26:28 PM PDT 23
Finished Oct 04 12:26:28 PM PDT 23
Peak memory 145752 kb
Host smart-65a19c56-d7cf-4a69-8546-d6175dd1599a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2236424861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2236424861
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1621974833
Short name T52
Test name
Test status
Simulation time 30980377 ps
CPU time 0.41 seconds
Started Oct 04 12:28:38 PM PDT 23
Finished Oct 04 12:28:39 PM PDT 23
Peak memory 145568 kb
Host smart-44cdcebe-0aa6-460d-b3f2-0ed3847c4e71
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1621974833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1621974833
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4075274072
Short name T5
Test name
Test status
Simulation time 27976719 ps
CPU time 0.43 seconds
Started Oct 04 12:39:42 PM PDT 23
Finished Oct 04 12:39:43 PM PDT 23
Peak memory 145612 kb
Host smart-147f3b80-d7d5-4d64-9a19-9edc2c3cb884
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4075274072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.4075274072
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3898360114
Short name T40
Test name
Test status
Simulation time 30678529 ps
CPU time 0.41 seconds
Started Oct 04 12:23:02 PM PDT 23
Finished Oct 04 12:23:03 PM PDT 23
Peak memory 145528 kb
Host smart-b0d2f242-fc36-4020-b992-c23f3c60fbbc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3898360114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3898360114
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.700925048
Short name T45
Test name
Test status
Simulation time 30177149 ps
CPU time 0.44 seconds
Started Oct 04 12:17:41 PM PDT 23
Finished Oct 04 12:17:43 PM PDT 23
Peak memory 145464 kb
Host smart-895188b8-2b4c-48c9-b16b-5e6cda640bed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=700925048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.700925048
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1820561299
Short name T4
Test name
Test status
Simulation time 29542231 ps
CPU time 0.4 seconds
Started Oct 04 12:39:43 PM PDT 23
Finished Oct 04 12:39:44 PM PDT 23
Peak memory 145668 kb
Host smart-5af1ca6e-8402-4ea6-a997-643311e518b3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1820561299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1820561299
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3708273404
Short name T44
Test name
Test status
Simulation time 30415226 ps
CPU time 0.45 seconds
Started Oct 04 12:29:55 PM PDT 23
Finished Oct 04 12:29:56 PM PDT 23
Peak memory 145608 kb
Host smart-7a5eca0f-f8cd-4809-b2ec-6766ed079cea
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3708273404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3708273404
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3101125225
Short name T39
Test name
Test status
Simulation time 29059473 ps
CPU time 0.42 seconds
Started Oct 04 12:27:35 PM PDT 23
Finished Oct 04 12:27:36 PM PDT 23
Peak memory 145596 kb
Host smart-568a434a-5365-4989-b865-3295cbb188dd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3101125225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3101125225
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1637327768
Short name T53
Test name
Test status
Simulation time 27604492 ps
CPU time 0.39 seconds
Started Oct 04 12:16:36 PM PDT 23
Finished Oct 04 12:16:37 PM PDT 23
Peak memory 145636 kb
Host smart-97ff41bc-9e8a-48a7-8740-784872bc9b8e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1637327768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1637327768
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.1454094902
Short name T51
Test name
Test status
Simulation time 32150940 ps
CPU time 0.38 seconds
Started Oct 04 12:16:35 PM PDT 23
Finished Oct 04 12:16:36 PM PDT 23
Peak memory 145692 kb
Host smart-7bf1a543-8629-4557-af6c-ef465fc252cc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1454094902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.1454094902
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1859618348
Short name T38
Test name
Test status
Simulation time 31263495 ps
CPU time 0.42 seconds
Started Oct 04 12:16:45 PM PDT 23
Finished Oct 04 12:16:46 PM PDT 23
Peak memory 145872 kb
Host smart-8e16e7bd-5544-4342-ad9f-621ae23c0614
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1859618348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1859618348
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1130802960
Short name T50
Test name
Test status
Simulation time 31047578 ps
CPU time 0.44 seconds
Started Oct 04 12:39:13 PM PDT 23
Finished Oct 04 12:39:13 PM PDT 23
Peak memory 145568 kb
Host smart-e6826492-a7fc-444a-a6f1-910cbcbd48e3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1130802960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1130802960
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3146044623
Short name T37
Test name
Test status
Simulation time 31702861 ps
CPU time 0.42 seconds
Started Oct 04 12:42:57 PM PDT 23
Finished Oct 04 12:42:58 PM PDT 23
Peak memory 145540 kb
Host smart-e6bbc2b0-e0e5-4fb4-85ea-17526e67d6a5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3146044623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3146044623
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2799520519
Short name T43
Test name
Test status
Simulation time 30476574 ps
CPU time 0.39 seconds
Started Oct 04 12:21:05 PM PDT 23
Finished Oct 04 12:21:06 PM PDT 23
Peak memory 145408 kb
Host smart-22945f88-a208-4a09-935e-17c9ccebafe1
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2799520519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2799520519
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2248429768
Short name T54
Test name
Test status
Simulation time 30622341 ps
CPU time 0.41 seconds
Started Oct 04 12:47:26 PM PDT 23
Finished Oct 04 12:47:27 PM PDT 23
Peak memory 145568 kb
Host smart-22d38fad-3596-4419-a6d8-ad6f38f56022
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2248429768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2248429768
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3133972382
Short name T42
Test name
Test status
Simulation time 30137275 ps
CPU time 0.4 seconds
Started Oct 04 12:38:49 PM PDT 23
Finished Oct 04 12:38:49 PM PDT 23
Peak memory 145636 kb
Host smart-659b7ea4-a69e-45a3-add3-824fb8dbcfba
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3133972382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3133972382
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3958827553
Short name T46
Test name
Test status
Simulation time 29590796 ps
CPU time 0.39 seconds
Started Oct 04 12:21:30 PM PDT 23
Finished Oct 04 12:21:31 PM PDT 23
Peak memory 145580 kb
Host smart-a858ce4c-796d-41fe-80f0-5845d7c0ebb3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3958827553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3958827553
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1593658872
Short name T31
Test name
Test status
Simulation time 9526006 ps
CPU time 0.38 seconds
Started Oct 04 02:34:54 PM PDT 23
Finished Oct 04 02:34:55 PM PDT 23
Peak memory 145072 kb
Host smart-0a798f3f-7f2e-4d2e-8ffe-0b8bc8f2eb5a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1593658872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1593658872
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3833827159
Short name T62
Test name
Test status
Simulation time 10310075 ps
CPU time 0.39 seconds
Started Oct 04 02:36:51 PM PDT 23
Finished Oct 04 02:36:52 PM PDT 23
Peak memory 145100 kb
Host smart-0b1762a1-b748-484f-8432-5b6f7a11cb3e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3833827159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3833827159
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.1046944823
Short name T29
Test name
Test status
Simulation time 9831137 ps
CPU time 0.42 seconds
Started Oct 04 02:41:48 PM PDT 23
Finished Oct 04 02:41:49 PM PDT 23
Peak memory 145092 kb
Host smart-f02c0550-4de5-4e5d-99fe-2998e165e9d3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1046944823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1046944823
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.2106432522
Short name T63
Test name
Test status
Simulation time 8932026 ps
CPU time 0.38 seconds
Started Oct 04 02:34:55 PM PDT 23
Finished Oct 04 02:34:55 PM PDT 23
Peak memory 145064 kb
Host smart-0f0f7480-c888-497f-93f3-47d5120ec21c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2106432522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.2106432522
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3374560358
Short name T60
Test name
Test status
Simulation time 8710227 ps
CPU time 0.37 seconds
Started Oct 04 02:39:32 PM PDT 23
Finished Oct 04 02:39:32 PM PDT 23
Peak memory 145064 kb
Host smart-d3747273-dbb5-42a8-80a7-6b300f7c9fad
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3374560358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3374560358
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.1943490340
Short name T11
Test name
Test status
Simulation time 9468344 ps
CPU time 0.37 seconds
Started Oct 04 02:40:49 PM PDT 23
Finished Oct 04 02:40:49 PM PDT 23
Peak memory 145072 kb
Host smart-c77b2cd9-3576-4e42-ac9f-492adc546e0a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1943490340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.1943490340
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3609504970
Short name T34
Test name
Test status
Simulation time 9538856 ps
CPU time 0.38 seconds
Started Oct 04 02:36:53 PM PDT 23
Finished Oct 04 02:36:54 PM PDT 23
Peak memory 145048 kb
Host smart-1a4e81b5-c4ec-49ff-babe-64ccd85f16bf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3609504970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3609504970
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.73900447
Short name T55
Test name
Test status
Simulation time 9047404 ps
CPU time 0.42 seconds
Started Oct 04 02:35:07 PM PDT 23
Finished Oct 04 02:35:08 PM PDT 23
Peak memory 145064 kb
Host smart-e3158720-ca7e-4c8c-b092-8d59024f37fb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=73900447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.73900447
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.2015193478
Short name T30
Test name
Test status
Simulation time 8223979 ps
CPU time 0.37 seconds
Started Oct 04 02:34:59 PM PDT 23
Finished Oct 04 02:35:00 PM PDT 23
Peak memory 145064 kb
Host smart-288e0426-d30c-42ff-97ff-da07a07ffdf8
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2015193478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2015193478
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.3257581074
Short name T33
Test name
Test status
Simulation time 9293308 ps
CPU time 0.39 seconds
Started Oct 04 02:35:00 PM PDT 23
Finished Oct 04 02:35:01 PM PDT 23
Peak memory 145160 kb
Host smart-d55b6a93-e331-4cc0-8a5c-5947ea86a2fa
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3257581074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3257581074
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1265283681
Short name T61
Test name
Test status
Simulation time 8464262 ps
CPU time 0.39 seconds
Started Oct 04 02:35:01 PM PDT 23
Finished Oct 04 02:35:03 PM PDT 23
Peak memory 145168 kb
Host smart-3eae6a3e-537c-4691-8593-f62cb28410ea
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1265283681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1265283681
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3442382817
Short name T28
Test name
Test status
Simulation time 9865737 ps
CPU time 0.37 seconds
Started Oct 04 02:46:57 PM PDT 23
Finished Oct 04 02:46:58 PM PDT 23
Peak memory 145072 kb
Host smart-4c217401-28a6-4ea6-b3cf-2a61c8e02ecb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3442382817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3442382817
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.407675151
Short name T32
Test name
Test status
Simulation time 9153720 ps
CPU time 0.38 seconds
Started Oct 04 02:36:51 PM PDT 23
Finished Oct 04 02:36:52 PM PDT 23
Peak memory 145000 kb
Host smart-e72bcd12-53f6-458d-b94e-06d72244f48a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=407675151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.407675151
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2359985312
Short name T58
Test name
Test status
Simulation time 9606424 ps
CPU time 0.37 seconds
Started Oct 04 02:34:55 PM PDT 23
Finished Oct 04 02:34:55 PM PDT 23
Peak memory 145108 kb
Host smart-1d39192b-6854-41f4-984f-1c1d468023e0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2359985312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2359985312
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1230095035
Short name T35
Test name
Test status
Simulation time 9439699 ps
CPU time 0.37 seconds
Started Oct 04 02:34:55 PM PDT 23
Finished Oct 04 02:34:56 PM PDT 23
Peak memory 145072 kb
Host smart-f1eff1e3-4a4c-4eb4-ba13-8dc582e2d7d2
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1230095035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1230095035
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2680824152
Short name T56
Test name
Test status
Simulation time 9089211 ps
CPU time 0.36 seconds
Started Oct 04 02:34:55 PM PDT 23
Finished Oct 04 02:34:56 PM PDT 23
Peak memory 145064 kb
Host smart-7c580f76-3701-4d85-8bf7-d72977194a4f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2680824152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2680824152
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1212240537
Short name T59
Test name
Test status
Simulation time 9408580 ps
CPU time 0.38 seconds
Started Oct 04 02:34:54 PM PDT 23
Finished Oct 04 02:34:55 PM PDT 23
Peak memory 145072 kb
Host smart-5ff35c27-7433-4a91-bb3a-e8635ecd3e70
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1212240537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1212240537
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.1052974541
Short name T57
Test name
Test status
Simulation time 8567646 ps
CPU time 0.37 seconds
Started Oct 04 02:38:33 PM PDT 23
Finished Oct 04 02:38:34 PM PDT 23
Peak memory 145104 kb
Host smart-928140ae-1f29-4967-9308-d8aa0a6f5983
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1052974541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1052974541
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1102427712
Short name T26
Test name
Test status
Simulation time 9405402 ps
CPU time 0.37 seconds
Started Oct 04 02:44:10 PM PDT 23
Finished Oct 04 02:44:11 PM PDT 23
Peak memory 145064 kb
Host smart-46d606d1-a65f-4b17-b69a-7c56ba7032c3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1102427712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1102427712
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.927833813
Short name T73
Test name
Test status
Simulation time 28709524 ps
CPU time 0.39 seconds
Started Oct 04 12:33:41 PM PDT 23
Finished Oct 04 12:33:42 PM PDT 23
Peak memory 145028 kb
Host smart-9c85b0f7-2d65-4c5a-ba0b-969d4b3a449b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=927833813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.927833813
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.884842250
Short name T77
Test name
Test status
Simulation time 27269043 ps
CPU time 0.39 seconds
Started Oct 04 12:24:45 PM PDT 23
Finished Oct 04 12:24:46 PM PDT 23
Peak memory 144964 kb
Host smart-3d1f85d0-ea19-4b2d-94dd-a4942f54d233
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=884842250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.884842250
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2699305725
Short name T64
Test name
Test status
Simulation time 27340720 ps
CPU time 0.37 seconds
Started Oct 04 12:36:50 PM PDT 23
Finished Oct 04 12:36:51 PM PDT 23
Peak memory 144772 kb
Host smart-903c77cf-d457-4a7a-9fd0-8f90d5958bca
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2699305725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2699305725
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3759687365
Short name T17
Test name
Test status
Simulation time 26978757 ps
CPU time 0.39 seconds
Started Oct 04 12:31:01 PM PDT 23
Finished Oct 04 12:31:02 PM PDT 23
Peak memory 144996 kb
Host smart-e75ca340-8876-4813-a701-c55dee495fd3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3759687365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3759687365
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3223274574
Short name T71
Test name
Test status
Simulation time 28121673 ps
CPU time 0.4 seconds
Started Oct 04 12:18:07 PM PDT 23
Finished Oct 04 12:18:08 PM PDT 23
Peak memory 145120 kb
Host smart-a08a5ba6-740e-4345-8b6f-b2544431f020
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3223274574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3223274574
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3784596429
Short name T78
Test name
Test status
Simulation time 26400708 ps
CPU time 0.4 seconds
Started Oct 04 12:21:02 PM PDT 23
Finished Oct 04 12:21:04 PM PDT 23
Peak memory 145176 kb
Host smart-e6a1a4a2-043b-4da2-8097-9592b0c2042a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3784596429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3784596429
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.4081367550
Short name T13
Test name
Test status
Simulation time 28512678 ps
CPU time 0.4 seconds
Started Oct 04 12:21:20 PM PDT 23
Finished Oct 04 12:21:20 PM PDT 23
Peak memory 144948 kb
Host smart-60396848-74e2-4592-bde5-b039053f05e3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4081367550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.4081367550
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.121379678
Short name T68
Test name
Test status
Simulation time 27582393 ps
CPU time 0.4 seconds
Started Oct 04 12:30:47 PM PDT 23
Finished Oct 04 12:30:48 PM PDT 23
Peak memory 145020 kb
Host smart-5a66192b-4429-4e2a-9742-1e47c10f5425
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=121379678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.121379678
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.295037840
Short name T6
Test name
Test status
Simulation time 27056564 ps
CPU time 0.39 seconds
Started Oct 04 12:16:37 PM PDT 23
Finished Oct 04 12:16:38 PM PDT 23
Peak memory 145016 kb
Host smart-33854a26-17d4-4864-8e57-2ecf34f639e1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=295037840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.295037840
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.61481329
Short name T69
Test name
Test status
Simulation time 28794159 ps
CPU time 0.4 seconds
Started Oct 04 12:46:45 PM PDT 23
Finished Oct 04 12:46:46 PM PDT 23
Peak memory 145104 kb
Host smart-1574f425-de4b-40d7-91f6-f8bd7051b81f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=61481329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.61481329
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3386058026
Short name T66
Test name
Test status
Simulation time 28357641 ps
CPU time 0.43 seconds
Started Oct 04 12:26:17 PM PDT 23
Finished Oct 04 12:26:18 PM PDT 23
Peak memory 144988 kb
Host smart-edc84b72-2225-40b6-b560-bb98443c3b60
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3386058026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3386058026
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.54576385
Short name T79
Test name
Test status
Simulation time 27141221 ps
CPU time 0.44 seconds
Started Oct 04 12:23:31 PM PDT 23
Finished Oct 04 12:23:32 PM PDT 23
Peak memory 145140 kb
Host smart-41ec0c8c-eca2-43b1-9826-4b3926e26ecb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=54576385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.54576385
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.4044886051
Short name T65
Test name
Test status
Simulation time 27044839 ps
CPU time 0.38 seconds
Started Oct 04 12:16:35 PM PDT 23
Finished Oct 04 12:16:36 PM PDT 23
Peak memory 144700 kb
Host smart-50ab27e9-50e9-4651-bdb7-e80ba610241d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4044886051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.4044886051
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2641996345
Short name T76
Test name
Test status
Simulation time 29073651 ps
CPU time 0.41 seconds
Started Oct 04 12:33:17 PM PDT 23
Finished Oct 04 12:33:18 PM PDT 23
Peak memory 145048 kb
Host smart-a08f1f3e-e14d-4ece-bb4a-8cbf4df00174
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2641996345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2641996345
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1659657022
Short name T75
Test name
Test status
Simulation time 27553915 ps
CPU time 0.44 seconds
Started Oct 04 12:36:46 PM PDT 23
Finished Oct 04 12:36:48 PM PDT 23
Peak memory 144520 kb
Host smart-f4749540-e48e-41a8-a78d-8178a3d695a8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1659657022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1659657022
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3942527248
Short name T72
Test name
Test status
Simulation time 25630303 ps
CPU time 0.39 seconds
Started Oct 04 12:26:16 PM PDT 23
Finished Oct 04 12:26:17 PM PDT 23
Peak memory 145020 kb
Host smart-5c023c49-b5bc-4fd6-8df3-ab09c55ff7ce
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3942527248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3942527248
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2586682789
Short name T67
Test name
Test status
Simulation time 26201806 ps
CPU time 0.38 seconds
Started Oct 04 12:32:51 PM PDT 23
Finished Oct 04 12:32:52 PM PDT 23
Peak memory 144956 kb
Host smart-50bb2b76-880f-4811-ab87-d5eca05669c2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2586682789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2586682789
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.4076590391
Short name T70
Test name
Test status
Simulation time 28226857 ps
CPU time 0.43 seconds
Started Oct 04 12:18:45 PM PDT 23
Finished Oct 04 12:18:46 PM PDT 23
Peak memory 145164 kb
Host smart-9b45330d-3aa2-46d3-9ae1-9882031bda10
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4076590391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.4076590391
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3344758044
Short name T74
Test name
Test status
Simulation time 26328251 ps
CPU time 0.39 seconds
Started Oct 04 12:22:16 PM PDT 23
Finished Oct 04 12:22:17 PM PDT 23
Peak memory 144932 kb
Host smart-353267dc-b1f9-4ead-9abd-be7d0a1c6279
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3344758044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3344758044
Directory /workspace/9.prim_sync_fatal_alert/latest
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