Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T13

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T9,T11,T14	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T3,T8,T15
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T16,T17,T18
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T19,T11,T14
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T1,T11,T20

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	154292	115948	0	158
AlertKnownO_A	154988	117637	0	0
InBandInitRequest_A	154988	4040	0	0
InBandInitSequence_A	154988	416	0	0
InitReq_A	154988	759	0	0
IntegFailKnownO_A	154988	117637	0	0
NoSpuriousAlertsDuringInit_A	154988	16408	0	0
NoSpuriousPingOksDuringInit_A	154988	16041	0	0
PingDiffOk_A	154116	116765	0	0
PingOkBypassDuringInit_A	154988	41	0	40
PingOkKnownO_A	154988	117637	0	0
PingPKnownO_A	154988	117637	0	0
PingPending_A	154988	828	0	119
PingRequest0_A	154988	0	0	79
PingResponse0_A	154988	759	0	0
gen_async_assert.Alert_A	81721	1349	0	0
gen_async_assert.PingResponse1_A	81721	316	0	0
gen_async_assert.SigInt_A	81721	246	0	85
gen_sync_assert.Alert_A	73267	3182	0	0
gen_sync_assert.PingResponse1_A	73267	352	0	0
gen_sync_assert.SigInt_A	73267	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154292	115948	0	158
T1	1138	1051	0	2
T2	1102	1002	0	2
T3	1074	1021	0	2
T7	1069	1012	0	2
T8	1080	1013	0	2
T9	1124	966	0	2
T10	1109	1023	0	2
T11	1280	1083	0	2
T15	1053	978	0	2
T19	1124	1042	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	117637	0	0
T1	1154	1069	0	0
T2	1117	1019	0	0
T3	1089	1038	0	0
T7	1082	1027	0	0
T8	1093	1028	0	0
T9	1137	983	0	0
T10	1123	1039	0	0
T11	1293	1100	0	0
T15	1067	994	0	0
T19	1140	1060	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	4040	0	0
T1	1154	63	0	0
T2	1117	56	0	0
T3	1089	75	0	0
T7	1082	63	0	0
T8	1093	42	0	0
T9	1137	27	0	0
T10	1123	51	0	0
T11	1293	81	0	0
T15	1067	46	0	0
T19	1140	55	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	416	0	0
T1	1154	2	0	0
T2	1117	1	0	0
T3	1089	4	0	0
T7	1082	2	0	0
T8	1093	1	0	0
T9	1137	1	0	0
T10	1123	1	0	0
T11	1293	4	0	0
T15	1067	1	0	0
T19	1140	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	759	0	0
T1	1154	10	0	0
T2	1117	10	0	0
T3	1089	12	0	0
T7	1082	10	0	0
T8	1093	9	0	0
T9	1137	5	0	0
T10	1123	11	0	0
T11	1293	12	0	0
T15	1067	11	0	0
T19	1140	10	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	117637	0	0
T1	1154	1069	0	0
T2	1117	1019	0	0
T3	1089	1038	0	0
T7	1082	1027	0	0
T8	1093	1028	0	0
T9	1137	983	0	0
T10	1123	1039	0	0
T11	1293	1100	0	0
T15	1067	994	0	0
T19	1140	1060	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	16408	0	0
T1	1154	195	0	0
T2	1117	197	0	0
T3	1089	241	0	0
T7	1082	199	0	0
T8	1093	184	0	0
T9	1137	124	0	0
T10	1123	219	0	0
T11	1293	244	0	0
T15	1067	218	0	0
T19	1140	197	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	16041	0	0
T1	1154	192	0	0
T2	1117	189	0	0
T3	1089	232	0	0
T7	1082	194	0	0
T8	1093	182	0	0
T9	1137	108	0	0
T10	1123	200	0	0
T11	1293	232	0	0
T15	1067	215	0	0
T19	1140	197	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154116	116765	0	0
T1	1140	1055	0	0
T2	1099	1001	0	0
T3	1072	1021	0	0
T7	1068	1013	0	0
T8	1076	1011	0	0
T9	1119	965	0	0
T10	1106	1022	0	0
T11	1280	1087	0	0
T15	1054	981	0	0
T19	1124	1044	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	41	0	40
T1	1154	1	0	1
T2	1117	1	0	0
T3	1089	3	0	0
T7	1082	0	0	0
T8	1093	1	0	0
T9	1137	0	0	0
T10	1123	0	0	0
T11	1293	0	0	0
T15	1067	1	0	0
T19	1140	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	117637	0	0
T1	1154	1069	0	0
T2	1117	1019	0	0
T3	1089	1038	0	0
T7	1082	1027	0	0
T8	1093	1028	0	0
T9	1137	983	0	0
T10	1123	1039	0	0
T11	1293	1100	0	0
T15	1067	994	0	0
T19	1140	1060	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	117637	0	0
T1	1154	1069	0	0
T2	1117	1019	0	0
T3	1089	1038	0	0
T7	1082	1027	0	0
T8	1093	1028	0	0
T9	1137	983	0	0
T10	1123	1039	0	0
T11	1293	1100	0	0
T15	1067	994	0	0
T19	1140	1060	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	828	0	119
T1	1154	11	0	1
T2	1117	11	0	1
T3	1089	11	0	1
T7	1082	11	0	1
T8	1093	11	0	1
T9	1137	11	0	1
T10	1123	11	0	1
T11	1293	11	0	1
T15	1067	11	0	1
T19	1140	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	0	0	79

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154988	759	0	0
T1	1154	10	0	0
T2	1117	9	0	0
T3	1089	10	0	0
T7	1082	9	0	0
T8	1093	9	0	0
T9	1137	10	0	0
T10	1123	10	0	0
T11	1293	9	0	0
T15	1067	8	0	0
T19	1140	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81721	1349	0	0
T1	1154	7	0	0
T2	1117	9	0	0
T3	1089	7	0	0
T7	1082	7	0	0
T8	1093	7	0	0
T9	1137	9	0	0
T10	1123	7	0	0
T11	1293	6	0	0
T15	1067	8	0	0
T19	1140	4	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81721	316	0	0
T1	1154	8	0	0
T2	1117	5	0	0
T3	1089	4	0	0
T7	1082	7	0	0
T8	1093	8	0	0
T9	1137	9	0	0
T10	1123	8	0	0
T11	1293	9	0	0
T15	1067	7	0	0
T19	1140	10	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81721	246	0	85
T1	1154	7	0	3
T2	1117	6	0	3
T3	1089	7	0	3
T7	1082	5	0	2
T8	1093	5	0	2
T9	1137	7	0	3
T10	1123	5	0	3
T11	1293	7	0	2
T15	1067	6	0	2
T19	1140	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73267	3182	0	0
T26	904	9	0	0
T27	944	10	0	0
T28	890	9	0	0
T29	973	8	0	0
T30	986	8	0	0
T35	918	10	0	0
T36	1011	11	0	0
T37	866	10	0	0
T38	931	13	0	0
T39	1043	8	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73267	352	0	0
T26	904	8	0	0
T27	944	10	0	0
T28	890	8	0	0
T29	973	9	0	0
T30	986	8	0	0
T35	918	6	0	0
T36	1011	10	0	0
T37	866	9	0	0
T38	931	9	0	0
T39	1043	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73267	40	0	0
T26	904	1	0	0
T27	944	1	0	0
T28	890	1	0	0
T29	973	1	0	0
T30	986	1	0	0
T35	918	1	0	0
T36	1011	1	0	0
T37	866	1	0	0
T38	931	1	0	0
T39	1043	1	0	0