Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T12,T13

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T14,T15	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T15,T16,T17
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T9,T18,T19
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T20,T15,T9

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	154905	116747	0	160
AlertKnownO_A	155620	118456	0	0
InBandInitRequest_A	155620	4374	0	0
InBandInitSequence_A	155620	450	0	0
InitReq_A	155620	799	0	0
IntegFailKnownO_A	155620	118456	0	0
NoSpuriousAlertsDuringInit_A	155620	16892	0	0
NoSpuriousPingOksDuringInit_A	155620	16591	0	0
PingDiffOk_A	154715	117551	0	0
PingOkBypassDuringInit_A	155620	37	0	40
PingOkKnownO_A	155620	118456	0	0
PingPKnownO_A	155620	118456	0	0
PingPending_A	155620	839	0	120
PingRequest0_A	155620	0	0	80
PingResponse0_A	155620	776	0	0
gen_async_assert.Alert_A	82556	1356	0	0
gen_async_assert.PingResponse1_A	82556	330	0	0
gen_async_assert.SigInt_A	82556	258	0	101
gen_sync_assert.Alert_A	73064	3091	0	0
gen_sync_assert.PingResponse1_A	73064	355	0	0
gen_sync_assert.SigInt_A	73064	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154905	116747	0	160
T1	1049	964	0	2
T2	1088	1017	0	2
T3	1131	1009	0	2
T7	1102	1048	0	2
T14	1156	983	0	2
T20	1164	1067	0	2
T21	1062	961	0	2
T22	1072	985	0	2
T23	1139	1043	0	2
T24	1094	1023	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	118456	0	0
T1	1064	981	0	0
T2	1104	1035	0	0
T3	1147	1029	0	0
T7	1115	1063	0	0
T14	1171	1002	0	0
T20	1180	1085	0	0
T21	1077	978	0	0
T22	1088	1003	0	0
T23	1154	1060	0	0
T24	1110	1041	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	4374	0	0
T1	1064	21	0	0
T2	1104	50	0	0
T3	1147	49	0	0
T7	1115	35	0	0
T14	1171	38	0	0
T20	1180	63	0	0
T21	1077	47	0	0
T22	1088	64	0	0
T23	1154	51	0	0
T24	1110	58	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	450	0	0
T2	1104	2	0	0
T3	1147	3	0	0
T7	1115	0	0	0
T8	0	4	0	0
T14	1171	2	0	0
T15	1183	3	0	0
T20	1180	2	0	0
T21	1077	1	0	0
T22	1088	3	0	0
T23	1154	2	0	0
T24	1110	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	799	0	0
T1	1064	6	0	0
T2	1104	9	0	0
T3	1147	8	0	0
T7	1115	11	0	0
T14	1171	5	0	0
T20	1180	14	0	0
T21	1077	8	0	0
T22	1088	8	0	0
T23	1154	9	0	0
T24	1110	11	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	118456	0	0
T1	1064	981	0	0
T2	1104	1035	0	0
T3	1147	1029	0	0
T7	1115	1063	0	0
T14	1171	1002	0	0
T20	1180	1085	0	0
T21	1077	978	0	0
T22	1088	1003	0	0
T23	1154	1060	0	0
T24	1110	1041	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	16892	0	0
T1	1064	123	0	0
T2	1104	185	0	0
T3	1147	187	0	0
T7	1115	211	0	0
T14	1171	132	0	0
T20	1180	274	0	0
T21	1077	165	0	0
T22	1088	165	0	0
T23	1154	183	0	0
T24	1110	225	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	16591	0	0
T1	1064	123	0	0
T2	1104	183	0	0
T3	1147	184	0	0
T7	1115	209	0	0
T14	1171	130	0	0
T20	1180	272	0	0
T21	1077	163	0	0
T22	1088	164	0	0
T23	1154	183	0	0
T24	1110	222	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154715	117551	0	0
T1	1048	965	0	0
T2	1089	1020	0	0
T3	1133	1015	0	0
T7	1100	1048	0	0
T14	1152	983	0	0
T20	1167	1072	0	0
T21	1061	962	0	0
T22	1076	991	0	0
T23	1138	1044	0	0
T24	1095	1026	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	37	0	40
T8	1147	1	0	0
T9	1210	0	0	0
T10	1110	1	0	0
T15	1183	0	0	0
T17	0	1	0	0
T18	0	0	0	1
T19	0	0	0	1
T20	1180	0	0	0
T22	1088	1	0	0
T23	1154	0	0	0
T24	1110	1	0	0
T25	1100	1	0	0
T26	1209	1	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	2	0	0
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1
T36	0	0	0	1
T37	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	118456	0	0
T1	1064	981	0	0
T2	1104	1035	0	0
T3	1147	1029	0	0
T7	1115	1063	0	0
T14	1171	1002	0	0
T20	1180	1085	0	0
T21	1077	978	0	0
T22	1088	1003	0	0
T23	1154	1060	0	0
T24	1110	1041	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	118456	0	0
T1	1064	981	0	0
T2	1104	1035	0	0
T3	1147	1029	0	0
T7	1115	1063	0	0
T14	1171	1002	0	0
T20	1180	1085	0	0
T21	1077	978	0	0
T22	1088	1003	0	0
T23	1154	1060	0	0
T24	1110	1041	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	839	0	120
T1	1064	11	0	1
T2	1104	11	0	1
T3	1147	11	0	1
T7	1115	11	0	1
T14	1171	11	0	1
T20	1180	11	0	1
T21	1077	11	0	1
T22	1088	11	0	1
T23	1154	11	0	1
T24	1110	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	0	0	80

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155620	776	0	0
T1	1064	10	0	0
T2	1104	9	0	0
T3	1147	9	0	0
T7	1115	9	0	0
T14	1171	10	0	0
T20	1180	8	0	0
T21	1077	10	0	0
T22	1088	10	0	0
T23	1154	10	0	0
T24	1110	8	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82556	1356	0	0
T1	1064	8	0	0
T2	1104	10	0	0
T3	1147	7	0	0
T7	1115	8	0	0
T14	1171	11	0	0
T20	1180	5	0	0
T21	1077	9	0	0
T22	1088	7	0	0
T23	1154	8	0	0
T24	1110	5	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82556	330	0	0
T1	1064	10	0	0
T2	1104	9	0	0
T3	1147	8	0	0
T7	1115	9	0	0
T14	1171	9	0	0
T20	1180	8	0	0
T21	1077	9	0	0
T22	1088	9	0	0
T23	1154	10	0	0
T24	1110	7	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82556	258	0	101
T1	1064	6	0	3
T2	1104	6	0	2
T3	1147	8	0	2
T7	1115	7	0	3
T14	1171	6	0	3
T20	1180	6	0	2
T21	1077	7	0	3
T22	1088	6	0	2
T23	1154	7	0	2
T24	1110	8	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73064	3091	0	0
T18	994	8	0	0
T19	1046	9	0	0
T30	864	10	0	0
T31	852	10	0	0
T32	832	12	0	0
T33	965	10	0	0
T34	922	9	0	0
T38	924	11	0	0
T39	930	9	0	0
T40	903	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73064	355	0	0
T18	994	10	0	0
T19	1046	7	0	0
T30	864	8	0	0
T31	852	9	0	0
T32	832	9	0	0
T33	965	9	0	0
T34	922	9	0	0
T38	924	10	0	0
T39	930	9	0	0
T40	903	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73064	40	0	0
T18	994	1	0	0
T19	1046	1	0	0
T30	864	1	0	0
T31	852	1	0	0
T32	832	1	0	0
T33	965	1	0	0
T34	922	1	0	0
T38	924	1	0	0
T39	930	1	0	0
T40	903	1	0	0