| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.19 | 100.00 | 100.00 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 88.32 | 88.32 | 100.00 | 100.00 | 91.67 | 91.67 | 96.43 | 96.43 | 78.57 | 78.57 | 95.83 | 95.83 | 67.44 | 67.44 | /workspace/coverage/default/14.prim_async_alert.1114880726 |
| 91.45 | 3.13 | 100.00 | 0.00 | 91.67 | 0.00 | 96.43 | 0.00 | 85.71 | 7.14 | 95.83 | 0.00 | 79.07 | 11.63 | /workspace/coverage/sync_alert/17.prim_sync_alert.3576461752 |
| 94.25 | 2.80 | 100.00 | 0.00 | 97.92 | 6.25 | 100.00 | 3.57 | 85.71 | 0.00 | 95.83 | 0.00 | 86.05 | 6.98 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4020027469 |
| 94.85 | 0.60 | 100.00 | 0.00 | 97.92 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2404706929 |
| 95.19 | 0.35 | 100.00 | 0.00 | 100.00 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2272324765 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.4017356227 |
| /workspace/coverage/default/1.prim_async_alert.2935939154 |
| /workspace/coverage/default/10.prim_async_alert.2252657288 |
| /workspace/coverage/default/11.prim_async_alert.1670792559 |
| /workspace/coverage/default/12.prim_async_alert.3278552329 |
| /workspace/coverage/default/13.prim_async_alert.3894232475 |
| /workspace/coverage/default/15.prim_async_alert.2977660775 |
| /workspace/coverage/default/16.prim_async_alert.592333788 |
| /workspace/coverage/default/17.prim_async_alert.1248210762 |
| /workspace/coverage/default/18.prim_async_alert.2597948875 |
| /workspace/coverage/default/19.prim_async_alert.1566620963 |
| /workspace/coverage/default/2.prim_async_alert.3701473911 |
| /workspace/coverage/default/3.prim_async_alert.629123040 |
| /workspace/coverage/default/4.prim_async_alert.316261294 |
| /workspace/coverage/default/5.prim_async_alert.1674861493 |
| /workspace/coverage/default/6.prim_async_alert.4280023668 |
| /workspace/coverage/default/7.prim_async_alert.3578235242 |
| /workspace/coverage/default/8.prim_async_alert.2235311510 |
| /workspace/coverage/default/9.prim_async_alert.2673876654 |
| /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2146685541 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1417979080 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2942506143 |
| /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2019046149 |
| /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4134730378 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2080668715 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2039408503 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4273812643 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3461581784 |
| /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1820245135 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3472110643 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2100139432 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3296750015 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3137827418 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.4243161599 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.4013772620 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.3962476942 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.2887027789 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.662724254 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.1291417024 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.1795670076 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.2537983989 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.2179906139 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.1883470561 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.140172392 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.2029470024 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.2280497552 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.1717184056 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.1486263832 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3029216669 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.227963721 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2239023361 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2265180669 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1263237661 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1535036522 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2801208315 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.136443675 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2927224885 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1604501374 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3594681091 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.354684377 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3039421628 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3713683803 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3106998584 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2792268323 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1277896657 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1441127449 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2431746324 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2833074834 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.prim_async_alert.2935939154 | Jan 03 12:40:51 PM PST 24 | Jan 03 12:42:20 PM PST 24 | 12279548 ps | ||
| T2 | /workspace/coverage/default/4.prim_async_alert.316261294 | Jan 03 12:40:54 PM PST 24 | Jan 03 12:42:23 PM PST 24 | 11476743 ps | ||
| T3 | /workspace/coverage/default/2.prim_async_alert.3701473911 | Jan 03 12:40:38 PM PST 24 | Jan 03 12:42:06 PM PST 24 | 11362422 ps | ||
| T7 | /workspace/coverage/default/19.prim_async_alert.1566620963 | Jan 03 12:40:22 PM PST 24 | Jan 03 12:41:54 PM PST 24 | 10537641 ps | ||
| T17 | /workspace/coverage/default/16.prim_async_alert.592333788 | Jan 03 12:40:38 PM PST 24 | Jan 03 12:42:05 PM PST 24 | 11424672 ps | ||
| T20 | /workspace/coverage/default/14.prim_async_alert.1114880726 | Jan 03 12:40:27 PM PST 24 | Jan 03 12:41:53 PM PST 24 | 11156119 ps | ||
| T21 | /workspace/coverage/default/7.prim_async_alert.3578235242 | Jan 03 12:40:27 PM PST 24 | Jan 03 12:41:59 PM PST 24 | 11475900 ps | ||
| T22 | /workspace/coverage/default/15.prim_async_alert.2977660775 | Jan 03 12:40:42 PM PST 24 | Jan 03 12:42:10 PM PST 24 | 11635178 ps | ||
| T9 | /workspace/coverage/default/6.prim_async_alert.4280023668 | Jan 03 12:41:05 PM PST 24 | Jan 03 12:42:35 PM PST 24 | 10301306 ps | ||
| T10 | /workspace/coverage/default/5.prim_async_alert.1674861493 | Jan 03 12:40:37 PM PST 24 | Jan 03 12:42:02 PM PST 24 | 10987272 ps | ||
| T12 | /workspace/coverage/default/8.prim_async_alert.2235311510 | Jan 03 12:40:58 PM PST 24 | Jan 03 12:42:27 PM PST 24 | 12114448 ps | ||
| T44 | /workspace/coverage/default/3.prim_async_alert.629123040 | Jan 03 12:40:28 PM PST 24 | Jan 03 12:41:56 PM PST 24 | 11525608 ps | ||
| T36 | /workspace/coverage/default/13.prim_async_alert.3894232475 | Jan 03 12:40:55 PM PST 24 | Jan 03 12:42:24 PM PST 24 | 10666874 ps | ||
| T13 | /workspace/coverage/default/0.prim_async_alert.4017356227 | Jan 03 12:41:08 PM PST 24 | Jan 03 12:42:37 PM PST 24 | 11829703 ps | ||
| T23 | /workspace/coverage/default/12.prim_async_alert.3278552329 | Jan 03 12:40:52 PM PST 24 | Jan 03 12:42:21 PM PST 24 | 12134562 ps | ||
| T8 | /workspace/coverage/default/11.prim_async_alert.1670792559 | Jan 03 12:41:01 PM PST 24 | Jan 03 12:42:30 PM PST 24 | 11010759 ps | ||
| T24 | /workspace/coverage/default/9.prim_async_alert.2673876654 | Jan 03 12:40:58 PM PST 24 | Jan 03 12:42:27 PM PST 24 | 11175155 ps | ||
| T18 | /workspace/coverage/default/17.prim_async_alert.1248210762 | Jan 03 12:41:01 PM PST 24 | Jan 03 12:42:30 PM PST 24 | 12081070 ps | ||
| T19 | /workspace/coverage/default/18.prim_async_alert.2597948875 | Jan 03 12:40:37 PM PST 24 | Jan 03 12:42:03 PM PST 24 | 10458597 ps | ||
| T45 | /workspace/coverage/default/10.prim_async_alert.2252657288 | Jan 03 12:40:42 PM PST 24 | Jan 03 12:42:09 PM PST 24 | 11540740 ps | ||
| T25 | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1820245135 | Jan 03 12:35:16 PM PST 24 | Jan 03 12:36:47 PM PST 24 | 30009136 ps | ||
| T4 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4020027469 | Jan 03 12:35:27 PM PST 24 | Jan 03 12:37:00 PM PST 24 | 28742585 ps | ||
| T26 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2019046149 | Jan 03 12:35:30 PM PST 24 | Jan 03 12:37:05 PM PST 24 | 29089624 ps | ||
| T38 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2080668715 | Jan 03 12:35:19 PM PST 24 | Jan 03 12:36:49 PM PST 24 | 30259607 ps | ||
| T39 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1417979080 | Jan 03 12:35:19 PM PST 24 | Jan 03 12:36:52 PM PST 24 | 30211600 ps | ||
| T40 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2942506143 | Jan 03 12:35:41 PM PST 24 | Jan 03 12:37:26 PM PST 24 | 29802910 ps | ||
| T41 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4134730378 | Jan 03 12:35:19 PM PST 24 | Jan 03 12:36:46 PM PST 24 | 28572409 ps | ||
| T42 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3461581784 | Jan 03 12:35:16 PM PST 24 | Jan 03 12:36:40 PM PST 24 | 28493491 ps | ||
| T43 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3296750015 | Jan 03 12:35:15 PM PST 24 | Jan 03 12:36:41 PM PST 24 | 30465723 ps | ||
| T14 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2404706929 | Jan 03 12:35:30 PM PST 24 | Jan 03 12:37:06 PM PST 24 | 28830013 ps | ||
| T37 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3472110643 | Jan 03 12:35:29 PM PST 24 | Jan 03 12:36:59 PM PST 24 | 30654657 ps | ||
| T5 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2100139432 | Jan 03 12:35:46 PM PST 24 | Jan 03 12:37:18 PM PST 24 | 32364202 ps | ||
| T46 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2039408503 | Jan 03 12:35:16 PM PST 24 | Jan 03 12:36:41 PM PST 24 | 29555324 ps | ||
| T47 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4273812643 | Jan 03 12:35:42 PM PST 24 | Jan 03 12:37:24 PM PST 24 | 31320770 ps | ||
| T48 | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2146685541 | Jan 03 12:35:42 PM PST 24 | Jan 03 12:37:23 PM PST 24 | 28876665 ps | ||
| T35 | /workspace/coverage/sync_alert/14.prim_sync_alert.662724254 | Jan 03 12:36:27 PM PST 24 | Jan 03 12:37:53 PM PST 24 | 8363594 ps | ||
| T15 | /workspace/coverage/sync_alert/10.prim_sync_alert.4243161599 | Jan 03 12:36:40 PM PST 24 | Jan 03 12:38:21 PM PST 24 | 10436374 ps | ||
| T27 | /workspace/coverage/sync_alert/6.prim_sync_alert.2280497552 | Jan 03 12:36:39 PM PST 24 | Jan 03 12:37:55 PM PST 24 | 9002190 ps | ||
| T28 | /workspace/coverage/sync_alert/7.prim_sync_alert.1717184056 | Jan 03 12:37:08 PM PST 24 | Jan 03 12:38:19 PM PST 24 | 8933144 ps | ||
| T29 | /workspace/coverage/sync_alert/19.prim_sync_alert.2537983989 | Jan 03 12:36:27 PM PST 24 | Jan 03 12:37:56 PM PST 24 | 10494445 ps | ||
| T30 | /workspace/coverage/sync_alert/3.prim_sync_alert.1883470561 | Jan 03 12:36:56 PM PST 24 | Jan 03 12:38:04 PM PST 24 | 9812012 ps | ||
| T31 | /workspace/coverage/sync_alert/4.prim_sync_alert.140172392 | Jan 03 12:36:35 PM PST 24 | Jan 03 12:37:59 PM PST 24 | 8953292 ps | ||
| T32 | /workspace/coverage/sync_alert/18.prim_sync_alert.1795670076 | Jan 03 12:36:23 PM PST 24 | Jan 03 12:38:06 PM PST 24 | 8547219 ps | ||
| T33 | /workspace/coverage/sync_alert/16.prim_sync_alert.1291417024 | Jan 03 12:36:14 PM PST 24 | Jan 03 12:38:06 PM PST 24 | 9926758 ps | ||
| T34 | /workspace/coverage/sync_alert/17.prim_sync_alert.3576461752 | Jan 03 12:36:18 PM PST 24 | Jan 03 12:37:55 PM PST 24 | 9694751 ps | ||
| T49 | /workspace/coverage/sync_alert/12.prim_sync_alert.3962476942 | Jan 03 12:36:20 PM PST 24 | Jan 03 12:38:21 PM PST 24 | 9171608 ps | ||
| T50 | /workspace/coverage/sync_alert/5.prim_sync_alert.2029470024 | Jan 03 12:36:22 PM PST 24 | Jan 03 12:37:53 PM PST 24 | 9300054 ps | ||
| T51 | /workspace/coverage/sync_alert/11.prim_sync_alert.4013772620 | Jan 03 12:36:51 PM PST 24 | Jan 03 12:38:21 PM PST 24 | 8669251 ps | ||
| T52 | /workspace/coverage/sync_alert/2.prim_sync_alert.2179906139 | Jan 03 12:36:25 PM PST 24 | Jan 03 12:38:02 PM PST 24 | 9558945 ps | ||
| T53 | /workspace/coverage/sync_alert/0.prim_sync_alert.3137827418 | Jan 03 12:36:29 PM PST 24 | Jan 03 12:37:55 PM PST 24 | 8898776 ps | ||
| T54 | /workspace/coverage/sync_alert/9.prim_sync_alert.3029216669 | Jan 03 12:36:31 PM PST 24 | Jan 03 12:38:06 PM PST 24 | 9514626 ps | ||
| T55 | /workspace/coverage/sync_alert/13.prim_sync_alert.2887027789 | Jan 03 12:36:16 PM PST 24 | Jan 03 12:38:04 PM PST 24 | 10439746 ps | ||
| T56 | /workspace/coverage/sync_alert/8.prim_sync_alert.1486263832 | Jan 03 12:36:30 PM PST 24 | Jan 03 12:38:08 PM PST 24 | 9050189 ps | ||
| T57 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1277896657 | Jan 03 12:44:03 PM PST 24 | Jan 03 12:45:28 PM PST 24 | 26717271 ps | ||
| T58 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.354684377 | Jan 03 12:43:42 PM PST 24 | Jan 03 12:45:33 PM PST 24 | 25112927 ps | ||
| T59 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2431746324 | Jan 03 12:44:01 PM PST 24 | Jan 03 12:45:17 PM PST 24 | 27820671 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2833074834 | Jan 03 12:44:01 PM PST 24 | Jan 03 12:45:16 PM PST 24 | 26859459 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2239023361 | Jan 03 12:44:43 PM PST 24 | Jan 03 12:46:07 PM PST 24 | 28940807 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1263237661 | Jan 03 12:44:19 PM PST 24 | Jan 03 12:45:38 PM PST 24 | 27536883 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2927224885 | Jan 03 12:43:56 PM PST 24 | Jan 03 12:45:31 PM PST 24 | 26969175 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1604501374 | Jan 03 12:43:39 PM PST 24 | Jan 03 12:45:00 PM PST 24 | 26727355 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.136443675 | Jan 03 12:44:10 PM PST 24 | Jan 03 12:45:25 PM PST 24 | 26978062 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3106998584 | Jan 03 12:43:59 PM PST 24 | Jan 03 12:45:45 PM PST 24 | 29607336 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3039421628 | Jan 03 12:43:51 PM PST 24 | Jan 03 12:45:07 PM PST 24 | 25877269 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3713683803 | Jan 03 12:44:13 PM PST 24 | Jan 03 12:45:34 PM PST 24 | 27223108 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2265180669 | Jan 03 12:44:09 PM PST 24 | Jan 03 12:45:51 PM PST 24 | 26721976 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1535036522 | Jan 03 12:44:21 PM PST 24 | Jan 03 12:45:52 PM PST 24 | 26136785 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2792268323 | Jan 03 12:43:53 PM PST 24 | Jan 03 12:45:10 PM PST 24 | 28121540 ps | ||
| T11 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2272324765 | Jan 03 12:43:47 PM PST 24 | Jan 03 12:45:09 PM PST 24 | 28239690 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.227963721 | Jan 03 12:43:54 PM PST 24 | Jan 03 12:45:20 PM PST 24 | 26771222 ps | ||
| T16 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2801208315 | Jan 03 12:43:46 PM PST 24 | Jan 03 12:45:30 PM PST 24 | 29297732 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3594681091 | Jan 03 12:43:47 PM PST 24 | Jan 03 12:45:04 PM PST 24 | 29355747 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1441127449 | Jan 03 12:44:01 PM PST 24 | Jan 03 12:45:16 PM PST 24 | 28348962 ps |
| Test location | /workspace/coverage/default/14.prim_async_alert.1114880726 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11156119 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:41:53 PM PST 24 |
| Peak memory | 145444 kb |
| Host | smart-ba9344db-23de-4e82-bef5-6c402f5c8759 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114880726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1114880726 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.3576461752 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9694751 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:18 PM PST 24 |
| Finished | Jan 03 12:37:55 PM PST 24 |
| Peak memory | 145012 kb |
| Host | smart-369d3867-cd7b-4510-a316-113a8afd02d8 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3576461752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.3576461752 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.4020027469 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28742585 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:35:27 PM PST 24 |
| Finished | Jan 03 12:37:00 PM PST 24 |
| Peak memory | 145616 kb |
| Host | smart-85cd7492-fd29-4b58-bba3-7487d282ef22 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4020027469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.4020027469 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2404706929 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 28830013 ps |
| CPU time | 0.46 seconds |
| Started | Jan 03 12:35:30 PM PST 24 |
| Finished | Jan 03 12:37:06 PM PST 24 |
| Peak memory | 145544 kb |
| Host | smart-79a9fa37-da15-4e76-92b5-e37791659bb7 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2404706929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2404706929 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2272324765 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28239690 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:43:47 PM PST 24 |
| Finished | Jan 03 12:45:09 PM PST 24 |
| Peak memory | 144992 kb |
| Host | smart-cecf7792-5b8f-433d-8686-8aba5747bc50 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2272324765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2272324765 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.4017356227 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11829703 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:08 PM PST 24 |
| Finished | Jan 03 12:42:37 PM PST 24 |
| Peak memory | 145412 kb |
| Host | smart-6604fe35-bc42-474b-9b1d-c472a4ce085f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017356227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4017356227 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.2935939154 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12279548 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:40:51 PM PST 24 |
| Finished | Jan 03 12:42:20 PM PST 24 |
| Peak memory | 145412 kb |
| Host | smart-e3d0ce51-8878-4a7d-80d7-18256d1a98eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935939154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2935939154 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.2252657288 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11540740 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:40:42 PM PST 24 |
| Finished | Jan 03 12:42:09 PM PST 24 |
| Peak memory | 145368 kb |
| Host | smart-e3199807-d92b-4b33-b8bd-ec7f82e6ee3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2252657288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.2252657288 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.1670792559 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11010759 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:41:01 PM PST 24 |
| Finished | Jan 03 12:42:30 PM PST 24 |
| Peak memory | 145448 kb |
| Host | smart-336f7470-fdd7-4a99-b35f-d9f8b8d539be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670792559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1670792559 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3278552329 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12134562 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:40:52 PM PST 24 |
| Finished | Jan 03 12:42:21 PM PST 24 |
| Peak memory | 145356 kb |
| Host | smart-38e8ebca-0854-425e-98ed-6251380d2783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278552329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3278552329 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3894232475 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10666874 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:40:55 PM PST 24 |
| Finished | Jan 03 12:42:24 PM PST 24 |
| Peak memory | 145444 kb |
| Host | smart-f0f46424-5b19-4d91-8ec4-fbbfd5bf9bd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894232475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3894232475 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.2977660775 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11635178 ps |
| CPU time | 0.4 seconds |
| Started | Jan 03 12:40:42 PM PST 24 |
| Finished | Jan 03 12:42:10 PM PST 24 |
| Peak memory | 145408 kb |
| Host | smart-58ec6db9-c78e-4a9f-8a67-559db473f783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977660775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2977660775 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.592333788 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11424672 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:40:38 PM PST 24 |
| Finished | Jan 03 12:42:05 PM PST 24 |
| Peak memory | 145436 kb |
| Host | smart-d05a47e7-b922-4ec6-80eb-12f237ade747 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592333788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.592333788 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.1248210762 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12081070 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:41:01 PM PST 24 |
| Finished | Jan 03 12:42:30 PM PST 24 |
| Peak memory | 145368 kb |
| Host | smart-f51c0dbb-4976-4c65-922b-7899ec93bc0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1248210762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1248210762 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/18.prim_async_alert.2597948875 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10458597 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:40:37 PM PST 24 |
| Finished | Jan 03 12:42:03 PM PST 24 |
| Peak memory | 145452 kb |
| Host | smart-6ab7b328-ed8b-4c02-b4fa-0e6b569f7f02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597948875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.2597948875 |
| Directory | /workspace/18.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.1566620963 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10537641 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:40:22 PM PST 24 |
| Finished | Jan 03 12:41:54 PM PST 24 |
| Peak memory | 145368 kb |
| Host | smart-c5e0f852-2980-405e-b4bd-4fedc6598f4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566620963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1566620963 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3701473911 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11362422 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:40:38 PM PST 24 |
| Finished | Jan 03 12:42:06 PM PST 24 |
| Peak memory | 145388 kb |
| Host | smart-98b4bb78-bef5-4b28-8618-b2cca6766b8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701473911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3701473911 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.629123040 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11525608 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:40:28 PM PST 24 |
| Finished | Jan 03 12:41:56 PM PST 24 |
| Peak memory | 145352 kb |
| Host | smart-1f68d8ce-c7ae-44b6-8f81-13ee39db72b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629123040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.629123040 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/4.prim_async_alert.316261294 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11476743 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:40:54 PM PST 24 |
| Finished | Jan 03 12:42:23 PM PST 24 |
| Peak memory | 145352 kb |
| Host | smart-a4a09f0a-c71d-4d7d-850d-9db77758a0ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316261294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.316261294 |
| Directory | /workspace/4.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.1674861493 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10987272 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:40:37 PM PST 24 |
| Finished | Jan 03 12:42:02 PM PST 24 |
| Peak memory | 145412 kb |
| Host | smart-df2f71bc-52e1-4e9c-89a5-97aad089b784 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674861493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1674861493 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.4280023668 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10301306 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:41:05 PM PST 24 |
| Finished | Jan 03 12:42:35 PM PST 24 |
| Peak memory | 145400 kb |
| Host | smart-380ca33d-8d2f-4cdd-b36c-ee50fd816f97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280023668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.4280023668 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/7.prim_async_alert.3578235242 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11475900 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:40:27 PM PST 24 |
| Finished | Jan 03 12:41:59 PM PST 24 |
| Peak memory | 145356 kb |
| Host | smart-8b1f9c82-ae03-464f-88cd-5c80371bda6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3578235242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3578235242 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.2235311510 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12114448 ps |
| CPU time | 0.41 seconds |
| Started | Jan 03 12:40:58 PM PST 24 |
| Finished | Jan 03 12:42:27 PM PST 24 |
| Peak memory | 145356 kb |
| Host | smart-68e9d724-84d9-4436-9523-b0f77c4d2f50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235311510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2235311510 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.2673876654 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11175155 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:40:58 PM PST 24 |
| Finished | Jan 03 12:42:27 PM PST 24 |
| Peak memory | 145356 kb |
| Host | smart-fe118bed-549f-4c32-bee8-6f61548dac96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673876654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2673876654 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2146685541 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 28876665 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:35:42 PM PST 24 |
| Finished | Jan 03 12:37:23 PM PST 24 |
| Peak memory | 145596 kb |
| Host | smart-a9b602d7-2a71-4090-8c4c-56ca150fb932 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2146685541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2146685541 |
| Directory | /workspace/1.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1417979080 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30211600 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:35:19 PM PST 24 |
| Finished | Jan 03 12:36:52 PM PST 24 |
| Peak memory | 145620 kb |
| Host | smart-17d5d275-f3db-4a9a-a7ae-ecdd70628228 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1417979080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1417979080 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2942506143 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29802910 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:35:41 PM PST 24 |
| Finished | Jan 03 12:37:26 PM PST 24 |
| Peak memory | 145500 kb |
| Host | smart-23399c0a-b7bc-43fb-adbb-f9b9d1880e3e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2942506143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2942506143 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2019046149 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 29089624 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:35:30 PM PST 24 |
| Finished | Jan 03 12:37:05 PM PST 24 |
| Peak memory | 145496 kb |
| Host | smart-1f22bc8f-6fe1-4f10-9ce7-220591a7e7b4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2019046149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2019046149 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4134730378 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 28572409 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:35:19 PM PST 24 |
| Finished | Jan 03 12:36:46 PM PST 24 |
| Peak memory | 145584 kb |
| Host | smart-17c5d537-b61e-4852-8863-8201de142425 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4134730378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4134730378 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2080668715 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 30259607 ps |
| CPU time | 0.4 seconds |
| Started | Jan 03 12:35:19 PM PST 24 |
| Finished | Jan 03 12:36:49 PM PST 24 |
| Peak memory | 145564 kb |
| Host | smart-3c4712ec-ef39-4bb0-904c-2d2a371cc07a |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2080668715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2080668715 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2039408503 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29555324 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:35:16 PM PST 24 |
| Finished | Jan 03 12:36:41 PM PST 24 |
| Peak memory | 145532 kb |
| Host | smart-085a55f7-fccb-43d5-afc4-e25d29d94b12 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2039408503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2039408503 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4273812643 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 31320770 ps |
| CPU time | 0.4 seconds |
| Started | Jan 03 12:35:42 PM PST 24 |
| Finished | Jan 03 12:37:24 PM PST 24 |
| Peak memory | 145408 kb |
| Host | smart-61d27164-303a-4633-a84b-c21290777fc3 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4273812643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4273812643 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.3461581784 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 28493491 ps |
| CPU time | 0.4 seconds |
| Started | Jan 03 12:35:16 PM PST 24 |
| Finished | Jan 03 12:36:40 PM PST 24 |
| Peak memory | 145452 kb |
| Host | smart-85faa404-ee62-4970-900b-8a71df551df6 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3461581784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.3461581784 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1820245135 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 30009136 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:35:16 PM PST 24 |
| Finished | Jan 03 12:36:47 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-d18fe6e7-b93d-4157-9b45-c46ab3de7ac4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1820245135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1820245135 |
| Directory | /workspace/4.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3472110643 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 30654657 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:35:29 PM PST 24 |
| Finished | Jan 03 12:36:59 PM PST 24 |
| Peak memory | 145620 kb |
| Host | smart-1ce0628c-5322-44e6-9ed8-5a1380f7a0ba |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3472110643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3472110643 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2100139432 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 32364202 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:35:46 PM PST 24 |
| Finished | Jan 03 12:37:18 PM PST 24 |
| Peak memory | 145524 kb |
| Host | smart-543140fb-29d7-4619-850d-133b962bbf0d |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2100139432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2100139432 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3296750015 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 30465723 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:35:15 PM PST 24 |
| Finished | Jan 03 12:36:41 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-c32a48e0-cf1a-4c7c-a17a-2c801fff3782 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3296750015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3296750015 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3137827418 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 8898776 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:29 PM PST 24 |
| Finished | Jan 03 12:37:55 PM PST 24 |
| Peak memory | 144908 kb |
| Host | smart-f979da32-0ddf-4637-9b58-8dc047be300c |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3137827418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3137827418 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.4243161599 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10436374 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:40 PM PST 24 |
| Finished | Jan 03 12:38:21 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-8310c49f-7604-4755-a596-8fc8c6414c28 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4243161599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.4243161599 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.4013772620 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 8669251 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:36:51 PM PST 24 |
| Finished | Jan 03 12:38:21 PM PST 24 |
| Peak memory | 144900 kb |
| Host | smart-1ec95eab-8d8c-4a6c-bf31-ff4787e9416f |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4013772620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4013772620 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.3962476942 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9171608 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:20 PM PST 24 |
| Finished | Jan 03 12:38:21 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-0c039315-c9b5-404b-84f0-ff3ac909d488 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3962476942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3962476942 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.2887027789 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 10439746 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:16 PM PST 24 |
| Finished | Jan 03 12:38:04 PM PST 24 |
| Peak memory | 145012 kb |
| Host | smart-34bf9162-8ec9-4044-968e-cfb1b77a57a3 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2887027789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2887027789 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.662724254 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8363594 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:36:27 PM PST 24 |
| Finished | Jan 03 12:37:53 PM PST 24 |
| Peak memory | 145008 kb |
| Host | smart-a0e73683-a22f-4e13-bf8b-7c792be09140 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=662724254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.662724254 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.1291417024 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9926758 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:14 PM PST 24 |
| Finished | Jan 03 12:38:06 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-02a0dd86-f332-4cd3-ad59-a4dddc8d4cc2 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1291417024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1291417024 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.1795670076 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8547219 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:36:23 PM PST 24 |
| Finished | Jan 03 12:38:06 PM PST 24 |
| Peak memory | 144940 kb |
| Host | smart-0f4bf720-cdfd-4384-9f53-a03457dfab4a |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1795670076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1795670076 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.2537983989 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10494445 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:27 PM PST 24 |
| Finished | Jan 03 12:37:56 PM PST 24 |
| Peak memory | 144988 kb |
| Host | smart-6ec8f13d-9ac5-4cc9-9797-c742e2733133 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2537983989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2537983989 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.2179906139 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 9558945 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:25 PM PST 24 |
| Finished | Jan 03 12:38:02 PM PST 24 |
| Peak memory | 144984 kb |
| Host | smart-466103c0-d253-4310-a14f-2cca46cb7c48 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2179906139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2179906139 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.1883470561 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9812012 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:36:56 PM PST 24 |
| Finished | Jan 03 12:38:04 PM PST 24 |
| Peak memory | 145000 kb |
| Host | smart-5ccb15ad-ef3b-4180-9e63-cc4516c4395b |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1883470561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1883470561 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.140172392 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8953292 ps |
| CPU time | 0.36 seconds |
| Started | Jan 03 12:36:35 PM PST 24 |
| Finished | Jan 03 12:37:59 PM PST 24 |
| Peak memory | 144804 kb |
| Host | smart-1c78b673-fcde-4cf3-8dc9-aa1b5bfdb504 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=140172392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.140172392 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.2029470024 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9300054 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:22 PM PST 24 |
| Finished | Jan 03 12:37:53 PM PST 24 |
| Peak memory | 144972 kb |
| Host | smart-fb2cb583-d806-40ab-b16d-1cf7b0895e33 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2029470024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2029470024 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.2280497552 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9002190 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:39 PM PST 24 |
| Finished | Jan 03 12:37:55 PM PST 24 |
| Peak memory | 144924 kb |
| Host | smart-6ac83a85-5d15-4cf0-8c00-dbdc414b2939 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2280497552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2280497552 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.1717184056 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8933144 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:37:08 PM PST 24 |
| Finished | Jan 03 12:38:19 PM PST 24 |
| Peak memory | 145000 kb |
| Host | smart-934555a4-768d-4b31-b9a5-a58832aa94d9 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1717184056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1717184056 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.1486263832 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9050189 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:36:30 PM PST 24 |
| Finished | Jan 03 12:38:08 PM PST 24 |
| Peak memory | 144936 kb |
| Host | smart-d9b37bce-46e2-4ce1-b841-eb80d533f277 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1486263832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.1486263832 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3029216669 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9514626 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:36:31 PM PST 24 |
| Finished | Jan 03 12:38:06 PM PST 24 |
| Peak memory | 144920 kb |
| Host | smart-08cb1d61-4077-4d0b-8e6e-3133621913f5 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3029216669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3029216669 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.227963721 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26771222 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:43:54 PM PST 24 |
| Finished | Jan 03 12:45:20 PM PST 24 |
| Peak memory | 144968 kb |
| Host | smart-282dbfe7-f209-4e22-ac50-8d1145afe838 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=227963721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.227963721 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2239023361 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 28940807 ps |
| CPU time | 0.4 seconds |
| Started | Jan 03 12:44:43 PM PST 24 |
| Finished | Jan 03 12:46:07 PM PST 24 |
| Peak memory | 144884 kb |
| Host | smart-f0b61eda-ffd3-4a09-9849-a7fcaea8b4b3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2239023361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2239023361 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2265180669 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26721976 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:44:09 PM PST 24 |
| Finished | Jan 03 12:45:51 PM PST 24 |
| Peak memory | 144904 kb |
| Host | smart-678c48d6-953c-452b-b126-9711bf1ec20c |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2265180669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2265180669 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1263237661 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27536883 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:44:19 PM PST 24 |
| Finished | Jan 03 12:45:38 PM PST 24 |
| Peak memory | 145012 kb |
| Host | smart-760b3e6a-0712-4e8b-9e3e-4e063664ff17 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1263237661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1263237661 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1535036522 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26136785 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:44:21 PM PST 24 |
| Finished | Jan 03 12:45:52 PM PST 24 |
| Peak memory | 144948 kb |
| Host | smart-30a3137e-d0bd-4cec-9d0a-bc70501cc2ca |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1535036522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1535036522 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2801208315 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 29297732 ps |
| CPU time | 0.37 seconds |
| Started | Jan 03 12:43:46 PM PST 24 |
| Finished | Jan 03 12:45:30 PM PST 24 |
| Peak memory | 144960 kb |
| Host | smart-85cb6ef6-9c65-4c66-9108-4a91ac7d6b01 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2801208315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2801208315 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.136443675 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26978062 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:44:10 PM PST 24 |
| Finished | Jan 03 12:45:25 PM PST 24 |
| Peak memory | 144964 kb |
| Host | smart-62b98ec2-9987-40f8-9d42-086323629e4e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=136443675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.136443675 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2927224885 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 26969175 ps |
| CPU time | 0.41 seconds |
| Started | Jan 03 12:43:56 PM PST 24 |
| Finished | Jan 03 12:45:31 PM PST 24 |
| Peak memory | 144932 kb |
| Host | smart-24d2078d-1873-4705-a053-d6bc82cf6b03 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2927224885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2927224885 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1604501374 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 26727355 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:43:39 PM PST 24 |
| Finished | Jan 03 12:45:00 PM PST 24 |
| Peak memory | 144952 kb |
| Host | smart-d4292f8f-c44d-4138-945c-47163492889e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1604501374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1604501374 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3594681091 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 29355747 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:43:47 PM PST 24 |
| Finished | Jan 03 12:45:04 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-f780292e-9978-4930-8e87-b0d85bb8ef30 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3594681091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3594681091 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.354684377 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 25112927 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:43:42 PM PST 24 |
| Finished | Jan 03 12:45:33 PM PST 24 |
| Peak memory | 145048 kb |
| Host | smart-f7b1a204-ac29-47fb-a641-1b4721f65f94 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=354684377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.354684377 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3039421628 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25877269 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:43:51 PM PST 24 |
| Finished | Jan 03 12:45:07 PM PST 24 |
| Peak memory | 144952 kb |
| Host | smart-e80a89fd-07df-441f-95d2-1597fd3442f4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3039421628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3039421628 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3713683803 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27223108 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:44:13 PM PST 24 |
| Finished | Jan 03 12:45:34 PM PST 24 |
| Peak memory | 145044 kb |
| Host | smart-78ca9dd1-fd78-418d-a57d-15ba05662109 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3713683803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3713683803 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3106998584 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 29607336 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:43:59 PM PST 24 |
| Finished | Jan 03 12:45:45 PM PST 24 |
| Peak memory | 144956 kb |
| Host | smart-c6955035-76a4-44a1-98d6-1f1b52f8d89a |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3106998584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3106998584 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2792268323 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28121540 ps |
| CPU time | 0.42 seconds |
| Started | Jan 03 12:43:53 PM PST 24 |
| Finished | Jan 03 12:45:10 PM PST 24 |
| Peak memory | 144880 kb |
| Host | smart-5d4a10f1-7caa-4f5e-bf26-675fb83c584e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2792268323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2792268323 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1277896657 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 26717271 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:44:03 PM PST 24 |
| Finished | Jan 03 12:45:28 PM PST 24 |
| Peak memory | 145044 kb |
| Host | smart-d6f3b462-21af-40ee-a6bd-2bc68c5f5c9d |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1277896657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1277896657 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1441127449 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 28348962 ps |
| CPU time | 0.4 seconds |
| Started | Jan 03 12:44:01 PM PST 24 |
| Finished | Jan 03 12:45:16 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-e9a1deda-326b-4eb9-8aa1-133d09b08123 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1441127449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1441127449 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2431746324 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27820671 ps |
| CPU time | 0.38 seconds |
| Started | Jan 03 12:44:01 PM PST 24 |
| Finished | Jan 03 12:45:17 PM PST 24 |
| Peak memory | 144944 kb |
| Host | smart-e428ff57-4b0e-43cf-b9cc-29d5b3f4d343 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2431746324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2431746324 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2833074834 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 26859459 ps |
| CPU time | 0.39 seconds |
| Started | Jan 03 12:44:01 PM PST 24 |
| Finished | Jan 03 12:45:16 PM PST 24 |
| Peak memory | 144940 kb |
| Host | smart-a1147b58-8b3b-44b8-957a-79b08695e736 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2833074834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2833074834 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |