Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T5,T9
1	0	Covered	T10

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T8	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T2,T11,T12
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T13,T11,T14
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T15,T16,T17

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	114858	87149	0	120
AlertKnownO_A	115412	88435	0	0
InBandInitRequest_A	115412	3149	0	0
InBandInitSequence_A	115412	287	0	0
InitReq_A	115412	570	0	0
IntegFailKnownO_A	115412	88435	0	0
NoSpuriousAlertsDuringInit_A	115412	12556	0	0
NoSpuriousPingOksDuringInit_A	115412	12283	0	0
PingDiffOk_A	114718	87741	0	0
PingOkBypassDuringInit_A	115412	41	0	28
PingOkKnownO_A	115412	88435	0	0
PingPKnownO_A	115412	88435	0	0
PingPending_A	115412	632	0	88
PingRequest0_A	115412	0	0	60
PingResponse0_A	115412	589	0	0
gen_async_assert.Alert_A	63912	1037	0	0
gen_async_assert.PingResponse1_A	63912	265	0	0
gen_async_assert.SigInt_A	63912	200	0	82
gen_sync_assert.Alert_A	51500	2246	0	0
gen_sync_assert.PingResponse1_A	51500	248	0	0
gen_sync_assert.SigInt_A	51500	28	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114858	87149	0	120
T1	1176	1007	0	2
T2	1200	1020	0	2
T3	1057	969	0	2
T5	1102	1042	0	2
T8	1253	1097	0	2
T9	1194	1054	0	2
T15	1058	988	0	2
T18	1080	1007	0	2
T19	1079	1017	0	2
T20	1102	1025	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	88435	0	0
T1	1191	1026	0	0
T2	1214	1038	0	0
T3	1072	986	0	0
T5	1118	1060	0	0
T8	1268	1116	0	0
T9	1209	1073	0	0
T15	1071	1003	0	0
T18	1095	1024	0	0
T19	1094	1034	0	0
T20	1116	1041	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	3149	0	0
T1	1191	29	0	0
T2	1214	50	0	0
T3	1072	33	0	0
T5	1118	47	0	0
T8	1268	64	0	0
T9	1209	70	0	0
T15	1071	54	0	0
T18	1095	61	0	0
T19	1094	50	0	0
T20	1116	60	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	287	0	0
T1	1191	1	0	0
T2	1214	1	0	0
T3	1072	1	0	0
T5	1118	1	0	0
T8	1268	4	0	0
T9	1209	3	0	0
T15	1071	4	0	0
T18	1095	3	0	0
T19	1094	2	0	0
T20	1116	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	570	0	0
T1	1191	7	0	0
T2	1214	10	0	0
T3	1072	6	0	0
T5	1118	11	0	0
T8	1268	14	0	0
T9	1209	12	0	0
T15	1071	9	0	0
T18	1095	8	0	0
T19	1094	10	0	0
T20	1116	10	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	88435	0	0
T1	1191	1026	0	0
T2	1214	1038	0	0
T3	1072	986	0	0
T5	1118	1060	0	0
T8	1268	1116	0	0
T9	1209	1073	0	0
T15	1071	1003	0	0
T18	1095	1024	0	0
T19	1094	1034	0	0
T20	1116	1041	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	12556	0	0
T1	1191	159	0	0
T2	1214	214	0	0
T3	1072	132	0	0
T5	1118	213	0	0
T8	1268	273	0	0
T9	1209	258	0	0
T15	1071	182	0	0
T18	1095	167	0	0
T19	1094	191	0	0
T20	1116	200	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	12283	0	0
T1	1191	159	0	0
T2	1214	211	0	0
T3	1072	131	0	0
T5	1118	201	0	0
T8	1268	263	0	0
T9	1209	237	0	0
T15	1071	179	0	0
T18	1095	165	0	0
T19	1094	189	0	0
T20	1116	197	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114718	87741	0	0
T1	1176	1011	0	0
T2	1196	1020	0	0
T3	1057	971	0	0
T5	1104	1046	0	0
T8	1250	1098	0	0
T9	1192	1056	0	0
T15	1055	987	0	0
T18	1080	1009	0	0
T19	1081	1021	0	0
T20	1102	1027	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	41	0	28
T2	1214	1	0	0
T3	1072	1	0	0
T5	1118	0	0	0
T6	1119	1	0	0
T7	0	2	0	0
T8	1268	0	0	0
T9	1209	1	0	0
T13	0	2	0	0
T15	1071	1	0	0
T17	0	2	0	0
T18	1095	0	0	0
T19	1094	0	0	0
T20	1116	1	0	0
T21	0	1	0	0
T22	0	0	0	1
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	88435	0	0
T1	1191	1026	0	0
T2	1214	1038	0	0
T3	1072	986	0	0
T5	1118	1060	0	0
T8	1268	1116	0	0
T9	1209	1073	0	0
T15	1071	1003	0	0
T18	1095	1024	0	0
T19	1094	1034	0	0
T20	1116	1041	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	88435	0	0
T1	1191	1026	0	0
T2	1214	1038	0	0
T3	1072	986	0	0
T5	1118	1060	0	0
T8	1268	1116	0	0
T9	1209	1073	0	0
T15	1071	1003	0	0
T18	1095	1024	0	0
T19	1094	1034	0	0
T20	1116	1041	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	632	0	88
T1	1191	11	0	1
T2	1214	11	0	1
T3	1072	11	0	1
T5	1118	11	0	1
T8	1268	11	0	1
T9	1209	11	0	1
T15	1071	11	0	1
T18	1095	11	0	1
T19	1094	11	0	1
T20	1116	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	0	0	60

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115412	589	0	0
T1	1191	10	0	0
T2	1214	10	0	0
T3	1072	10	0	0
T5	1118	8	0	0
T8	1268	10	0	0
T9	1209	10	0	0
T15	1071	10	0	0
T18	1095	10	0	0
T19	1094	10	0	0
T20	1116	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63912	1037	0	0
T1	1191	10	0	0
T2	1214	5	0	0
T3	1072	11	0	0
T5	1118	7	0	0
T8	1268	5	0	0
T9	1209	6	0	0
T15	1071	7	0	0
T18	1095	8	0	0
T19	1094	5	0	0
T20	1116	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63912	265	0	0
T1	1191	10	0	0
T2	1214	8	0	0
T3	1072	9	0	0
T5	1118	8	0	0
T8	1268	9	0	0
T9	1209	6	0	0
T15	1071	8	0	0
T18	1095	9	0	0
T19	1094	9	0	0
T20	1116	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63912	200	0	82
T1	1191	6	0	3
T2	1214	5	0	3
T3	1072	5	0	2
T5	1118	6	0	3
T8	1268	8	0	3
T9	1209	6	0	3
T15	1071	7	0	3
T18	1095	6	0	3
T19	1094	7	0	2
T20	1116	5	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51500	2246	0	0
T22	1015	10	0	0
T23	1060	7	0	0
T24	902	9	0	0
T25	1003	11	0	0
T26	931	9	0	0
T27	825	9	0	0
T32	944	6	0	0
T33	878	9	0	0
T34	818	10	0	0
T35	892	8	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51500	248	0	0
T22	1015	8	0	0
T23	1060	9	0	0
T24	902	7	0	0
T25	1003	9	0	0
T26	931	7	0	0
T27	825	8	0	0
T32	944	10	0	0
T33	878	10	0	0
T34	818	10	0	0
T35	892	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51500	28	0	0
T22	1015	1	0	0
T23	1060	1	0	0
T24	902	1	0	0
T25	1003	1	0	0
T26	931	1	0	0
T27	825	1	0	0
T32	944	1	0	0
T33	878	1	0	0
T34	818	1	0	0
T35	892	1	0	0