4d88b9516c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | prim_alert_request_test | prim_async_alert | 0.420s | 12.744us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.450s | 29.048us | 19 | 20 | 95.00 | ||
| prim_sync_alert | 0.430s | 8.592us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 0.450s | 26.323us | 20 | 20 | 100.00 | ||
| V1 | prim_alert_test | prim_async_alert | 0.420s | 12.744us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.450s | 29.048us | 19 | 20 | 95.00 | ||
| prim_sync_alert | 0.430s | 8.592us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 0.450s | 26.323us | 20 | 20 | 100.00 | ||
| V1 | prim_alert_ping_request_test | prim_async_alert | 0.420s | 12.744us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.450s | 29.048us | 19 | 20 | 95.00 | ||
| prim_sync_alert | 0.430s | 8.592us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 0.450s | 26.323us | 20 | 20 | 100.00 | ||
| V1 | prim_alert_integrity_errors_test | prim_async_alert | 0.420s | 12.744us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.450s | 29.048us | 19 | 20 | 95.00 | ||
| prim_sync_alert | 0.430s | 8.592us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 0.450s | 26.323us | 20 | 20 | 100.00 | ||
| V1 | TOTAL | 79 | 80 | 98.75 | |||
| V2 | prim_alert_init_trigger_test | prim_async_alert | 0.420s | 12.744us | 20 | 20 | 100.00 |
| prim_async_fatal_alert | 0.450s | 29.048us | 19 | 20 | 95.00 | ||
| prim_sync_alert | 0.430s | 8.592us | 20 | 20 | 100.00 | ||
| prim_sync_fatal_alert | 0.450s | 26.323us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 0 | 0 | -- | |||
| V2S | TOTAL | 0 | 0 | -- | |||
| V3 | prim_alert_gate_sender_clk_rst_test | prim_alert_gate_sender_clk_rst_test | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 79 | 80 | 98.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 0 | 0 | 0.00 |
Offending '$rose(alert_tx_o.alert_p)' has 1 failures:
4.prim_async_fatal_alert.97194648464591026503412523320326604457330407717347378724891628271591165830072
Line 265, in log /container/opentitan-public/scratch/os_regression/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest/run.log
Offending '$rose(alert_tx_o.alert_p)'
UVM_ERROR ../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv(328) @ 27058000: reporter [ASSERT FAILED] PingHs_A
[prim_alert_seq] Ping request sequence[5] finished!
[prim_alert_seq] Ping request sequence[6] finished!
[prim_alert_seq] Ping request sequence[7] finished!
Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/prim_alert-sim-vcs/cov_merge/merged.vdb/cov_merge.log
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Error-[URG-NLCW] No license key
URG failed to get a license key. Number of attempts to get a license key
exceeded the limit (500).
Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
file.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:220: cov_merge] Error 1
Job killed most likely because its dependent job failed. has 1 failures: