Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T9

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T7	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T10,T11
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T3,T12,T13
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T7,T14,T15
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	144282	108798	0	152
AlertKnownO_A	144934	110363	0	0
InBandInitRequest_A	144934	3973	0	0
InBandInitSequence_A	144934	402	0	0
InitReq_A	144934	742	0	0
IntegFailKnownO_A	144934	110363	0	0
NoSpuriousAlertsDuringInit_A	144934	15201	0	0
NoSpuriousPingOksDuringInit_A	144934	14818	0	0
PingDiffOk_A	144085	109514	0	0
PingOkBypassDuringInit_A	144934	44	0	40
PingOkKnownO_A	144934	110363	0	0
PingPKnownO_A	144934	110363	0	0
PingPending_A	144934	796	0	116
PingRequest0_A	144934	0	0	76
PingResponse0_A	144934	735	0	0
gen_async_assert.Alert_A	70994	1112	0	0
gen_async_assert.PingResponse1_A	70994	293	0	0
gen_async_assert.SigInt_A	70994	223	0	86
gen_sync_assert.Alert_A	73940	3179	0	0
gen_sync_assert.PingResponse1_A	73940	351	0	0
gen_sync_assert.SigInt_A	73940	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144282	108798	0	152
T1	1175	1121	0	2
T2	1274	1083	0	2
T3	1153	990	0	2
T7	1199	1031	0	2
T8	1077	1004	0	2
T10	1107	1035	0	2
T11	1146	1083	0	2
T16	1021	957	0	2
T17	1084	987	0	2
T18	1091	1019	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	110363	0	0
T1	1190	1138	0	0
T2	1289	1102	0	0
T3	1168	1009	0	0
T7	1213	1049	0	0
T8	1093	1022	0	0
T10	1121	1051	0	0
T11	1160	1099	0	0
T16	1036	974	0	0
T17	1100	1005	0	0
T18	1106	1036	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	3973	0	0
T1	1190	70	0	0
T2	1289	65	0	0
T3	1168	39	0	0
T7	1213	60	0	0
T8	1093	53	0	0
T10	1121	65	0	0
T11	1160	61	0	0
T16	1036	32	0	0
T17	1100	46	0	0
T18	1106	51	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	402	0	0
T1	1190	1	0	0
T2	1289	2	0	0
T3	1168	2	0	0
T7	1213	2	0	0
T8	1093	3	0	0
T10	1121	3	0	0
T11	1160	1	0	0
T16	1036	1	0	0
T17	1100	2	0	0
T18	1106	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	742	0	0
T1	1190	15	0	0
T2	1289	12	0	0
T3	1168	7	0	0
T7	1213	11	0	0
T8	1093	10	0	0
T10	1121	11	0	0
T11	1160	13	0	0
T16	1036	6	0	0
T17	1100	7	0	0
T18	1106	10	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	110363	0	0
T1	1190	1138	0	0
T2	1289	1102	0	0
T3	1168	1009	0	0
T7	1213	1049	0	0
T8	1093	1022	0	0
T10	1121	1051	0	0
T11	1160	1099	0	0
T16	1036	974	0	0
T17	1100	1005	0	0
T18	1106	1036	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	15201	0	0
T1	1190	289	0	0
T2	1289	252	0	0
T3	1168	157	0	0
T7	1213	222	0	0
T8	1093	196	0	0
T10	1121	207	0	0
T11	1160	256	0	0
T16	1036	127	0	0
T17	1100	148	0	0
T18	1106	194	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	14818	0	0
T1	1190	279	0	0
T2	1289	238	0	0
T3	1168	145	0	0
T7	1213	219	0	0
T8	1093	194	0	0
T10	1121	205	0	0
T11	1160	229	0	0
T16	1036	113	0	0
T17	1100	144	0	0
T18	1106	181	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144085	109514	0	0
T1	1172	1120	0	0
T2	1277	1090	0	0
T3	1152	993	0	0
T7	1199	1035	0	0
T8	1075	1004	0	0
T10	1102	1032	0	0
T11	1148	1087	0	0
T16	1018	956	0	0
T17	1087	992	0	0
T18	1089	1019	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	44	0	40
T7	1213	0	0	0
T8	1093	0	0	0
T9	0	0	0	1
T11	1160	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	1120	0	0	0
T15	1101	2	0	0
T16	1036	0	0	0
T17	1100	0	0	0
T18	1106	1	0	0
T19	0	1	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	2	0	1
T24	1104	0	0	0
T25	1096	0	0	0
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	110363	0	0
T1	1190	1138	0	0
T2	1289	1102	0	0
T3	1168	1009	0	0
T7	1213	1049	0	0
T8	1093	1022	0	0
T10	1121	1051	0	0
T11	1160	1099	0	0
T16	1036	974	0	0
T17	1100	1005	0	0
T18	1106	1036	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	110363	0	0
T1	1190	1138	0	0
T2	1289	1102	0	0
T3	1168	1009	0	0
T7	1213	1049	0	0
T8	1093	1022	0	0
T10	1121	1051	0	0
T11	1160	1099	0	0
T16	1036	974	0	0
T17	1100	1005	0	0
T18	1106	1036	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	796	0	116
T1	1190	11	0	1
T2	1289	11	0	1
T3	1168	11	0	1
T7	1213	11	0	1
T8	1093	11	0	1
T10	1121	11	0	1
T11	1160	11	0	1
T16	1036	11	0	1
T17	1100	11	0	1
T18	1106	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	0	0	76

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144934	735	0	0
T1	1190	10	0	0
T2	1289	9	0	0
T3	1168	10	0	0
T7	1213	9	0	0
T8	1093	8	0	0
T10	1121	10	0	0
T11	1160	10	0	0
T16	1036	10	0	0
T17	1100	10	0	0
T18	1106	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70994	1112	0	0
T1	1190	3	0	0
T2	1289	5	0	0
T3	1168	7	0	0
T7	1213	7	0	0
T8	1093	7	0	0
T10	1121	7	0	0
T11	1160	6	0	0
T16	1036	10	0	0
T17	1100	8	0	0
T18	1106	8	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70994	293	0	0
T1	1190	10	0	0
T2	1289	9	0	0
T3	1168	10	0	0
T7	1213	8	0	0
T8	1093	8	0	0
T10	1121	9	0	0
T11	1160	9	0	0
T16	1036	10	0	0
T17	1100	8	0	0
T18	1106	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70994	223	0	86
T1	1190	5	0	2
T2	1289	6	0	2
T3	1168	6	0	3
T7	1213	7	0	2
T8	1093	6	0	3
T10	1121	6	0	3
T11	1160	5	0	2
T16	1036	8	0	3
T17	1100	6	0	2
T18	1106	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73940	3179	0	0
T26	961	9	0	0
T27	841	8	0	0
T28	925	11	0	0
T29	1074	8	0	0
T30	941	9	0	0
T31	888	7	0	0
T34	922	7	0	0
T35	845	9	0	0
T36	853	13	0	0
T37	843	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73940	351	0	0
T26	961	6	0	0
T27	841	8	0	0
T28	925	9	0	0
T29	1074	9	0	0
T30	941	10	0	0
T31	888	10	0	0
T34	922	10	0	0
T35	845	9	0	0
T36	853	10	0	0
T37	843	8	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73940	40	0	0
T26	961	1	0	0
T27	841	1	0	0
T28	925	1	0	0
T29	1074	1	0	0
T30	941	1	0	0
T31	888	1	0	0
T34	922	1	0	0
T35	845	1	0	0
T36	853	1	0	0
T37	843	1	0	0