Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
89.27 89.27 100.00 100.00 93.75 93.75 96.43 96.43 82.14 82.14 95.83 95.83 67.44 67.44 /workspace/coverage/default/2.prim_async_alert.617712381
91.80 2.53 100.00 0.00 93.75 0.00 96.43 0.00 85.71 3.57 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/0.prim_sync_alert.3487962860
93.90 2.11 100.00 0.00 95.83 2.08 100.00 3.57 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2288112304
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/12.prim_async_alert.54816433
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2470443764
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/10.prim_sync_alert.2307571272

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.4050410487
/workspace/coverage/default/1.prim_async_alert.234682314
/workspace/coverage/default/10.prim_async_alert.485844449
/workspace/coverage/default/11.prim_async_alert.687695481
/workspace/coverage/default/13.prim_async_alert.3099574225
/workspace/coverage/default/14.prim_async_alert.1792058387
/workspace/coverage/default/15.prim_async_alert.696621237
/workspace/coverage/default/16.prim_async_alert.3225020501
/workspace/coverage/default/17.prim_async_alert.4063105740
/workspace/coverage/default/18.prim_async_alert.1096894213
/workspace/coverage/default/19.prim_async_alert.1197679464
/workspace/coverage/default/3.prim_async_alert.551370726
/workspace/coverage/default/4.prim_async_alert.2866198064
/workspace/coverage/default/5.prim_async_alert.2497195562
/workspace/coverage/default/6.prim_async_alert.272319677
/workspace/coverage/default/7.prim_async_alert.3332531555
/workspace/coverage/default/8.prim_async_alert.355731299
/workspace/coverage/default/9.prim_async_alert.3520259207
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3974452913
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3209578958
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.31423359
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2416083645
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.433870524
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3706380820
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2254847079
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1022973620
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2909269117
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4028945357
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2922099886
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2008034796
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3670266847
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.55882742
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3111156867
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.834252530
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3581004921
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3729914224
/workspace/coverage/sync_alert/1.prim_sync_alert.3363058102
/workspace/coverage/sync_alert/11.prim_sync_alert.875297877
/workspace/coverage/sync_alert/12.prim_sync_alert.970245206
/workspace/coverage/sync_alert/13.prim_sync_alert.3917121304
/workspace/coverage/sync_alert/14.prim_sync_alert.2274698996
/workspace/coverage/sync_alert/15.prim_sync_alert.2602705353
/workspace/coverage/sync_alert/16.prim_sync_alert.1118722919
/workspace/coverage/sync_alert/17.prim_sync_alert.572804369
/workspace/coverage/sync_alert/18.prim_sync_alert.817663024
/workspace/coverage/sync_alert/19.prim_sync_alert.3577219687
/workspace/coverage/sync_alert/2.prim_sync_alert.1799205447
/workspace/coverage/sync_alert/3.prim_sync_alert.4103038100
/workspace/coverage/sync_alert/4.prim_sync_alert.2431057006
/workspace/coverage/sync_alert/5.prim_sync_alert.3040463082
/workspace/coverage/sync_alert/6.prim_sync_alert.3510005554
/workspace/coverage/sync_alert/7.prim_sync_alert.3656109235
/workspace/coverage/sync_alert/8.prim_sync_alert.2630861393
/workspace/coverage/sync_alert/9.prim_sync_alert.1144568871
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2269363293
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2467393256
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4139454907
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.768944313
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4063477764
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3657063524
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.148963154
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.361289974
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1563592026
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1609511534
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.326586076
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2838078535
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.287033682
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1746086654
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1043104240
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2723530168
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1019135394
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2220031814
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.860374159
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1745859536



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/4.prim_async_alert.2866198064 Feb 07 12:25:01 PM PST 24 Feb 07 12:25:03 PM PST 24 11580292 ps
T2 /workspace/coverage/default/13.prim_async_alert.3099574225 Feb 07 12:24:22 PM PST 24 Feb 07 12:24:23 PM PST 24 11459322 ps
T3 /workspace/coverage/default/16.prim_async_alert.3225020501 Feb 07 12:25:41 PM PST 24 Feb 07 12:25:42 PM PST 24 11493736 ps
T9 /workspace/coverage/default/10.prim_async_alert.485844449 Feb 07 12:25:21 PM PST 24 Feb 07 12:25:25 PM PST 24 12143501 ps
T16 /workspace/coverage/default/1.prim_async_alert.234682314 Feb 07 12:20:11 PM PST 24 Feb 07 12:20:13 PM PST 24 11333791 ps
T17 /workspace/coverage/default/17.prim_async_alert.4063105740 Feb 07 12:20:23 PM PST 24 Feb 07 12:20:25 PM PST 24 11715587 ps
T6 /workspace/coverage/default/19.prim_async_alert.1197679464 Feb 07 12:24:19 PM PST 24 Feb 07 12:24:20 PM PST 24 11108494 ps
T18 /workspace/coverage/default/3.prim_async_alert.551370726 Feb 07 12:20:20 PM PST 24 Feb 07 12:20:21 PM PST 24 11133280 ps
T10 /workspace/coverage/default/2.prim_async_alert.617712381 Feb 07 12:21:20 PM PST 24 Feb 07 12:21:21 PM PST 24 11695631 ps
T7 /workspace/coverage/default/14.prim_async_alert.1792058387 Feb 07 12:24:18 PM PST 24 Feb 07 12:24:20 PM PST 24 11231483 ps
T19 /workspace/coverage/default/18.prim_async_alert.1096894213 Feb 07 12:26:00 PM PST 24 Feb 07 12:26:03 PM PST 24 11129260 ps
T13 /workspace/coverage/default/7.prim_async_alert.3332531555 Feb 07 12:24:22 PM PST 24 Feb 07 12:24:23 PM PST 24 12018395 ps
T20 /workspace/coverage/default/5.prim_async_alert.2497195562 Feb 07 12:25:40 PM PST 24 Feb 07 12:25:42 PM PST 24 11549599 ps
T42 /workspace/coverage/default/9.prim_async_alert.3520259207 Feb 07 12:24:22 PM PST 24 Feb 07 12:24:23 PM PST 24 10759824 ps
T21 /workspace/coverage/default/8.prim_async_alert.355731299 Feb 07 12:20:30 PM PST 24 Feb 07 12:20:31 PM PST 24 12005443 ps
T43 /workspace/coverage/default/6.prim_async_alert.272319677 Feb 07 12:20:23 PM PST 24 Feb 07 12:20:24 PM PST 24 11103102 ps
T14 /workspace/coverage/default/12.prim_async_alert.54816433 Feb 07 12:24:18 PM PST 24 Feb 07 12:24:20 PM PST 24 11648894 ps
T44 /workspace/coverage/default/15.prim_async_alert.696621237 Feb 07 12:24:22 PM PST 24 Feb 07 12:24:23 PM PST 24 11609870 ps
T45 /workspace/coverage/default/11.prim_async_alert.687695481 Feb 07 12:25:22 PM PST 24 Feb 07 12:25:25 PM PST 24 11066501 ps
T22 /workspace/coverage/default/0.prim_async_alert.4050410487 Feb 07 12:20:19 PM PST 24 Feb 07 12:20:21 PM PST 24 10472976 ps
T23 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2254847079 Feb 07 12:54:46 PM PST 24 Feb 07 12:54:51 PM PST 24 28151577 ps
T24 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.834252530 Feb 07 12:54:51 PM PST 24 Feb 07 12:55:00 PM PST 24 29929101 ps
T36 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.31423359 Feb 07 12:54:46 PM PST 24 Feb 07 12:54:51 PM PST 24 29485353 ps
T37 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1022973620 Feb 07 12:54:55 PM PST 24 Feb 07 12:55:02 PM PST 24 29049847 ps
T8 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2288112304 Feb 07 12:54:45 PM PST 24 Feb 07 12:54:50 PM PST 24 29727146 ps
T38 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.433870524 Feb 07 12:54:43 PM PST 24 Feb 07 12:54:49 PM PST 24 29573226 ps
T4 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2470443764 Feb 07 12:54:48 PM PST 24 Feb 07 12:54:57 PM PST 24 29692997 ps
T39 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3974452913 Feb 07 12:54:42 PM PST 24 Feb 07 12:54:48 PM PST 24 29310098 ps
T40 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3581004921 Feb 07 12:54:47 PM PST 24 Feb 07 12:54:52 PM PST 24 29397780 ps
T41 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2909269117 Feb 07 12:54:33 PM PST 24 Feb 07 12:54:43 PM PST 24 29304236 ps
T46 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.55882742 Feb 07 12:54:44 PM PST 24 Feb 07 12:54:49 PM PST 24 30355263 ps
T47 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2008034796 Feb 07 12:54:44 PM PST 24 Feb 07 12:54:50 PM PST 24 31277712 ps
T48 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3111156867 Feb 07 12:54:47 PM PST 24 Feb 07 12:54:52 PM PST 24 29136393 ps
T49 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3706380820 Feb 07 12:54:46 PM PST 24 Feb 07 12:54:51 PM PST 24 29981109 ps
T50 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3670266847 Feb 07 12:54:42 PM PST 24 Feb 07 12:54:48 PM PST 24 30122349 ps
T51 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2922099886 Feb 07 12:54:36 PM PST 24 Feb 07 12:54:45 PM PST 24 29703622 ps
T15 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2416083645 Feb 07 12:54:43 PM PST 24 Feb 07 12:54:49 PM PST 24 31097309 ps
T52 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3209578958 Feb 07 12:54:51 PM PST 24 Feb 07 12:54:59 PM PST 24 31118923 ps
T53 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3729914224 Feb 07 12:54:35 PM PST 24 Feb 07 12:54:44 PM PST 24 30158578 ps
T54 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4028945357 Feb 07 12:54:55 PM PST 24 Feb 07 12:55:03 PM PST 24 30163980 ps
T11 /workspace/coverage/sync_alert/10.prim_sync_alert.2307571272 Feb 07 12:56:02 PM PST 24 Feb 07 12:56:04 PM PST 24 8747433 ps
T25 /workspace/coverage/sync_alert/1.prim_sync_alert.3363058102 Feb 07 12:56:02 PM PST 24 Feb 07 12:56:04 PM PST 24 8780996 ps
T26 /workspace/coverage/sync_alert/5.prim_sync_alert.3040463082 Feb 07 12:55:58 PM PST 24 Feb 07 12:55:59 PM PST 24 9243885 ps
T27 /workspace/coverage/sync_alert/2.prim_sync_alert.1799205447 Feb 07 12:55:48 PM PST 24 Feb 07 12:55:49 PM PST 24 9518102 ps
T28 /workspace/coverage/sync_alert/7.prim_sync_alert.3656109235 Feb 07 12:55:53 PM PST 24 Feb 07 12:55:54 PM PST 24 9404581 ps
T29 /workspace/coverage/sync_alert/11.prim_sync_alert.875297877 Feb 07 12:56:03 PM PST 24 Feb 07 12:56:04 PM PST 24 9583412 ps
T30 /workspace/coverage/sync_alert/0.prim_sync_alert.3487962860 Feb 07 12:55:58 PM PST 24 Feb 07 12:55:59 PM PST 24 9866964 ps
T31 /workspace/coverage/sync_alert/14.prim_sync_alert.2274698996 Feb 07 12:55:47 PM PST 24 Feb 07 12:55:48 PM PST 24 10790757 ps
T32 /workspace/coverage/sync_alert/9.prim_sync_alert.1144568871 Feb 07 12:55:48 PM PST 24 Feb 07 12:55:49 PM PST 24 9229385 ps
T33 /workspace/coverage/sync_alert/17.prim_sync_alert.572804369 Feb 07 12:55:58 PM PST 24 Feb 07 12:55:59 PM PST 24 7580512 ps
T34 /workspace/coverage/sync_alert/16.prim_sync_alert.1118722919 Feb 07 12:56:00 PM PST 24 Feb 07 12:56:02 PM PST 24 9085915 ps
T12 /workspace/coverage/sync_alert/6.prim_sync_alert.3510005554 Feb 07 12:55:57 PM PST 24 Feb 07 12:55:58 PM PST 24 9454401 ps
T35 /workspace/coverage/sync_alert/19.prim_sync_alert.3577219687 Feb 07 12:55:52 PM PST 24 Feb 07 12:55:53 PM PST 24 8328267 ps
T55 /workspace/coverage/sync_alert/3.prim_sync_alert.4103038100 Feb 07 12:56:02 PM PST 24 Feb 07 12:56:04 PM PST 24 9894462 ps
T56 /workspace/coverage/sync_alert/13.prim_sync_alert.3917121304 Feb 07 12:55:59 PM PST 24 Feb 07 12:56:00 PM PST 24 9031708 ps
T57 /workspace/coverage/sync_alert/15.prim_sync_alert.2602705353 Feb 07 12:55:45 PM PST 24 Feb 07 12:55:46 PM PST 24 8496245 ps
T58 /workspace/coverage/sync_alert/8.prim_sync_alert.2630861393 Feb 07 12:56:13 PM PST 24 Feb 07 12:56:14 PM PST 24 8700762 ps
T59 /workspace/coverage/sync_alert/18.prim_sync_alert.817663024 Feb 07 12:55:46 PM PST 24 Feb 07 12:55:47 PM PST 24 8567197 ps
T60 /workspace/coverage/sync_alert/4.prim_sync_alert.2431057006 Feb 07 12:55:46 PM PST 24 Feb 07 12:55:47 PM PST 24 8975015 ps
T61 /workspace/coverage/sync_alert/12.prim_sync_alert.970245206 Feb 07 12:55:45 PM PST 24 Feb 07 12:55:47 PM PST 24 9044315 ps
T62 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4063477764 Feb 07 12:23:22 PM PST 24 Feb 07 12:23:23 PM PST 24 30398065 ps
T5 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.361289974 Feb 07 12:21:50 PM PST 24 Feb 07 12:21:51 PM PST 24 26599745 ps
T63 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1563592026 Feb 07 12:20:56 PM PST 24 Feb 07 12:20:58 PM PST 24 27936994 ps
T64 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2838078535 Feb 07 12:25:32 PM PST 24 Feb 07 12:25:34 PM PST 24 26977972 ps
T65 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1019135394 Feb 07 12:20:23 PM PST 24 Feb 07 12:20:25 PM PST 24 28624819 ps
T66 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2220031814 Feb 07 12:20:28 PM PST 24 Feb 07 12:20:29 PM PST 24 27091488 ps
T67 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1746086654 Feb 07 12:26:17 PM PST 24 Feb 07 12:26:18 PM PST 24 25352288 ps
T68 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1609511534 Feb 07 12:24:53 PM PST 24 Feb 07 12:24:56 PM PST 24 28921739 ps
T69 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.326586076 Feb 07 12:24:53 PM PST 24 Feb 07 12:24:56 PM PST 24 27857554 ps
T70 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2467393256 Feb 07 12:24:17 PM PST 24 Feb 07 12:24:20 PM PST 24 26376982 ps
T71 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.287033682 Feb 07 12:24:18 PM PST 24 Feb 07 12:24:20 PM PST 24 26613657 ps
T72 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3657063524 Feb 07 12:25:45 PM PST 24 Feb 07 12:25:47 PM PST 24 26830434 ps
T73 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1745859536 Feb 07 12:20:56 PM PST 24 Feb 07 12:20:58 PM PST 24 29718502 ps
T74 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.768944313 Feb 07 12:20:56 PM PST 24 Feb 07 12:20:58 PM PST 24 28814369 ps
T75 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.860374159 Feb 07 12:26:00 PM PST 24 Feb 07 12:26:03 PM PST 24 27423443 ps
T76 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2723530168 Feb 07 12:25:59 PM PST 24 Feb 07 12:26:02 PM PST 24 27508371 ps
T77 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.148963154 Feb 07 12:20:31 PM PST 24 Feb 07 12:20:32 PM PST 24 28328070 ps
T78 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1043104240 Feb 07 12:24:17 PM PST 24 Feb 07 12:24:20 PM PST 24 27539857 ps
T79 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4139454907 Feb 07 12:21:50 PM PST 24 Feb 07 12:21:51 PM PST 24 27445388 ps
T80 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2269363293 Feb 07 12:24:20 PM PST 24 Feb 07 12:24:21 PM PST 24 29200191 ps

Test location /workspace/coverage/default/2.prim_async_alert.617712381
Short name T10
Test name
Test status
Simulation time 11695631 ps
CPU time 0.42 seconds
Started Feb 07 12:21:20 PM PST 24
Finished Feb 07 12:21:21 PM PST 24
Peak memory 145456 kb
Host smart-e6ba5ccf-0983-464f-842a-bb32f7c48ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617712381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.617712381
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3487962860
Short name T30
Test name
Test status
Simulation time 9866964 ps
CPU time 0.37 seconds
Started Feb 07 12:55:58 PM PST 24
Finished Feb 07 12:55:59 PM PST 24
Peak memory 144996 kb
Host smart-c8693afa-a209-486e-bd87-27709f67dc37
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3487962860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3487962860
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2288112304
Short name T8
Test name
Test status
Simulation time 29727146 ps
CPU time 0.4 seconds
Started Feb 07 12:54:45 PM PST 24
Finished Feb 07 12:54:50 PM PST 24
Peak memory 145676 kb
Host smart-c5cdaf7f-e67c-4dc3-861e-b0b68dfc3a84
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2288112304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2288112304
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.54816433
Short name T14
Test name
Test status
Simulation time 11648894 ps
CPU time 0.38 seconds
Started Feb 07 12:24:18 PM PST 24
Finished Feb 07 12:24:20 PM PST 24
Peak memory 145372 kb
Host smart-f08b286f-8ff8-4a6c-89d4-11bcbd8fd671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54816433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.54816433
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2470443764
Short name T4
Test name
Test status
Simulation time 29692997 ps
CPU time 0.42 seconds
Started Feb 07 12:54:48 PM PST 24
Finished Feb 07 12:54:57 PM PST 24
Peak memory 145632 kb
Host smart-1f40b77b-b4e9-43fa-9bcb-3aab0d1b171a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2470443764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2470443764
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2307571272
Short name T11
Test name
Test status
Simulation time 8747433 ps
CPU time 0.4 seconds
Started Feb 07 12:56:02 PM PST 24
Finished Feb 07 12:56:04 PM PST 24
Peak memory 145044 kb
Host smart-4ac70c40-82b1-4488-867b-0ddf533c7649
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2307571272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2307571272
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.4050410487
Short name T22
Test name
Test status
Simulation time 10472976 ps
CPU time 0.48 seconds
Started Feb 07 12:20:19 PM PST 24
Finished Feb 07 12:20:21 PM PST 24
Peak memory 146072 kb
Host smart-fda75fd8-24d2-4249-b1a9-02a40ee80213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050410487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.4050410487
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.234682314
Short name T16
Test name
Test status
Simulation time 11333791 ps
CPU time 0.48 seconds
Started Feb 07 12:20:11 PM PST 24
Finished Feb 07 12:20:13 PM PST 24
Peak memory 146108 kb
Host smart-0eb9cd4c-8e7d-48fd-9a2b-0432c9a95903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234682314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.234682314
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.485844449
Short name T9
Test name
Test status
Simulation time 12143501 ps
CPU time 0.41 seconds
Started Feb 07 12:25:21 PM PST 24
Finished Feb 07 12:25:25 PM PST 24
Peak memory 145392 kb
Host smart-04247cb2-198b-4d02-a891-253c21838a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485844449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.485844449
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.687695481
Short name T45
Test name
Test status
Simulation time 11066501 ps
CPU time 0.38 seconds
Started Feb 07 12:25:22 PM PST 24
Finished Feb 07 12:25:25 PM PST 24
Peak memory 145372 kb
Host smart-6e91b8d0-52b1-41ec-8a12-586c8a9322e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687695481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.687695481
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3099574225
Short name T2
Test name
Test status
Simulation time 11459322 ps
CPU time 0.43 seconds
Started Feb 07 12:24:22 PM PST 24
Finished Feb 07 12:24:23 PM PST 24
Peak memory 143972 kb
Host smart-1280b697-ba69-495b-bfb2-46b551d5dc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099574225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3099574225
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.1792058387
Short name T7
Test name
Test status
Simulation time 11231483 ps
CPU time 0.37 seconds
Started Feb 07 12:24:18 PM PST 24
Finished Feb 07 12:24:20 PM PST 24
Peak memory 146328 kb
Host smart-badb9ed6-0d24-4932-83e4-6c41ce7be2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792058387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.1792058387
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.696621237
Short name T44
Test name
Test status
Simulation time 11609870 ps
CPU time 0.43 seconds
Started Feb 07 12:24:22 PM PST 24
Finished Feb 07 12:24:23 PM PST 24
Peak memory 143700 kb
Host smart-c5d0491f-1352-4935-a716-fd7905e9c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696621237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.696621237
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3225020501
Short name T3
Test name
Test status
Simulation time 11493736 ps
CPU time 0.38 seconds
Started Feb 07 12:25:41 PM PST 24
Finished Feb 07 12:25:42 PM PST 24
Peak memory 145640 kb
Host smart-c4f14041-a70d-4dce-95fb-c64c4d62f298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225020501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3225020501
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.4063105740
Short name T17
Test name
Test status
Simulation time 11715587 ps
CPU time 0.51 seconds
Started Feb 07 12:20:23 PM PST 24
Finished Feb 07 12:20:25 PM PST 24
Peak memory 145512 kb
Host smart-0e4e4659-547f-4b74-862d-5e11916650c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063105740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4063105740
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1096894213
Short name T19
Test name
Test status
Simulation time 11129260 ps
CPU time 0.38 seconds
Started Feb 07 12:26:00 PM PST 24
Finished Feb 07 12:26:03 PM PST 24
Peak memory 145216 kb
Host smart-676b569f-6d4f-43c9-87e4-93598f925b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096894213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1096894213
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1197679464
Short name T6
Test name
Test status
Simulation time 11108494 ps
CPU time 0.38 seconds
Started Feb 07 12:24:19 PM PST 24
Finished Feb 07 12:24:20 PM PST 24
Peak memory 145224 kb
Host smart-3a60912d-f0e9-459d-a0a6-099b3370fbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197679464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1197679464
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.551370726
Short name T18
Test name
Test status
Simulation time 11133280 ps
CPU time 0.46 seconds
Started Feb 07 12:20:20 PM PST 24
Finished Feb 07 12:20:21 PM PST 24
Peak memory 145636 kb
Host smart-f75fe85b-6958-404e-a1d3-87f835499262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551370726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.551370726
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.2866198064
Short name T1
Test name
Test status
Simulation time 11580292 ps
CPU time 0.42 seconds
Started Feb 07 12:25:01 PM PST 24
Finished Feb 07 12:25:03 PM PST 24
Peak memory 146048 kb
Host smart-5b3401f3-f48c-4d63-b753-212aa402c62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866198064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.2866198064
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.2497195562
Short name T20
Test name
Test status
Simulation time 11549599 ps
CPU time 0.37 seconds
Started Feb 07 12:25:40 PM PST 24
Finished Feb 07 12:25:42 PM PST 24
Peak memory 145608 kb
Host smart-7282ee0c-8059-4c94-b935-4bf7ba14078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497195562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.2497195562
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.272319677
Short name T43
Test name
Test status
Simulation time 11103102 ps
CPU time 0.48 seconds
Started Feb 07 12:20:23 PM PST 24
Finished Feb 07 12:20:24 PM PST 24
Peak memory 145544 kb
Host smart-4b9b32a2-a552-41c3-9633-bba4c35e637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272319677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.272319677
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3332531555
Short name T13
Test name
Test status
Simulation time 12018395 ps
CPU time 0.43 seconds
Started Feb 07 12:24:22 PM PST 24
Finished Feb 07 12:24:23 PM PST 24
Peak memory 144460 kb
Host smart-4ea9243d-b2ea-4f94-968f-3d583da73116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332531555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3332531555
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.355731299
Short name T21
Test name
Test status
Simulation time 12005443 ps
CPU time 0.39 seconds
Started Feb 07 12:20:30 PM PST 24
Finished Feb 07 12:20:31 PM PST 24
Peak memory 145632 kb
Host smart-97b13dd9-d436-4c6d-9a20-e989bfdd49ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355731299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.355731299
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3520259207
Short name T42
Test name
Test status
Simulation time 10759824 ps
CPU time 0.42 seconds
Started Feb 07 12:24:22 PM PST 24
Finished Feb 07 12:24:23 PM PST 24
Peak memory 143948 kb
Host smart-e6047168-42c4-405c-8ac4-482e3e2b1f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520259207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3520259207
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3974452913
Short name T39
Test name
Test status
Simulation time 29310098 ps
CPU time 0.4 seconds
Started Feb 07 12:54:42 PM PST 24
Finished Feb 07 12:54:48 PM PST 24
Peak memory 145712 kb
Host smart-18f8504e-9ff9-4c7a-b4f3-ad1b8b9b22e6
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3974452913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3974452913
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.3209578958
Short name T52
Test name
Test status
Simulation time 31118923 ps
CPU time 0.4 seconds
Started Feb 07 12:54:51 PM PST 24
Finished Feb 07 12:54:59 PM PST 24
Peak memory 145652 kb
Host smart-13ae0f46-ecfa-47ea-b70f-aa44df69b263
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3209578958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.3209578958
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.31423359
Short name T36
Test name
Test status
Simulation time 29485353 ps
CPU time 0.4 seconds
Started Feb 07 12:54:46 PM PST 24
Finished Feb 07 12:54:51 PM PST 24
Peak memory 145676 kb
Host smart-c2f91d88-e68f-487b-9843-d7c5d9a2e34b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=31423359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.31423359
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2416083645
Short name T15
Test name
Test status
Simulation time 31097309 ps
CPU time 0.41 seconds
Started Feb 07 12:54:43 PM PST 24
Finished Feb 07 12:54:49 PM PST 24
Peak memory 145632 kb
Host smart-1975d640-0b5b-4e1e-ba51-2284de65a63f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2416083645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2416083645
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.433870524
Short name T38
Test name
Test status
Simulation time 29573226 ps
CPU time 0.41 seconds
Started Feb 07 12:54:43 PM PST 24
Finished Feb 07 12:54:49 PM PST 24
Peak memory 145652 kb
Host smart-69ff4b4a-299f-443b-8d61-bb5679c61e40
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=433870524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.433870524
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.3706380820
Short name T49
Test name
Test status
Simulation time 29981109 ps
CPU time 0.39 seconds
Started Feb 07 12:54:46 PM PST 24
Finished Feb 07 12:54:51 PM PST 24
Peak memory 145372 kb
Host smart-f3106e52-32d6-41c5-9780-8712889278c0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3706380820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.3706380820
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2254847079
Short name T23
Test name
Test status
Simulation time 28151577 ps
CPU time 0.39 seconds
Started Feb 07 12:54:46 PM PST 24
Finished Feb 07 12:54:51 PM PST 24
Peak memory 145364 kb
Host smart-a249aa65-7697-4730-9177-ee7df1813ea0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2254847079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2254847079
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.1022973620
Short name T37
Test name
Test status
Simulation time 29049847 ps
CPU time 0.4 seconds
Started Feb 07 12:54:55 PM PST 24
Finished Feb 07 12:55:02 PM PST 24
Peak memory 145612 kb
Host smart-2bec1825-1aec-454c-b159-2b96bf35dfed
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1022973620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.1022973620
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2909269117
Short name T41
Test name
Test status
Simulation time 29304236 ps
CPU time 0.41 seconds
Started Feb 07 12:54:33 PM PST 24
Finished Feb 07 12:54:43 PM PST 24
Peak memory 145536 kb
Host smart-fbc48b4b-f868-4f88-bb67-57c386061c37
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2909269117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2909269117
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.4028945357
Short name T54
Test name
Test status
Simulation time 30163980 ps
CPU time 0.39 seconds
Started Feb 07 12:54:55 PM PST 24
Finished Feb 07 12:55:03 PM PST 24
Peak memory 145612 kb
Host smart-860c32dd-197b-4699-86ff-d4fd01d48c73
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4028945357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.4028945357
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2922099886
Short name T51
Test name
Test status
Simulation time 29703622 ps
CPU time 0.45 seconds
Started Feb 07 12:54:36 PM PST 24
Finished Feb 07 12:54:45 PM PST 24
Peak memory 145608 kb
Host smart-3aa22acf-0d4a-4ea9-9e8e-c624e5cc7539
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2922099886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2922099886
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2008034796
Short name T47
Test name
Test status
Simulation time 31277712 ps
CPU time 0.4 seconds
Started Feb 07 12:54:44 PM PST 24
Finished Feb 07 12:54:50 PM PST 24
Peak memory 145760 kb
Host smart-46db9a8c-1499-411f-9d11-7e6767ac78a2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2008034796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2008034796
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3670266847
Short name T50
Test name
Test status
Simulation time 30122349 ps
CPU time 0.4 seconds
Started Feb 07 12:54:42 PM PST 24
Finished Feb 07 12:54:48 PM PST 24
Peak memory 145704 kb
Host smart-ec4cb0ed-ab24-4602-9736-7f34b3a56e22
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3670266847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3670266847
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.55882742
Short name T46
Test name
Test status
Simulation time 30355263 ps
CPU time 0.39 seconds
Started Feb 07 12:54:44 PM PST 24
Finished Feb 07 12:54:49 PM PST 24
Peak memory 145592 kb
Host smart-8b2d4306-f25a-4024-a566-19f479cc963a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=55882742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.55882742
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.3111156867
Short name T48
Test name
Test status
Simulation time 29136393 ps
CPU time 0.41 seconds
Started Feb 07 12:54:47 PM PST 24
Finished Feb 07 12:54:52 PM PST 24
Peak memory 145668 kb
Host smart-2e64b027-99aa-4cb2-8756-a5781ba68323
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3111156867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.3111156867
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.834252530
Short name T24
Test name
Test status
Simulation time 29929101 ps
CPU time 0.4 seconds
Started Feb 07 12:54:51 PM PST 24
Finished Feb 07 12:55:00 PM PST 24
Peak memory 145572 kb
Host smart-e173cd5e-2a1c-41e5-a016-9795647a252d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=834252530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.834252530
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3581004921
Short name T40
Test name
Test status
Simulation time 29397780 ps
CPU time 0.4 seconds
Started Feb 07 12:54:47 PM PST 24
Finished Feb 07 12:54:52 PM PST 24
Peak memory 145656 kb
Host smart-13c008ee-5113-44b5-92a8-637c5b03d5d8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3581004921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3581004921
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3729914224
Short name T53
Test name
Test status
Simulation time 30158578 ps
CPU time 0.41 seconds
Started Feb 07 12:54:35 PM PST 24
Finished Feb 07 12:54:44 PM PST 24
Peak memory 145724 kb
Host smart-8890e198-e078-4cd8-80b5-f1d518526205
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3729914224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3729914224
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3363058102
Short name T25
Test name
Test status
Simulation time 8780996 ps
CPU time 0.38 seconds
Started Feb 07 12:56:02 PM PST 24
Finished Feb 07 12:56:04 PM PST 24
Peak memory 144976 kb
Host smart-3493cba5-47b0-47b3-8b10-d48d079dd6ed
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3363058102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3363058102
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.875297877
Short name T29
Test name
Test status
Simulation time 9583412 ps
CPU time 0.41 seconds
Started Feb 07 12:56:03 PM PST 24
Finished Feb 07 12:56:04 PM PST 24
Peak memory 145084 kb
Host smart-763e847a-d472-4a50-b321-ff4b68ac41b9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=875297877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.875297877
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.970245206
Short name T61
Test name
Test status
Simulation time 9044315 ps
CPU time 0.38 seconds
Started Feb 07 12:55:45 PM PST 24
Finished Feb 07 12:55:47 PM PST 24
Peak memory 144980 kb
Host smart-eeffaf37-709a-4df3-9f99-577e489352b0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=970245206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.970245206
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3917121304
Short name T56
Test name
Test status
Simulation time 9031708 ps
CPU time 0.37 seconds
Started Feb 07 12:55:59 PM PST 24
Finished Feb 07 12:56:00 PM PST 24
Peak memory 145044 kb
Host smart-6233f5e7-7d1d-4f87-8556-dab7825f0145
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3917121304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3917121304
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2274698996
Short name T31
Test name
Test status
Simulation time 10790757 ps
CPU time 0.4 seconds
Started Feb 07 12:55:47 PM PST 24
Finished Feb 07 12:55:48 PM PST 24
Peak memory 145052 kb
Host smart-09115263-d99b-4bde-a8f5-9b0095bc8669
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2274698996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2274698996
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2602705353
Short name T57
Test name
Test status
Simulation time 8496245 ps
CPU time 0.4 seconds
Started Feb 07 12:55:45 PM PST 24
Finished Feb 07 12:55:46 PM PST 24
Peak memory 144868 kb
Host smart-2f130349-70c5-4680-906d-c9030d0d949e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2602705353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2602705353
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1118722919
Short name T34
Test name
Test status
Simulation time 9085915 ps
CPU time 0.38 seconds
Started Feb 07 12:56:00 PM PST 24
Finished Feb 07 12:56:02 PM PST 24
Peak memory 145080 kb
Host smart-f0dbdc60-7bd9-4265-b690-25f6b4766534
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1118722919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1118722919
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.572804369
Short name T33
Test name
Test status
Simulation time 7580512 ps
CPU time 0.43 seconds
Started Feb 07 12:55:58 PM PST 24
Finished Feb 07 12:55:59 PM PST 24
Peak memory 145040 kb
Host smart-0b5ee3f3-6169-4a3d-8f14-ae8255fab196
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=572804369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.572804369
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.817663024
Short name T59
Test name
Test status
Simulation time 8567197 ps
CPU time 0.43 seconds
Started Feb 07 12:55:46 PM PST 24
Finished Feb 07 12:55:47 PM PST 24
Peak memory 144952 kb
Host smart-e10aa281-a63a-4dff-8adf-876beb3b1f55
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=817663024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.817663024
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.3577219687
Short name T35
Test name
Test status
Simulation time 8328267 ps
CPU time 0.39 seconds
Started Feb 07 12:55:52 PM PST 24
Finished Feb 07 12:55:53 PM PST 24
Peak memory 145000 kb
Host smart-686047c4-9103-4bae-addb-36376341c941
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3577219687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.3577219687
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1799205447
Short name T27
Test name
Test status
Simulation time 9518102 ps
CPU time 0.39 seconds
Started Feb 07 12:55:48 PM PST 24
Finished Feb 07 12:55:49 PM PST 24
Peak memory 145080 kb
Host smart-a46eff89-62a8-44bc-9d0e-2c33a32b8d83
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1799205447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1799205447
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.4103038100
Short name T55
Test name
Test status
Simulation time 9894462 ps
CPU time 0.4 seconds
Started Feb 07 12:56:02 PM PST 24
Finished Feb 07 12:56:04 PM PST 24
Peak memory 144964 kb
Host smart-d23092ae-de85-4b1d-9dfe-718e700da269
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4103038100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.4103038100
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.2431057006
Short name T60
Test name
Test status
Simulation time 8975015 ps
CPU time 0.38 seconds
Started Feb 07 12:55:46 PM PST 24
Finished Feb 07 12:55:47 PM PST 24
Peak memory 144968 kb
Host smart-d9f3c622-1355-4088-ad5d-97dab641d819
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2431057006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.2431057006
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.3040463082
Short name T26
Test name
Test status
Simulation time 9243885 ps
CPU time 0.38 seconds
Started Feb 07 12:55:58 PM PST 24
Finished Feb 07 12:55:59 PM PST 24
Peak memory 145024 kb
Host smart-7653a5fd-24ed-4912-9268-7010b9cb679d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3040463082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3040463082
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3510005554
Short name T12
Test name
Test status
Simulation time 9454401 ps
CPU time 0.39 seconds
Started Feb 07 12:55:57 PM PST 24
Finished Feb 07 12:55:58 PM PST 24
Peak memory 145008 kb
Host smart-363e9310-56f5-4655-b204-55a465266025
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3510005554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3510005554
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3656109235
Short name T28
Test name
Test status
Simulation time 9404581 ps
CPU time 0.39 seconds
Started Feb 07 12:55:53 PM PST 24
Finished Feb 07 12:55:54 PM PST 24
Peak memory 145000 kb
Host smart-4fd78541-f82e-4a1f-8b69-b01db6cb57f5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3656109235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3656109235
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2630861393
Short name T58
Test name
Test status
Simulation time 8700762 ps
CPU time 0.39 seconds
Started Feb 07 12:56:13 PM PST 24
Finished Feb 07 12:56:14 PM PST 24
Peak memory 144944 kb
Host smart-9112e092-2ff8-41c1-bba1-8c4e01f79bca
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2630861393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2630861393
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.1144568871
Short name T32
Test name
Test status
Simulation time 9229385 ps
CPU time 0.4 seconds
Started Feb 07 12:55:48 PM PST 24
Finished Feb 07 12:55:49 PM PST 24
Peak memory 145080 kb
Host smart-9aaa516b-3a56-42bf-b3cb-71a46e7f0fcf
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1144568871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1144568871
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.2269363293
Short name T80
Test name
Test status
Simulation time 29200191 ps
CPU time 0.4 seconds
Started Feb 07 12:24:20 PM PST 24
Finished Feb 07 12:24:21 PM PST 24
Peak memory 144916 kb
Host smart-3e2bfbe8-c298-4f9b-9f50-2105701ce0f5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2269363293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.2269363293
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.2467393256
Short name T70
Test name
Test status
Simulation time 26376982 ps
CPU time 0.42 seconds
Started Feb 07 12:24:17 PM PST 24
Finished Feb 07 12:24:20 PM PST 24
Peak memory 144908 kb
Host smart-973fec9e-1982-4ae0-961c-9e9617eb9dd7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2467393256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2467393256
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4139454907
Short name T79
Test name
Test status
Simulation time 27445388 ps
CPU time 0.43 seconds
Started Feb 07 12:21:50 PM PST 24
Finished Feb 07 12:21:51 PM PST 24
Peak memory 144956 kb
Host smart-2655565b-8edd-4472-a534-a399de7013b4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4139454907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4139454907
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.768944313
Short name T74
Test name
Test status
Simulation time 28814369 ps
CPU time 0.42 seconds
Started Feb 07 12:20:56 PM PST 24
Finished Feb 07 12:20:58 PM PST 24
Peak memory 144788 kb
Host smart-5c4f3d4e-de5c-4656-b10f-be19a35ffc72
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=768944313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.768944313
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.4063477764
Short name T62
Test name
Test status
Simulation time 30398065 ps
CPU time 0.4 seconds
Started Feb 07 12:23:22 PM PST 24
Finished Feb 07 12:23:23 PM PST 24
Peak memory 144700 kb
Host smart-47e1a980-1021-428e-bd29-50295aaa3afa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4063477764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.4063477764
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3657063524
Short name T72
Test name
Test status
Simulation time 26830434 ps
CPU time 0.36 seconds
Started Feb 07 12:25:45 PM PST 24
Finished Feb 07 12:25:47 PM PST 24
Peak memory 144804 kb
Host smart-f52b86c2-3f5b-46fd-9e8d-91269453c447
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3657063524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3657063524
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.148963154
Short name T77
Test name
Test status
Simulation time 28328070 ps
CPU time 0.41 seconds
Started Feb 07 12:20:31 PM PST 24
Finished Feb 07 12:20:32 PM PST 24
Peak memory 144892 kb
Host smart-08c81043-6d5e-4615-bc35-b86eaccf73c9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=148963154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.148963154
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.361289974
Short name T5
Test name
Test status
Simulation time 26599745 ps
CPU time 0.41 seconds
Started Feb 07 12:21:50 PM PST 24
Finished Feb 07 12:21:51 PM PST 24
Peak memory 144900 kb
Host smart-181211c1-1cd8-4d88-9cf3-b9844ceee455
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=361289974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.361289974
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1563592026
Short name T63
Test name
Test status
Simulation time 27936994 ps
CPU time 0.42 seconds
Started Feb 07 12:20:56 PM PST 24
Finished Feb 07 12:20:58 PM PST 24
Peak memory 144816 kb
Host smart-052c68ab-88b0-4218-89c0-0861054e7736
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1563592026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1563592026
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1609511534
Short name T68
Test name
Test status
Simulation time 28921739 ps
CPU time 0.4 seconds
Started Feb 07 12:24:53 PM PST 24
Finished Feb 07 12:24:56 PM PST 24
Peak memory 144644 kb
Host smart-9ad64959-c566-4592-a7e5-39d312df78e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1609511534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1609511534
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.326586076
Short name T69
Test name
Test status
Simulation time 27857554 ps
CPU time 0.39 seconds
Started Feb 07 12:24:53 PM PST 24
Finished Feb 07 12:24:56 PM PST 24
Peak memory 144644 kb
Host smart-58272575-9569-4d1d-8375-31db3e5ceed1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=326586076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.326586076
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2838078535
Short name T64
Test name
Test status
Simulation time 26977972 ps
CPU time 0.4 seconds
Started Feb 07 12:25:32 PM PST 24
Finished Feb 07 12:25:34 PM PST 24
Peak memory 144684 kb
Host smart-8de5bd3c-b69b-4ce3-8efc-9a28339d3f97
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2838078535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2838078535
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.287033682
Short name T71
Test name
Test status
Simulation time 26613657 ps
CPU time 0.39 seconds
Started Feb 07 12:24:18 PM PST 24
Finished Feb 07 12:24:20 PM PST 24
Peak memory 144612 kb
Host smart-d585c0de-0d8d-402d-b9b6-ec417790fe6f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=287033682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.287033682
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.1746086654
Short name T67
Test name
Test status
Simulation time 25352288 ps
CPU time 0.4 seconds
Started Feb 07 12:26:17 PM PST 24
Finished Feb 07 12:26:18 PM PST 24
Peak memory 144888 kb
Host smart-f306d7e5-58e0-47d8-92cf-3b92687b4514
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1746086654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.1746086654
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.1043104240
Short name T78
Test name
Test status
Simulation time 27539857 ps
CPU time 0.45 seconds
Started Feb 07 12:24:17 PM PST 24
Finished Feb 07 12:24:20 PM PST 24
Peak memory 144852 kb
Host smart-a510f28f-4355-4030-9897-3c2a28551429
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1043104240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.1043104240
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2723530168
Short name T76
Test name
Test status
Simulation time 27508371 ps
CPU time 0.44 seconds
Started Feb 07 12:25:59 PM PST 24
Finished Feb 07 12:26:02 PM PST 24
Peak memory 144696 kb
Host smart-f865be3a-e985-443e-94fe-51f070cd8e87
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2723530168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2723530168
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1019135394
Short name T65
Test name
Test status
Simulation time 28624819 ps
CPU time 0.51 seconds
Started Feb 07 12:20:23 PM PST 24
Finished Feb 07 12:20:25 PM PST 24
Peak memory 145092 kb
Host smart-941d1666-fae5-4bd5-b737-f4f57a01e540
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1019135394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1019135394
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2220031814
Short name T66
Test name
Test status
Simulation time 27091488 ps
CPU time 0.52 seconds
Started Feb 07 12:20:28 PM PST 24
Finished Feb 07 12:20:29 PM PST 24
Peak memory 144736 kb
Host smart-40123df6-fc6b-4f6a-ad09-043df280730a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2220031814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2220031814
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.860374159
Short name T75
Test name
Test status
Simulation time 27423443 ps
CPU time 0.38 seconds
Started Feb 07 12:26:00 PM PST 24
Finished Feb 07 12:26:03 PM PST 24
Peak memory 144552 kb
Host smart-39389df9-17fe-4234-9827-7e4edd715c31
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=860374159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.860374159
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.1745859536
Short name T73
Test name
Test status
Simulation time 29718502 ps
CPU time 0.41 seconds
Started Feb 07 12:20:56 PM PST 24
Finished Feb 07 12:20:58 PM PST 24
Peak memory 144780 kb
Host smart-5627b2b8-7c8d-459a-91b6-e890a96556fc
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1745859536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.1745859536
Directory /workspace/9.prim_sync_fatal_alert/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%