Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 100.00 97.92 100.00 89.29 95.83 86.05


Total tests in report: 80
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.28 88.28 100.00 100.00 93.75 93.75 96.43 96.43 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/10.prim_async_alert.3187481459
91.37 3.09 100.00 0.00 95.83 2.08 100.00 3.57 82.14 3.57 95.83 0.00 74.42 9.30 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2770753701
93.90 2.53 100.00 0.00 95.83 0.00 100.00 0.00 85.71 3.57 95.83 0.00 86.05 11.63 /workspace/coverage/sync_alert/1.prim_sync_alert.3371469312
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/0.prim_sync_alert.1866646833
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3512903622

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3441198211
/workspace/coverage/default/1.prim_async_alert.713535712
/workspace/coverage/default/11.prim_async_alert.1366702345
/workspace/coverage/default/12.prim_async_alert.1661371805
/workspace/coverage/default/13.prim_async_alert.1354131803
/workspace/coverage/default/14.prim_async_alert.2370052929
/workspace/coverage/default/15.prim_async_alert.4000141009
/workspace/coverage/default/16.prim_async_alert.2789784320
/workspace/coverage/default/17.prim_async_alert.1920010760
/workspace/coverage/default/18.prim_async_alert.4219363291
/workspace/coverage/default/19.prim_async_alert.3495142267
/workspace/coverage/default/2.prim_async_alert.3089392247
/workspace/coverage/default/3.prim_async_alert.3298452858
/workspace/coverage/default/4.prim_async_alert.3032804877
/workspace/coverage/default/5.prim_async_alert.3124457912
/workspace/coverage/default/6.prim_async_alert.3159878290
/workspace/coverage/default/7.prim_async_alert.1643656913
/workspace/coverage/default/8.prim_async_alert.642002600
/workspace/coverage/default/9.prim_async_alert.1793866366
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3809192577
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.626781548
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1882790417
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.723632600
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2616013810
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1602701445
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2018809986
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.855303441
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.367299426
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.639320685
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4071287457
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.643212868
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3981612975
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2064919211
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2913765650
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2273457640
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2367069876
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2414635458
/workspace/coverage/sync_alert/10.prim_sync_alert.666311381
/workspace/coverage/sync_alert/11.prim_sync_alert.1664001122
/workspace/coverage/sync_alert/12.prim_sync_alert.2047643570
/workspace/coverage/sync_alert/13.prim_sync_alert.3425991039
/workspace/coverage/sync_alert/14.prim_sync_alert.4012232620
/workspace/coverage/sync_alert/15.prim_sync_alert.231707309
/workspace/coverage/sync_alert/16.prim_sync_alert.3233092048
/workspace/coverage/sync_alert/17.prim_sync_alert.1001584940
/workspace/coverage/sync_alert/18.prim_sync_alert.1718157937
/workspace/coverage/sync_alert/19.prim_sync_alert.1261895963
/workspace/coverage/sync_alert/2.prim_sync_alert.1089549967
/workspace/coverage/sync_alert/3.prim_sync_alert.2439585352
/workspace/coverage/sync_alert/4.prim_sync_alert.1836933513
/workspace/coverage/sync_alert/5.prim_sync_alert.64525073
/workspace/coverage/sync_alert/6.prim_sync_alert.2060353278
/workspace/coverage/sync_alert/7.prim_sync_alert.859410763
/workspace/coverage/sync_alert/8.prim_sync_alert.375082531
/workspace/coverage/sync_alert/9.prim_sync_alert.2485780101
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.505366310
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.23489068
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2488780763
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1772318422
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2441768250
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1294773653
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2765980558
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.580747096
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1150663135
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1574388838
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3054907358
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2639581290
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3999991425
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2363949300
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3067473462
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.117128726
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1089755062
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1283195007
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.287455453
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2887682578



Total test records in report: 80
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/10.prim_async_alert.3187481459 Feb 18 12:27:50 PM PST 24 Feb 18 12:27:57 PM PST 24 11894374 ps
T2 /workspace/coverage/default/8.prim_async_alert.642002600 Feb 18 12:27:49 PM PST 24 Feb 18 12:27:51 PM PST 24 11071866 ps
T3 /workspace/coverage/default/11.prim_async_alert.1366702345 Feb 18 12:27:47 PM PST 24 Feb 18 12:27:49 PM PST 24 11100077 ps
T19 /workspace/coverage/default/13.prim_async_alert.1354131803 Feb 18 12:27:51 PM PST 24 Feb 18 12:27:58 PM PST 24 11611678 ps
T9 /workspace/coverage/default/15.prim_async_alert.4000141009 Feb 18 12:27:38 PM PST 24 Feb 18 12:27:39 PM PST 24 10790951 ps
T7 /workspace/coverage/default/17.prim_async_alert.1920010760 Feb 18 12:27:47 PM PST 24 Feb 18 12:27:49 PM PST 24 10507940 ps
T8 /workspace/coverage/default/19.prim_async_alert.3495142267 Feb 18 12:27:42 PM PST 24 Feb 18 12:27:43 PM PST 24 12398400 ps
T16 /workspace/coverage/default/14.prim_async_alert.2370052929 Feb 18 12:27:36 PM PST 24 Feb 18 12:27:37 PM PST 24 11517921 ps
T20 /workspace/coverage/default/16.prim_async_alert.2789784320 Feb 18 12:27:48 PM PST 24 Feb 18 12:27:50 PM PST 24 11566574 ps
T21 /workspace/coverage/default/1.prim_async_alert.713535712 Feb 18 12:27:39 PM PST 24 Feb 18 12:27:40 PM PST 24 11330401 ps
T26 /workspace/coverage/default/3.prim_async_alert.3298452858 Feb 18 12:27:44 PM PST 24 Feb 18 12:27:46 PM PST 24 10841059 ps
T51 /workspace/coverage/default/0.prim_async_alert.3441198211 Feb 18 12:28:00 PM PST 24 Feb 18 12:28:07 PM PST 24 10843202 ps
T52 /workspace/coverage/default/9.prim_async_alert.1793866366 Feb 18 12:27:54 PM PST 24 Feb 18 12:28:00 PM PST 24 10843232 ps
T22 /workspace/coverage/default/2.prim_async_alert.3089392247 Feb 18 12:27:48 PM PST 24 Feb 18 12:27:50 PM PST 24 11140708 ps
T23 /workspace/coverage/default/5.prim_async_alert.3124457912 Feb 18 12:27:48 PM PST 24 Feb 18 12:27:58 PM PST 24 10938741 ps
T10 /workspace/coverage/default/7.prim_async_alert.1643656913 Feb 18 12:27:55 PM PST 24 Feb 18 12:28:01 PM PST 24 11271235 ps
T53 /workspace/coverage/default/12.prim_async_alert.1661371805 Feb 18 12:27:48 PM PST 24 Feb 18 12:27:58 PM PST 24 10728072 ps
T11 /workspace/coverage/default/4.prim_async_alert.3032804877 Feb 18 12:27:42 PM PST 24 Feb 18 12:27:44 PM PST 24 12281415 ps
T24 /workspace/coverage/default/6.prim_async_alert.3159878290 Feb 18 12:27:51 PM PST 24 Feb 18 12:27:58 PM PST 24 12409669 ps
T25 /workspace/coverage/default/18.prim_async_alert.4219363291 Feb 18 12:27:55 PM PST 24 Feb 18 12:28:01 PM PST 24 11337662 ps
T12 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2770753701 Feb 18 12:27:49 PM PST 24 Feb 18 12:27:58 PM PST 24 30750845 ps
T4 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2414635458 Feb 18 12:27:41 PM PST 24 Feb 18 12:27:42 PM PST 24 29578743 ps
T17 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.639320685 Feb 18 12:27:43 PM PST 24 Feb 18 12:27:44 PM PST 24 30267277 ps
T46 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2367069876 Feb 18 12:27:50 PM PST 24 Feb 18 12:27:54 PM PST 24 30500872 ps
T47 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2616013810 Feb 18 12:27:49 PM PST 24 Feb 18 12:27:53 PM PST 24 29348428 ps
T48 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3981612975 Feb 18 12:27:49 PM PST 24 Feb 18 12:27:52 PM PST 24 28859515 ps
T14 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2913765650 Feb 18 12:27:57 PM PST 24 Feb 18 12:28:03 PM PST 24 28791524 ps
T49 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.723632600 Feb 18 12:27:42 PM PST 24 Feb 18 12:27:43 PM PST 24 31234192 ps
T50 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2273457640 Feb 18 12:27:45 PM PST 24 Feb 18 12:27:46 PM PST 24 30752048 ps
T45 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.643212868 Feb 18 12:27:45 PM PST 24 Feb 18 12:27:46 PM PST 24 30273815 ps
T54 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4071287457 Feb 18 12:27:49 PM PST 24 Feb 18 12:27:53 PM PST 24 29628582 ps
T55 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.855303441 Feb 18 12:27:45 PM PST 24 Feb 18 12:27:46 PM PST 24 28976811 ps
T56 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2064919211 Feb 18 12:27:56 PM PST 24 Feb 18 12:28:03 PM PST 24 29056358 ps
T57 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2018809986 Feb 18 12:27:48 PM PST 24 Feb 18 12:27:58 PM PST 24 28621834 ps
T13 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.626781548 Feb 18 12:27:50 PM PST 24 Feb 18 12:27:55 PM PST 24 29794816 ps
T18 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3809192577 Feb 18 12:27:49 PM PST 24 Feb 18 12:27:53 PM PST 24 31225723 ps
T15 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.367299426 Feb 18 12:27:56 PM PST 24 Feb 18 12:28:02 PM PST 24 29412878 ps
T58 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1602701445 Feb 18 12:27:56 PM PST 24 Feb 18 12:28:02 PM PST 24 30392402 ps
T5 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3512903622 Feb 18 12:27:39 PM PST 24 Feb 18 12:27:40 PM PST 24 30208150 ps
T59 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1882790417 Feb 18 12:27:55 PM PST 24 Feb 18 12:28:01 PM PST 24 30595160 ps
T36 /workspace/coverage/sync_alert/9.prim_sync_alert.2485780101 Feb 18 12:28:01 PM PST 24 Feb 18 12:28:13 PM PST 24 8201609 ps
T37 /workspace/coverage/sync_alert/4.prim_sync_alert.1836933513 Feb 18 12:27:58 PM PST 24 Feb 18 12:28:05 PM PST 24 9059077 ps
T27 /workspace/coverage/sync_alert/11.prim_sync_alert.1664001122 Feb 18 12:28:04 PM PST 24 Feb 18 12:28:09 PM PST 24 8850781 ps
T28 /workspace/coverage/sync_alert/10.prim_sync_alert.666311381 Feb 18 12:27:51 PM PST 24 Feb 18 12:27:58 PM PST 24 8704940 ps
T38 /workspace/coverage/sync_alert/8.prim_sync_alert.375082531 Feb 18 12:27:58 PM PST 24 Feb 18 12:28:05 PM PST 24 8579634 ps
T39 /workspace/coverage/sync_alert/2.prim_sync_alert.1089549967 Feb 18 12:27:50 PM PST 24 Feb 18 12:27:57 PM PST 24 9524822 ps
T40 /workspace/coverage/sync_alert/1.prim_sync_alert.3371469312 Feb 18 12:27:49 PM PST 24 Feb 18 12:27:51 PM PST 24 9106648 ps
T29 /workspace/coverage/sync_alert/16.prim_sync_alert.3233092048 Feb 18 12:28:00 PM PST 24 Feb 18 12:28:06 PM PST 24 8819973 ps
T41 /workspace/coverage/sync_alert/3.prim_sync_alert.2439585352 Feb 18 12:28:06 PM PST 24 Feb 18 12:28:12 PM PST 24 9576753 ps
T42 /workspace/coverage/sync_alert/13.prim_sync_alert.3425991039 Feb 18 12:27:47 PM PST 24 Feb 18 12:27:49 PM PST 24 8736978 ps
T30 /workspace/coverage/sync_alert/14.prim_sync_alert.4012232620 Feb 18 12:27:58 PM PST 24 Feb 18 12:28:05 PM PST 24 9173834 ps
T60 /workspace/coverage/sync_alert/17.prim_sync_alert.1001584940 Feb 18 12:28:16 PM PST 24 Feb 18 12:28:22 PM PST 24 9155626 ps
T61 /workspace/coverage/sync_alert/6.prim_sync_alert.2060353278 Feb 18 12:27:45 PM PST 24 Feb 18 12:27:47 PM PST 24 9358712 ps
T31 /workspace/coverage/sync_alert/19.prim_sync_alert.1261895963 Feb 18 12:28:05 PM PST 24 Feb 18 12:28:10 PM PST 24 10510954 ps
T62 /workspace/coverage/sync_alert/15.prim_sync_alert.231707309 Feb 18 12:28:05 PM PST 24 Feb 18 12:28:10 PM PST 24 9333193 ps
T43 /workspace/coverage/sync_alert/7.prim_sync_alert.859410763 Feb 18 12:27:45 PM PST 24 Feb 18 12:27:47 PM PST 24 10060953 ps
T44 /workspace/coverage/sync_alert/0.prim_sync_alert.1866646833 Feb 18 12:27:41 PM PST 24 Feb 18 12:27:43 PM PST 24 9965653 ps
T63 /workspace/coverage/sync_alert/18.prim_sync_alert.1718157937 Feb 18 12:28:07 PM PST 24 Feb 18 12:28:14 PM PST 24 10723767 ps
T64 /workspace/coverage/sync_alert/12.prim_sync_alert.2047643570 Feb 18 12:28:02 PM PST 24 Feb 18 12:28:08 PM PST 24 8848806 ps
T32 /workspace/coverage/sync_alert/5.prim_sync_alert.64525073 Feb 18 12:28:08 PM PST 24 Feb 18 12:28:16 PM PST 24 9710582 ps
T65 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.580747096 Feb 18 12:29:32 PM PST 24 Feb 18 12:29:34 PM PST 24 26086063 ps
T33 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1294773653 Feb 18 12:29:22 PM PST 24 Feb 18 12:29:24 PM PST 24 30613637 ps
T6 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1089755062 Feb 18 12:29:27 PM PST 24 Feb 18 12:29:29 PM PST 24 27362046 ps
T66 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2488780763 Feb 18 12:29:46 PM PST 24 Feb 18 12:29:49 PM PST 24 26134980 ps
T67 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3067473462 Feb 18 12:29:38 PM PST 24 Feb 18 12:29:40 PM PST 24 25544454 ps
T68 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.117128726 Feb 18 12:29:22 PM PST 24 Feb 18 12:29:24 PM PST 24 26764123 ps
T69 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2441768250 Feb 18 12:29:27 PM PST 24 Feb 18 12:29:28 PM PST 24 26588500 ps
T70 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.287455453 Feb 18 12:29:28 PM PST 24 Feb 18 12:29:30 PM PST 24 28647551 ps
T34 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3054907358 Feb 18 12:29:35 PM PST 24 Feb 18 12:29:38 PM PST 24 28900868 ps
T71 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2363949300 Feb 18 12:29:11 PM PST 24 Feb 18 12:29:13 PM PST 24 26826600 ps
T72 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1150663135 Feb 18 12:29:24 PM PST 24 Feb 18 12:29:25 PM PST 24 29736459 ps
T35 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.23489068 Feb 18 12:29:20 PM PST 24 Feb 18 12:29:23 PM PST 24 26890783 ps
T73 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1283195007 Feb 18 12:29:27 PM PST 24 Feb 18 12:29:29 PM PST 24 28200658 ps
T74 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2639581290 Feb 18 12:29:36 PM PST 24 Feb 18 12:29:38 PM PST 24 27574107 ps
T75 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1772318422 Feb 18 12:29:43 PM PST 24 Feb 18 12:29:45 PM PST 24 27036943 ps
T76 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2765980558 Feb 18 12:29:28 PM PST 24 Feb 18 12:29:30 PM PST 24 28830129 ps
T77 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1574388838 Feb 18 12:29:21 PM PST 24 Feb 18 12:29:23 PM PST 24 27163488 ps
T78 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3999991425 Feb 18 12:29:23 PM PST 24 Feb 18 12:29:24 PM PST 24 29007691 ps
T79 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.505366310 Feb 18 12:29:32 PM PST 24 Feb 18 12:29:33 PM PST 24 28470742 ps
T80 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2887682578 Feb 18 12:29:16 PM PST 24 Feb 18 12:29:21 PM PST 24 28146778 ps

Test location /workspace/coverage/default/10.prim_async_alert.3187481459
Short name T1
Test name
Test status
Simulation time 11894374 ps
CPU time 0.4 seconds
Started Feb 18 12:27:50 PM PST 24
Finished Feb 18 12:27:57 PM PST 24
Peak memory 145464 kb
Host smart-d0a8d010-afeb-406c-910d-e29160ae6c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187481459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3187481459
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.2770753701
Short name T12
Test name
Test status
Simulation time 30750845 ps
CPU time 0.42 seconds
Started Feb 18 12:27:49 PM PST 24
Finished Feb 18 12:27:58 PM PST 24
Peak memory 145680 kb
Host smart-3d2e7055-d425-4a40-ba95-8d9e16335b76
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2770753701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.2770753701
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3371469312
Short name T40
Test name
Test status
Simulation time 9106648 ps
CPU time 0.38 seconds
Started Feb 18 12:27:49 PM PST 24
Finished Feb 18 12:27:51 PM PST 24
Peak memory 144404 kb
Host smart-aa56cbaa-3a44-4f7d-bf8e-509148a2047e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3371469312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3371469312
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.1866646833
Short name T44
Test name
Test status
Simulation time 9965653 ps
CPU time 0.45 seconds
Started Feb 18 12:27:41 PM PST 24
Finished Feb 18 12:27:43 PM PST 24
Peak memory 144504 kb
Host smart-91b0dbe0-33bd-431a-8784-574e23857c0c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1866646833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1866646833
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3512903622
Short name T5
Test name
Test status
Simulation time 30208150 ps
CPU time 0.49 seconds
Started Feb 18 12:27:39 PM PST 24
Finished Feb 18 12:27:40 PM PST 24
Peak memory 145380 kb
Host smart-28f91a88-0879-4824-893d-ee0fd76b50cb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3512903622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3512903622
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3441198211
Short name T51
Test name
Test status
Simulation time 10843202 ps
CPU time 0.37 seconds
Started Feb 18 12:28:00 PM PST 24
Finished Feb 18 12:28:07 PM PST 24
Peak memory 145396 kb
Host smart-833f8fa8-6362-470a-aa88-03311ee29ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441198211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3441198211
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.713535712
Short name T21
Test name
Test status
Simulation time 11330401 ps
CPU time 0.38 seconds
Started Feb 18 12:27:39 PM PST 24
Finished Feb 18 12:27:40 PM PST 24
Peak memory 145360 kb
Host smart-24b68da2-16c6-4bb9-a103-82fb7d3a2acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713535712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.713535712
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.1366702345
Short name T3
Test name
Test status
Simulation time 11100077 ps
CPU time 0.41 seconds
Started Feb 18 12:27:47 PM PST 24
Finished Feb 18 12:27:49 PM PST 24
Peak memory 144840 kb
Host smart-9f2f834d-3eee-44df-80ad-9cb6426ee707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366702345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.1366702345
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.1661371805
Short name T53
Test name
Test status
Simulation time 10728072 ps
CPU time 0.44 seconds
Started Feb 18 12:27:48 PM PST 24
Finished Feb 18 12:27:58 PM PST 24
Peak memory 144796 kb
Host smart-8914d519-9191-477a-807d-1f587b2e8f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661371805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1661371805
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1354131803
Short name T19
Test name
Test status
Simulation time 11611678 ps
CPU time 0.38 seconds
Started Feb 18 12:27:51 PM PST 24
Finished Feb 18 12:27:58 PM PST 24
Peak memory 145452 kb
Host smart-71c5d80e-bc17-427e-b21f-bc61da256549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354131803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1354131803
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2370052929
Short name T16
Test name
Test status
Simulation time 11517921 ps
CPU time 0.38 seconds
Started Feb 18 12:27:36 PM PST 24
Finished Feb 18 12:27:37 PM PST 24
Peak memory 145640 kb
Host smart-5742cfd9-5a8c-42dc-b11f-057cee33d058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370052929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2370052929
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.4000141009
Short name T9
Test name
Test status
Simulation time 10790951 ps
CPU time 0.39 seconds
Started Feb 18 12:27:38 PM PST 24
Finished Feb 18 12:27:39 PM PST 24
Peak memory 145444 kb
Host smart-0adb8baf-25f5-400b-91b5-afbdf66bd2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000141009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.4000141009
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.2789784320
Short name T20
Test name
Test status
Simulation time 11566574 ps
CPU time 0.38 seconds
Started Feb 18 12:27:48 PM PST 24
Finished Feb 18 12:27:50 PM PST 24
Peak memory 145492 kb
Host smart-34b8c49a-708b-4c8d-b2bb-37a1edfcc9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789784320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.2789784320
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.1920010760
Short name T7
Test name
Test status
Simulation time 10507940 ps
CPU time 0.43 seconds
Started Feb 18 12:27:47 PM PST 24
Finished Feb 18 12:27:49 PM PST 24
Peak memory 144836 kb
Host smart-9a49eccc-f04c-4ca5-bf31-452c61f82141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920010760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.1920010760
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.4219363291
Short name T25
Test name
Test status
Simulation time 11337662 ps
CPU time 0.43 seconds
Started Feb 18 12:27:55 PM PST 24
Finished Feb 18 12:28:01 PM PST 24
Peak memory 145352 kb
Host smart-b06eccf3-a2eb-41bd-9263-31806cd3415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219363291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.4219363291
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3495142267
Short name T8
Test name
Test status
Simulation time 12398400 ps
CPU time 0.41 seconds
Started Feb 18 12:27:42 PM PST 24
Finished Feb 18 12:27:43 PM PST 24
Peak memory 145332 kb
Host smart-b5b8fa1d-ebad-4be0-adb7-9e55b0dab0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495142267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3495142267
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3089392247
Short name T22
Test name
Test status
Simulation time 11140708 ps
CPU time 0.38 seconds
Started Feb 18 12:27:48 PM PST 24
Finished Feb 18 12:27:50 PM PST 24
Peak memory 144744 kb
Host smart-49387f33-f0b7-4510-aabe-c38073f5353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089392247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3089392247
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3298452858
Short name T26
Test name
Test status
Simulation time 10841059 ps
CPU time 0.48 seconds
Started Feb 18 12:27:44 PM PST 24
Finished Feb 18 12:27:46 PM PST 24
Peak memory 145276 kb
Host smart-78a1e9cd-16ce-41dc-ac25-2eb912a40c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298452858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3298452858
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3032804877
Short name T11
Test name
Test status
Simulation time 12281415 ps
CPU time 0.47 seconds
Started Feb 18 12:27:42 PM PST 24
Finished Feb 18 12:27:44 PM PST 24
Peak memory 145140 kb
Host smart-cfe5706a-d546-4860-a9dd-41a594a8e229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032804877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3032804877
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3124457912
Short name T23
Test name
Test status
Simulation time 10938741 ps
CPU time 0.43 seconds
Started Feb 18 12:27:48 PM PST 24
Finished Feb 18 12:27:58 PM PST 24
Peak memory 144668 kb
Host smart-a520a528-f847-40d0-bac3-256fd95ad348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124457912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3124457912
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3159878290
Short name T24
Test name
Test status
Simulation time 12409669 ps
CPU time 0.39 seconds
Started Feb 18 12:27:51 PM PST 24
Finished Feb 18 12:27:58 PM PST 24
Peak memory 144988 kb
Host smart-616a3413-6ae0-409b-a71f-05bc008b8bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159878290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3159878290
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.1643656913
Short name T10
Test name
Test status
Simulation time 11271235 ps
CPU time 0.39 seconds
Started Feb 18 12:27:55 PM PST 24
Finished Feb 18 12:28:01 PM PST 24
Peak memory 145092 kb
Host smart-0ce017d0-9e59-477e-8e04-7a9f77885100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643656913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1643656913
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.642002600
Short name T2
Test name
Test status
Simulation time 11071866 ps
CPU time 0.38 seconds
Started Feb 18 12:27:49 PM PST 24
Finished Feb 18 12:27:51 PM PST 24
Peak memory 145064 kb
Host smart-417a18fc-d71a-4885-abc9-e02b96006415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642002600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.642002600
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.1793866366
Short name T52
Test name
Test status
Simulation time 10843232 ps
CPU time 0.38 seconds
Started Feb 18 12:27:54 PM PST 24
Finished Feb 18 12:28:00 PM PST 24
Peak memory 145092 kb
Host smart-4c4bb48d-d3b0-41c0-9cb9-036521252194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793866366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1793866366
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3809192577
Short name T18
Test name
Test status
Simulation time 31225723 ps
CPU time 0.47 seconds
Started Feb 18 12:27:49 PM PST 24
Finished Feb 18 12:27:53 PM PST 24
Peak memory 144584 kb
Host smart-e899b4c0-6a3b-4a6a-a83a-9992bfeaf1f3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3809192577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3809192577
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.626781548
Short name T13
Test name
Test status
Simulation time 29794816 ps
CPU time 0.4 seconds
Started Feb 18 12:27:50 PM PST 24
Finished Feb 18 12:27:55 PM PST 24
Peak memory 145240 kb
Host smart-252acbcf-227f-44f7-8213-edf49b5ed287
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=626781548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.626781548
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.1882790417
Short name T59
Test name
Test status
Simulation time 30595160 ps
CPU time 0.46 seconds
Started Feb 18 12:27:55 PM PST 24
Finished Feb 18 12:28:01 PM PST 24
Peak memory 143476 kb
Host smart-5f331481-b0f9-47bc-b33a-624cda122216
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1882790417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.1882790417
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.723632600
Short name T49
Test name
Test status
Simulation time 31234192 ps
CPU time 0.4 seconds
Started Feb 18 12:27:42 PM PST 24
Finished Feb 18 12:27:43 PM PST 24
Peak memory 145416 kb
Host smart-a44cd918-0dfa-4ff4-b6e6-d6c8e457c675
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=723632600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.723632600
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.2616013810
Short name T47
Test name
Test status
Simulation time 29348428 ps
CPU time 0.45 seconds
Started Feb 18 12:27:49 PM PST 24
Finished Feb 18 12:27:53 PM PST 24
Peak memory 144848 kb
Host smart-dbc93019-d7a2-4b7f-94a1-2c85f5d813df
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2616013810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.2616013810
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1602701445
Short name T58
Test name
Test status
Simulation time 30392402 ps
CPU time 0.42 seconds
Started Feb 18 12:27:56 PM PST 24
Finished Feb 18 12:28:02 PM PST 24
Peak memory 145436 kb
Host smart-80d9eeb3-d13d-417f-a6d9-47a3d2901f86
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1602701445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1602701445
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.2018809986
Short name T57
Test name
Test status
Simulation time 28621834 ps
CPU time 0.41 seconds
Started Feb 18 12:27:48 PM PST 24
Finished Feb 18 12:27:58 PM PST 24
Peak memory 145516 kb
Host smart-7ec48bfe-680c-4456-9200-d0f66b41d41e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2018809986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.2018809986
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.855303441
Short name T55
Test name
Test status
Simulation time 28976811 ps
CPU time 0.41 seconds
Started Feb 18 12:27:45 PM PST 24
Finished Feb 18 12:27:46 PM PST 24
Peak memory 145420 kb
Host smart-6998523b-817f-4ea4-9316-8ed86e1593c7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=855303441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.855303441
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.367299426
Short name T15
Test name
Test status
Simulation time 29412878 ps
CPU time 0.41 seconds
Started Feb 18 12:27:56 PM PST 24
Finished Feb 18 12:28:02 PM PST 24
Peak memory 145416 kb
Host smart-33966897-2de0-4505-b88d-d5d3e7b12a24
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=367299426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.367299426
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.639320685
Short name T17
Test name
Test status
Simulation time 30267277 ps
CPU time 0.49 seconds
Started Feb 18 12:27:43 PM PST 24
Finished Feb 18 12:27:44 PM PST 24
Peak memory 145376 kb
Host smart-b8456c1d-40f2-44d7-bbf0-32b7abe86a14
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=639320685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.639320685
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4071287457
Short name T54
Test name
Test status
Simulation time 29628582 ps
CPU time 0.47 seconds
Started Feb 18 12:27:49 PM PST 24
Finished Feb 18 12:27:53 PM PST 24
Peak memory 145008 kb
Host smart-f32b1b42-ea5a-4c35-bf49-19207981b471
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4071287457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4071287457
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.643212868
Short name T45
Test name
Test status
Simulation time 30273815 ps
CPU time 0.49 seconds
Started Feb 18 12:27:45 PM PST 24
Finished Feb 18 12:27:46 PM PST 24
Peak memory 145040 kb
Host smart-9c6d9d30-8bfc-4563-8bff-0b6e681f4bb3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=643212868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.643212868
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3981612975
Short name T48
Test name
Test status
Simulation time 28859515 ps
CPU time 0.48 seconds
Started Feb 18 12:27:49 PM PST 24
Finished Feb 18 12:27:52 PM PST 24
Peak memory 145200 kb
Host smart-d6d04255-36e1-4d02-a02e-cbad457f9d76
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3981612975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3981612975
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2064919211
Short name T56
Test name
Test status
Simulation time 29056358 ps
CPU time 0.4 seconds
Started Feb 18 12:27:56 PM PST 24
Finished Feb 18 12:28:03 PM PST 24
Peak memory 145488 kb
Host smart-b0e58524-6721-4ae6-bb52-fe9bd604a79e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2064919211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2064919211
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2913765650
Short name T14
Test name
Test status
Simulation time 28791524 ps
CPU time 0.39 seconds
Started Feb 18 12:27:57 PM PST 24
Finished Feb 18 12:28:03 PM PST 24
Peak memory 145560 kb
Host smart-4a0178bc-7f45-4f7a-8df9-74e4191f1cb0
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2913765650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2913765650
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.2273457640
Short name T50
Test name
Test status
Simulation time 30752048 ps
CPU time 0.48 seconds
Started Feb 18 12:27:45 PM PST 24
Finished Feb 18 12:27:46 PM PST 24
Peak memory 144752 kb
Host smart-c290da3d-e634-4129-ba5e-abb0d4911a95
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2273457640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.2273457640
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2367069876
Short name T46
Test name
Test status
Simulation time 30500872 ps
CPU time 0.39 seconds
Started Feb 18 12:27:50 PM PST 24
Finished Feb 18 12:27:54 PM PST 24
Peak memory 145144 kb
Host smart-8b09250a-8cd8-4d6a-a225-ca8e0d198ce8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2367069876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2367069876
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2414635458
Short name T4
Test name
Test status
Simulation time 29578743 ps
CPU time 0.4 seconds
Started Feb 18 12:27:41 PM PST 24
Finished Feb 18 12:27:42 PM PST 24
Peak memory 145428 kb
Host smart-b05d552d-d975-4509-bfb9-1c89524e6f93
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2414635458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2414635458
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.666311381
Short name T28
Test name
Test status
Simulation time 8704940 ps
CPU time 0.37 seconds
Started Feb 18 12:27:51 PM PST 24
Finished Feb 18 12:27:58 PM PST 24
Peak memory 144892 kb
Host smart-5656f472-e93e-4a3a-9773-245644fb2aa1
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=666311381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.666311381
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.1664001122
Short name T27
Test name
Test status
Simulation time 8850781 ps
CPU time 0.38 seconds
Started Feb 18 12:28:04 PM PST 24
Finished Feb 18 12:28:09 PM PST 24
Peak memory 144908 kb
Host smart-8cc431a7-a374-49dd-af3c-439b4fad24cb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1664001122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1664001122
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2047643570
Short name T64
Test name
Test status
Simulation time 8848806 ps
CPU time 0.38 seconds
Started Feb 18 12:28:02 PM PST 24
Finished Feb 18 12:28:08 PM PST 24
Peak memory 144972 kb
Host smart-6801aff5-8067-4349-9b45-b884150b9681
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2047643570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2047643570
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3425991039
Short name T42
Test name
Test status
Simulation time 8736978 ps
CPU time 0.44 seconds
Started Feb 18 12:27:47 PM PST 24
Finished Feb 18 12:27:49 PM PST 24
Peak memory 144580 kb
Host smart-c741c801-24d5-4a32-b6fb-cdf1ea67132c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3425991039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3425991039
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.4012232620
Short name T30
Test name
Test status
Simulation time 9173834 ps
CPU time 0.46 seconds
Started Feb 18 12:27:58 PM PST 24
Finished Feb 18 12:28:05 PM PST 24
Peak memory 143272 kb
Host smart-6187e5d8-6262-49bc-bbec-cb73db2cd55d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4012232620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.4012232620
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.231707309
Short name T62
Test name
Test status
Simulation time 9333193 ps
CPU time 0.39 seconds
Started Feb 18 12:28:05 PM PST 24
Finished Feb 18 12:28:10 PM PST 24
Peak memory 144904 kb
Host smart-87a05e55-8dc0-47c9-8493-cdc504d16c7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=231707309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.231707309
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3233092048
Short name T29
Test name
Test status
Simulation time 8819973 ps
CPU time 0.37 seconds
Started Feb 18 12:28:00 PM PST 24
Finished Feb 18 12:28:06 PM PST 24
Peak memory 144648 kb
Host smart-00b97f30-49b4-4db9-9bb9-ca02b6ee1b91
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3233092048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3233092048
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1001584940
Short name T60
Test name
Test status
Simulation time 9155626 ps
CPU time 0.42 seconds
Started Feb 18 12:28:16 PM PST 24
Finished Feb 18 12:28:22 PM PST 24
Peak memory 144880 kb
Host smart-12f5e82d-4466-4d04-b0ee-d9c0ab27dfea
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1001584940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1001584940
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1718157937
Short name T63
Test name
Test status
Simulation time 10723767 ps
CPU time 0.51 seconds
Started Feb 18 12:28:07 PM PST 24
Finished Feb 18 12:28:14 PM PST 24
Peak memory 144588 kb
Host smart-0c3c6b8d-35d4-4543-9811-2e80fa0a29ae
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1718157937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1718157937
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1261895963
Short name T31
Test name
Test status
Simulation time 10510954 ps
CPU time 0.36 seconds
Started Feb 18 12:28:05 PM PST 24
Finished Feb 18 12:28:10 PM PST 24
Peak memory 144904 kb
Host smart-7aa36a8d-fec6-452a-a981-775ab36107e3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1261895963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1261895963
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.1089549967
Short name T39
Test name
Test status
Simulation time 9524822 ps
CPU time 0.38 seconds
Started Feb 18 12:27:50 PM PST 24
Finished Feb 18 12:27:57 PM PST 24
Peak memory 144720 kb
Host smart-ebf2f113-7f72-49e1-ae8e-f092e9f5a112
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1089549967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1089549967
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.2439585352
Short name T41
Test name
Test status
Simulation time 9576753 ps
CPU time 0.39 seconds
Started Feb 18 12:28:06 PM PST 24
Finished Feb 18 12:28:12 PM PST 24
Peak memory 144816 kb
Host smart-b06dbb07-298f-466f-b1d2-65766db1b2de
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2439585352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.2439585352
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1836933513
Short name T37
Test name
Test status
Simulation time 9059077 ps
CPU time 0.39 seconds
Started Feb 18 12:27:58 PM PST 24
Finished Feb 18 12:28:05 PM PST 24
Peak memory 144524 kb
Host smart-a7bab50b-0974-45db-893f-3fe524f207cb
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1836933513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1836933513
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.64525073
Short name T32
Test name
Test status
Simulation time 9710582 ps
CPU time 0.37 seconds
Started Feb 18 12:28:08 PM PST 24
Finished Feb 18 12:28:16 PM PST 24
Peak memory 144888 kb
Host smart-e1a3d17f-9d95-4d7a-aa63-381575b311fd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=64525073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.64525073
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.2060353278
Short name T61
Test name
Test status
Simulation time 9358712 ps
CPU time 0.38 seconds
Started Feb 18 12:27:45 PM PST 24
Finished Feb 18 12:27:47 PM PST 24
Peak memory 144560 kb
Host smart-0432401b-ff39-47a6-be4a-367114ac1a07
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2060353278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.2060353278
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.859410763
Short name T43
Test name
Test status
Simulation time 10060953 ps
CPU time 0.38 seconds
Started Feb 18 12:27:45 PM PST 24
Finished Feb 18 12:27:47 PM PST 24
Peak memory 144568 kb
Host smart-68bdbe90-6de0-4903-bd2d-792bae3c7bd6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=859410763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.859410763
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.375082531
Short name T38
Test name
Test status
Simulation time 8579634 ps
CPU time 0.47 seconds
Started Feb 18 12:27:58 PM PST 24
Finished Feb 18 12:28:05 PM PST 24
Peak memory 143664 kb
Host smart-50c04f20-9d96-40d6-9dc3-5ef717bf2dde
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=375082531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.375082531
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2485780101
Short name T36
Test name
Test status
Simulation time 8201609 ps
CPU time 0.39 seconds
Started Feb 18 12:28:01 PM PST 24
Finished Feb 18 12:28:13 PM PST 24
Peak memory 144888 kb
Host smart-e9a01abb-00f1-4164-84f0-85966d5661dd
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2485780101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2485780101
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.505366310
Short name T79
Test name
Test status
Simulation time 28470742 ps
CPU time 0.41 seconds
Started Feb 18 12:29:32 PM PST 24
Finished Feb 18 12:29:33 PM PST 24
Peak memory 145048 kb
Host smart-8c833278-d4dc-4c2f-acd0-e74b8aa1c154
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=505366310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.505366310
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.23489068
Short name T35
Test name
Test status
Simulation time 26890783 ps
CPU time 0.39 seconds
Started Feb 18 12:29:20 PM PST 24
Finished Feb 18 12:29:23 PM PST 24
Peak memory 145048 kb
Host smart-af9baebc-c0c4-4048-a502-9dc8d908c5e2
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=23489068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.23489068
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2488780763
Short name T66
Test name
Test status
Simulation time 26134980 ps
CPU time 0.41 seconds
Started Feb 18 12:29:46 PM PST 24
Finished Feb 18 12:29:49 PM PST 24
Peak memory 145076 kb
Host smart-a5deb612-94ae-4f67-9de5-aa737d116c40
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2488780763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2488780763
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1772318422
Short name T75
Test name
Test status
Simulation time 27036943 ps
CPU time 0.38 seconds
Started Feb 18 12:29:43 PM PST 24
Finished Feb 18 12:29:45 PM PST 24
Peak memory 145084 kb
Host smart-cacd1331-8cc3-483a-ac17-ac694fb36781
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1772318422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1772318422
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2441768250
Short name T69
Test name
Test status
Simulation time 26588500 ps
CPU time 0.41 seconds
Started Feb 18 12:29:27 PM PST 24
Finished Feb 18 12:29:28 PM PST 24
Peak memory 145084 kb
Host smart-01253a07-e961-4de7-b999-2f8bb50e20b5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2441768250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2441768250
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1294773653
Short name T33
Test name
Test status
Simulation time 30613637 ps
CPU time 0.39 seconds
Started Feb 18 12:29:22 PM PST 24
Finished Feb 18 12:29:24 PM PST 24
Peak memory 145084 kb
Host smart-31e8d831-989c-4005-896a-2f3e85eea2a4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1294773653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1294773653
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.2765980558
Short name T76
Test name
Test status
Simulation time 28830129 ps
CPU time 0.4 seconds
Started Feb 18 12:29:28 PM PST 24
Finished Feb 18 12:29:30 PM PST 24
Peak memory 145192 kb
Host smart-71e8316d-19ab-41b3-ac24-2759417cbab9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2765980558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.2765980558
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.580747096
Short name T65
Test name
Test status
Simulation time 26086063 ps
CPU time 0.4 seconds
Started Feb 18 12:29:32 PM PST 24
Finished Feb 18 12:29:34 PM PST 24
Peak memory 145088 kb
Host smart-21c08aee-caf2-4cde-a566-206e2536ca97
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=580747096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.580747096
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.1150663135
Short name T72
Test name
Test status
Simulation time 29736459 ps
CPU time 0.4 seconds
Started Feb 18 12:29:24 PM PST 24
Finished Feb 18 12:29:25 PM PST 24
Peak memory 145108 kb
Host smart-847f8b79-f9d7-4db5-ac1e-086951cf622d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1150663135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.1150663135
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1574388838
Short name T77
Test name
Test status
Simulation time 27163488 ps
CPU time 0.42 seconds
Started Feb 18 12:29:21 PM PST 24
Finished Feb 18 12:29:23 PM PST 24
Peak memory 145072 kb
Host smart-7a9f2862-842a-4018-94aa-014f3b0b2eaa
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1574388838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1574388838
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3054907358
Short name T34
Test name
Test status
Simulation time 28900868 ps
CPU time 0.39 seconds
Started Feb 18 12:29:35 PM PST 24
Finished Feb 18 12:29:38 PM PST 24
Peak memory 145076 kb
Host smart-1b3d9987-8d20-4a83-9960-2515a8bcfc89
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3054907358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3054907358
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2639581290
Short name T74
Test name
Test status
Simulation time 27574107 ps
CPU time 0.46 seconds
Started Feb 18 12:29:36 PM PST 24
Finished Feb 18 12:29:38 PM PST 24
Peak memory 145004 kb
Host smart-5f8eea82-4b04-4fa3-9bd1-0fa8bcee4b14
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2639581290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2639581290
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3999991425
Short name T78
Test name
Test status
Simulation time 29007691 ps
CPU time 0.4 seconds
Started Feb 18 12:29:23 PM PST 24
Finished Feb 18 12:29:24 PM PST 24
Peak memory 145068 kb
Host smart-acf8d878-8d11-4074-a3ff-cef66c3511ff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3999991425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3999991425
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2363949300
Short name T71
Test name
Test status
Simulation time 26826600 ps
CPU time 0.39 seconds
Started Feb 18 12:29:11 PM PST 24
Finished Feb 18 12:29:13 PM PST 24
Peak memory 145088 kb
Host smart-0a320568-6221-4e82-9b92-99152827bbb8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2363949300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2363949300
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3067473462
Short name T67
Test name
Test status
Simulation time 25544454 ps
CPU time 0.42 seconds
Started Feb 18 12:29:38 PM PST 24
Finished Feb 18 12:29:40 PM PST 24
Peak memory 145080 kb
Host smart-fc08ec4d-d131-47c1-9670-30834dab9aa7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3067473462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3067473462
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.117128726
Short name T68
Test name
Test status
Simulation time 26764123 ps
CPU time 0.39 seconds
Started Feb 18 12:29:22 PM PST 24
Finished Feb 18 12:29:24 PM PST 24
Peak memory 145036 kb
Host smart-049550ed-1af3-4ee3-93ae-b7ad4cf3f72b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=117128726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.117128726
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1089755062
Short name T6
Test name
Test status
Simulation time 27362046 ps
CPU time 0.39 seconds
Started Feb 18 12:29:27 PM PST 24
Finished Feb 18 12:29:29 PM PST 24
Peak memory 144996 kb
Host smart-bc7bd5ad-6345-4f5d-8336-b42b40ed8747
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1089755062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1089755062
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.1283195007
Short name T73
Test name
Test status
Simulation time 28200658 ps
CPU time 0.4 seconds
Started Feb 18 12:29:27 PM PST 24
Finished Feb 18 12:29:29 PM PST 24
Peak memory 145088 kb
Host smart-85c94fed-d027-4ad1-bec3-03f08b11a37a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1283195007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1283195007
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.287455453
Short name T70
Test name
Test status
Simulation time 28647551 ps
CPU time 0.41 seconds
Started Feb 18 12:29:28 PM PST 24
Finished Feb 18 12:29:30 PM PST 24
Peak memory 145044 kb
Host smart-8908c154-2c1a-4765-821e-f5c8b5f4e36b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=287455453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.287455453
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2887682578
Short name T80
Test name
Test status
Simulation time 28146778 ps
CPU time 0.41 seconds
Started Feb 18 12:29:16 PM PST 24
Finished Feb 18 12:29:21 PM PST 24
Peak memory 145100 kb
Host smart-662b480d-37e7-4396-821a-a6c6320c5289
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2887682578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2887682578
Directory /workspace/9.prim_sync_fatal_alert/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%