Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T10
1	0	Covered	T11,T12

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T13	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T3,T6
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T14,T15,T16
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T17,T18,T19
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T3,T20,T17

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	156352	116953	0	160
AlertKnownO_A	157066	118672	0	0
InBandInitRequest_A	157066	4055	0	0
InBandInitSequence_A	157066	426	0	0
InitReq_A	157066	761	0	0
IntegFailKnownO_A	157066	118672	0	0
NoSpuriousAlertsDuringInit_A	157066	16156	0	0
NoSpuriousPingOksDuringInit_A	157066	15848	0	0
PingDiffOk_A	156131	117737	0	0
PingOkBypassDuringInit_A	157066	51	0	40
PingOkKnownO_A	157066	118672	0	0
PingPKnownO_A	157066	118672	0	0
PingPending_A	157066	839	0	120
PingRequest0_A	157066	0	0	80
PingResponse0_A	157066	770	0	0
gen_async_assert.Alert_A	83130	1412	0	0
gen_async_assert.PingResponse1_A	83130	312	0	0
gen_async_assert.SigInt_A	83130	251	0	94
gen_sync_assert.Alert_A	73936	3105	0	0
gen_sync_assert.PingResponse1_A	73936	353	0	0
gen_sync_assert.SigInt_A	73936	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156352	116953	0	160
T1	1062	1008	0	2
T2	1096	976	0	2
T3	1177	997	0	2
T6	1064	987	0	2
T7	1152	1056	0	2
T9	1109	1036	0	2
T17	1112	1025	0	2
T20	1120	1023	0	2
T21	1046	986	0	2
T22	1018	952	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	118672	0	0
T1	1077	1025	0	0
T2	1109	992	0	0
T3	1191	1015	0	0
T6	1080	1005	0	0
T7	1166	1072	0	0
T9	1124	1053	0	0
T17	1126	1041	0	0
T20	1135	1040	0	0
T21	1060	1002	0	0
T22	1032	968	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	4055	0	0
T1	1077	37	0	0
T2	1109	59	0	0
T3	1191	56	0	0
T6	1080	28	0	0
T7	1166	51	0	0
T9	1124	59	0	0
T17	1126	42	0	0
T20	1135	55	0	0
T21	1060	35	0	0
T22	1032	49	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	426	0	0
T1	1077	1	0	0
T2	1109	3	0	0
T3	1191	2	0	0
T6	1080	1	0	0
T7	1166	3	0	0
T9	1124	2	0	0
T17	1126	1	0	0
T20	1135	3	0	0
T21	1060	1	0	0
T22	1032	1	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	761	0	0
T1	1077	6	0	0
T2	1109	10	0	0
T3	1191	8	0	0
T6	1080	7	0	0
T7	1166	10	0	0
T9	1124	10	0	0
T17	1126	9	0	0
T20	1135	10	0	0
T21	1060	7	0	0
T22	1032	8	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	118672	0	0
T1	1077	1025	0	0
T2	1109	992	0	0
T3	1191	1015	0	0
T6	1080	1005	0	0
T7	1166	1072	0	0
T9	1124	1053	0	0
T17	1126	1041	0	0
T20	1135	1040	0	0
T21	1060	1002	0	0
T22	1032	968	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	16156	0	0
T1	1077	123	0	0
T2	1109	198	0	0
T3	1191	181	0	0
T6	1080	140	0	0
T7	1166	200	0	0
T9	1124	202	0	0
T17	1126	176	0	0
T20	1135	199	0	0
T21	1060	143	0	0
T22	1032	157	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	15848	0	0
T1	1077	123	0	0
T2	1109	186	0	0
T3	1191	178	0	0
T6	1080	139	0	0
T7	1166	195	0	0
T9	1124	180	0	0
T17	1126	176	0	0
T20	1135	197	0	0
T21	1060	141	0	0
T22	1032	153	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156131	117737	0	0
T1	1059	1007	0	0
T2	1096	979	0	0
T3	1174	998	0	0
T6	1063	988	0	0
T7	1149	1055	0	0
T9	1113	1042	0	0
T17	1113	1028	0	0
T20	1117	1022	0	0
T21	1048	990	0	0
T22	1014	950	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	51	0	40
T2	1109	2	0	0
T3	1191	1	0	0
T4	0	0	0	1
T6	1080	0	0	0
T7	1166	0	0	0
T9	1124	1	0	0
T10	1058	1	0	0
T12	0	0	0	1
T14	0	1	0	0
T17	1126	0	0	0
T18	0	2	0	0
T20	1135	2	0	0
T21	1060	0	0	0
T22	1032	2	0	0
T23	0	2	0	0
T24	0	2	0	0
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	118672	0	0
T1	1077	1025	0	0
T2	1109	992	0	0
T3	1191	1015	0	0
T6	1080	1005	0	0
T7	1166	1072	0	0
T9	1124	1053	0	0
T17	1126	1041	0	0
T20	1135	1040	0	0
T21	1060	1002	0	0
T22	1032	968	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	118672	0	0
T1	1077	1025	0	0
T2	1109	992	0	0
T3	1191	1015	0	0
T6	1080	1005	0	0
T7	1166	1072	0	0
T9	1124	1053	0	0
T17	1126	1041	0	0
T20	1135	1040	0	0
T21	1060	1002	0	0
T22	1032	968	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	839	0	120
T1	1077	11	0	1
T2	1109	11	0	1
T3	1191	11	0	1
T6	1080	11	0	1
T7	1166	11	0	1
T9	1124	11	0	1
T17	1126	11	0	1
T20	1135	11	0	1
T21	1060	11	0	1
T22	1032	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	0	0	80

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157066	770	0	0
T1	1077	10	0	0
T2	1109	10	0	0
T3	1191	10	0	0
T6	1080	9	0	0
T7	1166	9	0	0
T9	1124	10	0	0
T17	1126	10	0	0
T20	1135	10	0	0
T21	1060	10	0	0
T22	1032	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83130	1412	0	0
T1	1077	11	0	0
T2	1109	7	0	0
T3	1191	8	0	0
T6	1080	9	0	0
T7	1166	7	0	0
T9	1124	5	0	0
T17	1126	7	0	0
T20	1135	8	0	0
T21	1060	8	0	0
T22	1032	8	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83130	312	0	0
T1	1077	10	0	0
T2	1109	7	0	0
T3	1191	8	0	0
T6	1080	9	0	0
T7	1166	7	0	0
T9	1124	9	0	0
T17	1126	10	0	0
T20	1135	8	0	0
T21	1060	9	0	0
T22	1032	7	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83130	251	0	94
T1	1077	8	0	2
T2	1109	7	0	1
T3	1191	5	0	2
T6	1080	8	0	2
T7	1166	6	0	3
T9	1124	7	0	1
T17	1126	6	0	2
T20	1135	5	0	3
T21	1060	6	0	1
T22	1032	5	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73936	3105	0	0
T11	935	12	0	0
T25	962	10	0	0
T26	934	8	0	0
T27	900	9	0	0
T28	958	11	0	0
T29	991	8	0	0
T30	809	10	0	0
T33	1009	12	0	0
T34	899	9	0	0
T35	931	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73936	353	0	0
T11	935	9	0	0
T25	962	9	0	0
T26	934	9	0	0
T27	900	8	0	0
T28	958	9	0	0
T29	991	8	0	0
T30	809	9	0	0
T33	1009	10	0	0
T34	899	10	0	0
T35	931	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73936	40	0	0
T11	935	1	0	0
T25	962	1	0	0
T26	934	1	0	0
T27	900	1	0	0
T28	958	1	0	0
T29	991	1	0	0
T30	809	1	0	0
T33	1009	1	0	0
T34	899	1	0	0
T35	931	1	0	0