Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T8,T9,T10

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T10,T14
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T12,T15,T16
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T6,T17,T18

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	156505	117933	0	158
AlertKnownO_A	157200	119628	0	0
InBandInitRequest_A	157200	4321	0	0
InBandInitSequence_A	157200	436	0	0
InitReq_A	157200	792	0	0
IntegFailKnownO_A	157200	119628	0	0
NoSpuriousAlertsDuringInit_A	157200	16780	0	0
NoSpuriousPingOksDuringInit_A	157200	16457	0	0
PingDiffOk_A	156297	118725	0	0
PingOkBypassDuringInit_A	157200	50	0	40
PingOkKnownO_A	157200	119628	0	0
PingPKnownO_A	157200	119628	0	0
PingPending_A	157200	829	0	119
PingRequest0_A	157200	0	0	79
PingResponse0_A	157200	768	0	0
gen_async_assert.Alert_A	82484	1408	0	0
gen_async_assert.PingResponse1_A	82484	305	0	0
gen_async_assert.SigInt_A	82484	234	0	98
gen_sync_assert.Alert_A	74716	3226	0	0
gen_sync_assert.PingResponse1_A	74716	354	0	0
gen_sync_assert.SigInt_A	74716	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156505	117933	0	158
T1	1078	979	0	2
T2	1096	1040	0	2
T3	1165	1065	0	2
T6	1119	1030	0	2
T7	1069	1007	0	2
T19	1141	1075	0	2
T20	1055	975	0	2
T21	1134	1047	0	2
T22	1079	1021	0	2
T23	1091	1024	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	119628	0	0
T1	1092	995	0	0
T2	1112	1058	0	0
T3	1178	1080	0	0
T6	1134	1047	0	0
T7	1082	1022	0	0
T19	1156	1092	0	0
T20	1068	990	0	0
T21	1148	1063	0	0
T22	1094	1038	0	0
T23	1106	1041	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	4321	0	0
T1	1092	48	0	0
T2	1112	57	0	0
T3	1178	67	0	0
T6	1134	51	0	0
T7	1082	41	0	0
T19	1156	73	0	0
T20	1068	30	0	0
T21	1148	60	0	0
T22	1094	46	0	0
T23	1106	42	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	436	0	0
T1	1092	2	0	0
T2	1112	3	0	0
T3	1178	2	0	0
T6	1134	1	0	0
T7	1082	1	0	0
T11	0	1	0	0
T19	1156	0	0	0
T20	1068	1	0	0
T21	1148	2	0	0
T22	1094	2	0	0
T23	1106	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	792	0	0
T1	1092	9	0	0
T2	1112	11	0	0
T3	1178	14	0	0
T6	1134	12	0	0
T7	1082	9	0	0
T19	1156	13	0	0
T20	1068	7	0	0
T21	1148	13	0	0
T22	1094	10	0	0
T23	1106	7	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	119628	0	0
T1	1092	995	0	0
T2	1112	1058	0	0
T3	1178	1080	0	0
T6	1134	1047	0	0
T7	1082	1022	0	0
T19	1156	1092	0	0
T20	1068	990	0	0
T21	1148	1063	0	0
T22	1094	1038	0	0
T23	1106	1041	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	16780	0	0
T1	1092	183	0	0
T2	1112	221	0	0
T3	1178	271	0	0
T6	1134	229	0	0
T7	1082	177	0	0
T19	1156	253	0	0
T20	1068	141	0	0
T21	1148	252	0	0
T22	1094	200	0	0
T23	1106	141	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	16457	0	0
T1	1092	171	0	0
T2	1112	216	0	0
T3	1178	254	0	0
T6	1134	226	0	0
T7	1082	144	0	0
T19	1156	234	0	0
T20	1068	128	0	0
T21	1148	237	0	0
T22	1094	184	0	0
T23	1106	141	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156297	118725	0	0
T1	1076	979	0	0
T2	1095	1041	0	0
T3	1159	1061	0	0
T6	1120	1033	0	0
T7	1069	1009	0	0
T19	1140	1076	0	0
T20	1054	976	0	0
T21	1134	1049	0	0
T22	1080	1024	0	0
T23	1091	1026	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	50	0	40
T1	1092	1	0	0
T2	1112	1	0	0
T3	1178	1	0	0
T5	0	0	0	1
T6	1134	1	0	0
T7	1082	1	0	0
T11	0	1	0	0
T18	0	0	0	1
T19	1156	1	0	0
T20	1068	0	0	0
T21	1148	0	0	0
T22	1094	1	0	0
T23	1106	0	0	0
T24	0	2	0	0
T25	0	1	0	0
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	119628	0	0
T1	1092	995	0	0
T2	1112	1058	0	0
T3	1178	1080	0	0
T6	1134	1047	0	0
T7	1082	1022	0	0
T19	1156	1092	0	0
T20	1068	990	0	0
T21	1148	1063	0	0
T22	1094	1038	0	0
T23	1106	1041	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	119628	0	0
T1	1092	995	0	0
T2	1112	1058	0	0
T3	1178	1080	0	0
T6	1134	1047	0	0
T7	1082	1022	0	0
T19	1156	1092	0	0
T20	1068	990	0	0
T21	1148	1063	0	0
T22	1094	1038	0	0
T23	1106	1041	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	829	0	119
T1	1092	11	0	1
T2	1112	11	0	1
T3	1178	11	0	1
T6	1134	11	0	1
T7	1082	11	0	1
T19	1156	11	0	1
T20	1068	11	0	1
T21	1148	11	0	1
T22	1094	11	0	1
T23	1106	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	0	0	79

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157200	768	0	0
T1	1092	9	0	0
T2	1112	10	0	0
T3	1178	9	0	0
T6	1134	9	0	0
T7	1082	10	0	0
T19	1156	10	0	0
T20	1068	10	0	0
T21	1148	10	0	0
T22	1094	10	0	0
T23	1106	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82484	1408	0	0
T1	1092	10	0	0
T2	1112	7	0	0
T3	1178	6	0	0
T6	1134	5	0	0
T7	1082	10	0	0
T19	1156	5	0	0
T20	1068	9	0	0
T21	1148	4	0	0
T22	1094	8	0	0
T23	1106	8	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82484	305	0	0
T1	1092	7	0	0
T2	1112	7	0	0
T3	1178	6	0	0
T6	1134	8	0	0
T7	1082	7	0	0
T19	1156	7	0	0
T20	1068	10	0	0
T21	1148	8	0	0
T22	1094	7	0	0
T23	1106	10	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82484	234	0	98
T1	1092	6	0	2
T2	1112	6	0	2
T3	1178	5	0	3
T6	1134	5	0	3
T7	1082	5	0	2
T19	1156	6	0	2
T20	1068	5	0	3
T21	1148	5	0	2
T22	1094	6	0	2
T23	1106	6	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74716	3226	0	0
T18	941	11	0	0
T26	846	9	0	0
T27	980	10	0	0
T34	939	9	0	0
T35	950	9	0	0
T36	898	12	0	0
T37	858	8	0	0
T38	935	10	0	0
T39	927	12	0	0
T40	1025	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74716	354	0	0
T18	941	7	0	0
T26	846	8	0	0
T27	980	8	0	0
T34	939	10	0	0
T35	950	9	0	0
T36	898	10	0	0
T37	858	10	0	0
T38	935	9	0	0
T39	927	8	0	0
T40	1025	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74716	40	0	0
T18	941	1	0	0
T26	846	1	0	0
T27	980	1	0	0
T34	939	1	0	0
T35	950	1	0	0
T36	898	1	0	0
T37	858	1	0	0
T38	935	1	0	0
T39	927	1	0	0
T40	1025	1	0	0