Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	100.00	100.00	89.29	95.83	86.05

Total tests in report: 79

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
88.53	88.53	100.00	100.00	91.67	91.67	100.00	100.00	78.57	78.57	95.83	95.83	65.12	65.12	/workspace/coverage/default/16.prim_async_alert.1544179201
91.66	3.13	100.00	0.00	91.67	0.00	100.00	0.00	85.71	7.14	95.83	0.00	76.74	11.63	/workspace/coverage/sync_alert/5.prim_sync_alert.3169460724
93.76	2.11	100.00	0.00	93.75	2.08	100.00	0.00	89.29	3.57	95.83	0.00	83.72	6.98	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1897624967
94.50	0.73	100.00	0.00	95.83	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	2.33	/workspace/coverage/default/13.prim_async_alert.123845241
94.85	0.35	100.00	0.00	97.92	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4270219499
95.19	0.35	100.00	0.00	100.00	2.08	100.00	0.00	89.29	0.00	95.83	0.00	86.05	0.00	/workspace/coverage/sync_alert/2.prim_sync_alert.978156513

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2109262382
/workspace/coverage/default/1.prim_async_alert.2127367229
/workspace/coverage/default/10.prim_async_alert.3977424932
/workspace/coverage/default/11.prim_async_alert.3407123350
/workspace/coverage/default/12.prim_async_alert.1102399374
/workspace/coverage/default/14.prim_async_alert.2937717352
/workspace/coverage/default/15.prim_async_alert.1293725810
/workspace/coverage/default/17.prim_async_alert.60214650
/workspace/coverage/default/18.prim_async_alert.3081571294
/workspace/coverage/default/19.prim_async_alert.3278554120
/workspace/coverage/default/2.prim_async_alert.2465089749
/workspace/coverage/default/3.prim_async_alert.2167900080
/workspace/coverage/default/4.prim_async_alert.636300704
/workspace/coverage/default/5.prim_async_alert.1857848192
/workspace/coverage/default/6.prim_async_alert.4221425812
/workspace/coverage/default/7.prim_async_alert.942314310
/workspace/coverage/default/8.prim_async_alert.2456822000
/workspace/coverage/default/9.prim_async_alert.1454598339
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3618160768
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.557076876
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.777049757
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3755359292
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3273662755
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2218306420
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.72359689
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3577631513
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.499778875
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1455638560
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1627618981
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2684276815
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.635192427
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3661051305
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.955903358
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.302110457
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4013936599
/workspace/coverage/sync_alert/0.prim_sync_alert.2031607267
/workspace/coverage/sync_alert/1.prim_sync_alert.2238990355
/workspace/coverage/sync_alert/10.prim_sync_alert.2080321822
/workspace/coverage/sync_alert/11.prim_sync_alert.1120263201
/workspace/coverage/sync_alert/12.prim_sync_alert.2926237550
/workspace/coverage/sync_alert/13.prim_sync_alert.4126139027
/workspace/coverage/sync_alert/14.prim_sync_alert.1979692348
/workspace/coverage/sync_alert/15.prim_sync_alert.2509038534
/workspace/coverage/sync_alert/16.prim_sync_alert.1782285573
/workspace/coverage/sync_alert/17.prim_sync_alert.281880098
/workspace/coverage/sync_alert/18.prim_sync_alert.847957521
/workspace/coverage/sync_alert/19.prim_sync_alert.1978456503
/workspace/coverage/sync_alert/3.prim_sync_alert.1399051206
/workspace/coverage/sync_alert/4.prim_sync_alert.469005758
/workspace/coverage/sync_alert/6.prim_sync_alert.1223079880
/workspace/coverage/sync_alert/7.prim_sync_alert.447679687
/workspace/coverage/sync_alert/8.prim_sync_alert.3590576701
/workspace/coverage/sync_alert/9.prim_sync_alert.256673388
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3827649831
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1697128213
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2151512458
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1532584775
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1423614951
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2242973590
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1947437013
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2045340663
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2684039552
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.547613584
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1682614428
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3033788638
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.398354558
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.389901088
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.244273390
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2007072722
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2995910856
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.636370720
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2937563975
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3464081582

Total test records in report: 79

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.prim_async_alert.2465089749	Mar 05 01:08:26 PM PST 24	Mar 05 01:08:27 PM PST 24	11041222 ps
T2	/workspace/coverage/default/12.prim_async_alert.1102399374	Mar 05 01:08:17 PM PST 24	Mar 05 01:08:17 PM PST 24	10898849 ps
T3	/workspace/coverage/default/17.prim_async_alert.60214650	Mar 05 01:08:18 PM PST 24	Mar 05 01:08:19 PM PST 24	11975592 ps
T17	/workspace/coverage/default/1.prim_async_alert.2127367229	Mar 05 01:08:27 PM PST 24	Mar 05 01:08:28 PM PST 24	11028474 ps
T12	/workspace/coverage/default/16.prim_async_alert.1544179201	Mar 05 01:08:22 PM PST 24	Mar 05 01:08:23 PM PST 24	12734269 ps
T7	/workspace/coverage/default/19.prim_async_alert.3278554120	Mar 05 01:08:20 PM PST 24	Mar 05 01:08:22 PM PST 24	11188723 ps
T8	/workspace/coverage/default/14.prim_async_alert.2937717352	Mar 05 01:08:17 PM PST 24	Mar 05 01:08:17 PM PST 24	10384233 ps
T9	/workspace/coverage/default/5.prim_async_alert.1857848192	Mar 05 01:08:17 PM PST 24	Mar 05 01:08:18 PM PST 24	10675602 ps
T18	/workspace/coverage/default/15.prim_async_alert.1293725810	Mar 05 01:08:21 PM PST 24	Mar 05 01:08:23 PM PST 24	10942605 ps
T16	/workspace/coverage/default/9.prim_async_alert.1454598339	Mar 05 01:08:16 PM PST 24	Mar 05 01:08:17 PM PST 24	11527035 ps
T19	/workspace/coverage/default/7.prim_async_alert.942314310	Mar 05 01:08:16 PM PST 24	Mar 05 01:08:17 PM PST 24	11476052 ps
T13	/workspace/coverage/default/8.prim_async_alert.2456822000	Mar 05 01:08:19 PM PST 24	Mar 05 01:08:20 PM PST 24	11733282 ps
T48	/workspace/coverage/default/10.prim_async_alert.3977424932	Mar 05 01:08:16 PM PST 24	Mar 05 01:08:17 PM PST 24	11655306 ps
T20	/workspace/coverage/default/13.prim_async_alert.123845241	Mar 05 01:08:19 PM PST 24	Mar 05 01:08:19 PM PST 24	10440433 ps
T21	/workspace/coverage/default/18.prim_async_alert.3081571294	Mar 05 01:08:18 PM PST 24	Mar 05 01:08:19 PM PST 24	11370778 ps
T40	/workspace/coverage/default/0.prim_async_alert.2109262382	Mar 05 01:08:19 PM PST 24	Mar 05 01:08:20 PM PST 24	10720270 ps
T22	/workspace/coverage/default/6.prim_async_alert.4221425812	Mar 05 01:08:21 PM PST 24	Mar 05 01:08:23 PM PST 24	10407513 ps
T23	/workspace/coverage/default/11.prim_async_alert.3407123350	Mar 05 01:08:15 PM PST 24	Mar 05 01:08:16 PM PST 24	10875343 ps
T24	/workspace/coverage/default/4.prim_async_alert.636300704	Mar 05 01:08:17 PM PST 24	Mar 05 01:08:18 PM PST 24	11013731 ps
T49	/workspace/coverage/default/3.prim_async_alert.2167900080	Mar 05 01:08:19 PM PST 24	Mar 05 01:08:20 PM PST 24	11137168 ps
T14	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.557076876	Mar 05 12:17:06 PM PST 24	Mar 05 12:17:07 PM PST 24	31852930 ps
T4	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4270219499	Mar 05 12:17:22 PM PST 24	Mar 05 12:17:22 PM PST 24	29407324 ps
T41	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.955903358	Mar 05 12:17:09 PM PST 24	Mar 05 12:17:10 PM PST 24	31915016 ps
T42	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2218306420	Mar 05 12:17:32 PM PST 24	Mar 05 12:17:33 PM PST 24	30282348 ps
T43	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1455638560	Mar 05 12:17:28 PM PST 24	Mar 05 12:17:28 PM PST 24	30970234 ps
T15	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1897624967	Mar 05 12:17:17 PM PST 24	Mar 05 12:17:17 PM PST 24	30275179 ps
T44	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.635192427	Mar 05 12:17:22 PM PST 24	Mar 05 12:17:22 PM PST 24	28858366 ps
T45	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3755359292	Mar 05 12:17:53 PM PST 24	Mar 05 12:17:54 PM PST 24	32571795 ps
T46	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3273662755	Mar 05 12:17:21 PM PST 24	Mar 05 12:17:22 PM PST 24	26939308 ps
T47	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.777049757	Mar 05 12:17:13 PM PST 24	Mar 05 12:17:14 PM PST 24	30659774 ps
T50	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2684276815	Mar 05 12:17:14 PM PST 24	Mar 05 12:17:15 PM PST 24	29753369 ps
T51	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4013936599	Mar 05 12:17:09 PM PST 24	Mar 05 12:17:10 PM PST 24	31195247 ps
T52	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.302110457	Mar 05 12:17:11 PM PST 24	Mar 05 12:17:12 PM PST 24	28782754 ps
T53	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3618160768	Mar 05 12:17:18 PM PST 24	Mar 05 12:17:18 PM PST 24	30785811 ps
T54	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.499778875	Mar 05 12:17:15 PM PST 24	Mar 05 12:17:15 PM PST 24	28953589 ps
T55	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.72359689	Mar 05 12:20:40 PM PST 24	Mar 05 12:20:40 PM PST 24	27973675 ps
T56	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1627618981	Mar 05 12:17:22 PM PST 24	Mar 05 12:17:23 PM PST 24	29483873 ps
T57	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3661051305	Mar 05 12:17:18 PM PST 24	Mar 05 12:17:18 PM PST 24	29442006 ps
T58	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3577631513	Mar 05 12:17:14 PM PST 24	Mar 05 12:17:14 PM PST 24	30330638 ps
T34	/workspace/coverage/sync_alert/17.prim_sync_alert.281880098	Mar 05 01:08:20 PM PST 24	Mar 05 01:08:21 PM PST 24	9571024 ps
T25	/workspace/coverage/sync_alert/5.prim_sync_alert.3169460724	Mar 05 01:08:20 PM PST 24	Mar 05 01:08:21 PM PST 24	8962087 ps
T10	/workspace/coverage/sync_alert/2.prim_sync_alert.978156513	Mar 05 01:08:17 PM PST 24	Mar 05 01:08:18 PM PST 24	10024568 ps
T35	/workspace/coverage/sync_alert/6.prim_sync_alert.1223079880	Mar 05 01:08:21 PM PST 24	Mar 05 01:08:22 PM PST 24	9728981 ps
T26	/workspace/coverage/sync_alert/15.prim_sync_alert.2509038534	Mar 05 01:08:19 PM PST 24	Mar 05 01:08:19 PM PST 24	8995288 ps
T27	/workspace/coverage/sync_alert/19.prim_sync_alert.1978456503	Mar 05 01:08:20 PM PST 24	Mar 05 01:08:21 PM PST 24	10098375 ps
T36	/workspace/coverage/sync_alert/18.prim_sync_alert.847957521	Mar 05 01:08:20 PM PST 24	Mar 05 01:08:21 PM PST 24	9542895 ps
T37	/workspace/coverage/sync_alert/10.prim_sync_alert.2080321822	Mar 05 01:08:20 PM PST 24	Mar 05 01:08:22 PM PST 24	10381353 ps
T38	/workspace/coverage/sync_alert/1.prim_sync_alert.2238990355	Mar 05 01:08:16 PM PST 24	Mar 05 01:08:17 PM PST 24	9405074 ps
T39	/workspace/coverage/sync_alert/7.prim_sync_alert.447679687	Mar 05 01:08:17 PM PST 24	Mar 05 01:08:18 PM PST 24	8865046 ps
T59	/workspace/coverage/sync_alert/9.prim_sync_alert.256673388	Mar 05 01:08:22 PM PST 24	Mar 05 01:08:23 PM PST 24	9389406 ps
T28	/workspace/coverage/sync_alert/16.prim_sync_alert.1782285573	Mar 05 01:08:22 PM PST 24	Mar 05 01:08:24 PM PST 24	9285465 ps
T29	/workspace/coverage/sync_alert/8.prim_sync_alert.3590576701	Mar 05 01:08:28 PM PST 24	Mar 05 01:08:29 PM PST 24	8772919 ps
T60	/workspace/coverage/sync_alert/11.prim_sync_alert.1120263201	Mar 05 01:08:17 PM PST 24	Mar 05 01:08:17 PM PST 24	9621849 ps
T30	/workspace/coverage/sync_alert/13.prim_sync_alert.4126139027	Mar 05 01:08:22 PM PST 24	Mar 05 01:08:23 PM PST 24	9063295 ps
T61	/workspace/coverage/sync_alert/12.prim_sync_alert.2926237550	Mar 05 01:08:18 PM PST 24	Mar 05 01:08:19 PM PST 24	9453261 ps
T62	/workspace/coverage/sync_alert/14.prim_sync_alert.1979692348	Mar 05 01:08:19 PM PST 24	Mar 05 01:08:21 PM PST 24	8906593 ps
T31	/workspace/coverage/sync_alert/4.prim_sync_alert.469005758	Mar 05 01:08:31 PM PST 24	Mar 05 01:08:32 PM PST 24	9592509 ps
T32	/workspace/coverage/sync_alert/3.prim_sync_alert.1399051206	Mar 05 01:08:22 PM PST 24	Mar 05 01:08:23 PM PST 24	9849246 ps
T63	/workspace/coverage/sync_alert/0.prim_sync_alert.2031607267	Mar 05 01:08:19 PM PST 24	Mar 05 01:08:21 PM PST 24	9353115 ps
T64	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3464081582	Mar 05 12:17:11 PM PST 24	Mar 05 12:17:12 PM PST 24	29952348 ps
T65	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2151512458	Mar 05 12:17:22 PM PST 24	Mar 05 12:17:23 PM PST 24	27295580 ps
T5	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.244273390	Mar 05 12:17:08 PM PST 24	Mar 05 12:17:08 PM PST 24	26472087 ps
T66	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1532584775	Mar 05 12:18:05 PM PST 24	Mar 05 12:18:06 PM PST 24	26847846 ps
T67	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1697128213	Mar 05 12:17:06 PM PST 24	Mar 05 12:17:07 PM PST 24	28418285 ps
T68	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.636370720	Mar 05 12:17:11 PM PST 24	Mar 05 12:17:12 PM PST 24	27119912 ps
T33	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.547613584	Mar 05 12:22:26 PM PST 24	Mar 05 12:22:27 PM PST 24	28075089 ps
T69	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2242973590	Mar 05 12:17:30 PM PST 24	Mar 05 12:17:31 PM PST 24	27921009 ps
T70	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1423614951	Mar 05 12:17:28 PM PST 24	Mar 05 12:17:29 PM PST 24	29154817 ps
T6	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2937563975	Mar 05 12:17:22 PM PST 24	Mar 05 12:17:23 PM PST 24	27559225 ps
T71	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2045340663	Mar 05 12:17:28 PM PST 24	Mar 05 12:17:29 PM PST 24	26094547 ps
T11	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3033788638	Mar 05 12:17:22 PM PST 24	Mar 05 12:17:23 PM PST 24	26077137 ps
T72	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3827649831	Mar 05 12:17:10 PM PST 24	Mar 05 12:17:11 PM PST 24	28238559 ps
T73	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2995910856	Mar 05 12:17:10 PM PST 24	Mar 05 12:17:11 PM PST 24	27589289 ps
T74	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2007072722	Mar 05 12:17:22 PM PST 24	Mar 05 12:17:23 PM PST 24	27297804 ps
T75	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.389901088	Mar 05 12:17:06 PM PST 24	Mar 05 12:17:07 PM PST 24	28326432 ps
T76	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2684039552	Mar 05 12:17:28 PM PST 24	Mar 05 12:17:29 PM PST 24	27422715 ps
T77	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1947437013	Mar 05 12:17:15 PM PST 24	Mar 05 12:17:15 PM PST 24	27644881 ps
T78	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.398354558	Mar 05 12:17:11 PM PST 24	Mar 05 12:17:12 PM PST 24	28643499 ps
T79	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1682614428	Mar 05 12:17:28 PM PST 24	Mar 05 12:17:29 PM PST 24	27359313 ps

Test location	/workspace/coverage/default/16.prim_async_alert.1544179201
Short name	T12
Test name
Test status
Simulation time	12734269 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:22 PM PST 24
Finished	Mar 05 01:08:23 PM PST 24
Peak memory	145560 kb
Host	smart-f333e883-899e-4438-8f85-5a4a4a1a84e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544179201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1544179201
Directory	/workspace/16.prim_async_alert/latest

Test location	/workspace/coverage/sync_alert/5.prim_sync_alert.3169460724
Short name	T25
Test name
Test status
Simulation time	8962087 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:20 PM PST 24
Finished	Mar 05 01:08:21 PM PST 24
Peak memory	144900 kb
Host	smart-772c8a17-a99c-4654-9124-04c06de8e9af
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3169460724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3169460724
Directory	/workspace/5.prim_sync_alert/latest

Test location	/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.1897624967
Short name	T15
Test name
Test status
Simulation time	30275179 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:17 PM PST 24
Finished	Mar 05 12:17:17 PM PST 24
Peak memory	145764 kb
Host	smart-e72cafd5-ef5e-45d5-947b-c2bf39147e21
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1897624967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1897624967
Directory	/workspace/5.prim_async_fatal_alert/latest

Test location	/workspace/coverage/default/13.prim_async_alert.123845241
Short name	T20
Test name
Test status
Simulation time	10440433 ps
CPU time	0.4 seconds
Started	Mar 05 01:08:19 PM PST 24
Finished	Mar 05 01:08:19 PM PST 24
Peak memory	145364 kb
Host	smart-33c54110-c325-4719-b916-a4a93c41a73f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123845241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.123845241
Directory	/workspace/13.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.4270219499
Short name	T4
Test name
Test status
Simulation time	29407324 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:22 PM PST 24
Finished	Mar 05 12:17:22 PM PST 24
Peak memory	145764 kb
Host	smart-5ab82870-58c1-4776-90f6-869355533ca5
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4270219499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.4270219499
Directory	/workspace/3.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/2.prim_sync_alert.978156513
Short name	T10
Test name
Test status
Simulation time	10024568 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:17 PM PST 24
Finished	Mar 05 01:08:18 PM PST 24
Peak memory	145060 kb
Host	smart-2b9d87d0-c908-4a22-a137-9fed1a2238fb
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=978156513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.978156513
Directory	/workspace/2.prim_sync_alert/latest

Test location	/workspace/coverage/default/0.prim_async_alert.2109262382
Short name	T40
Test name
Test status
Simulation time	10720270 ps
CPU time	0.4 seconds
Started	Mar 05 01:08:19 PM PST 24
Finished	Mar 05 01:08:20 PM PST 24
Peak memory	145532 kb
Host	smart-dcab96a6-714c-4518-820b-785a598d3334
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2109262382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2109262382
Directory	/workspace/0.prim_async_alert/latest

Test location	/workspace/coverage/default/1.prim_async_alert.2127367229
Short name	T17
Test name
Test status
Simulation time	11028474 ps
CPU time	0.43 seconds
Started	Mar 05 01:08:27 PM PST 24
Finished	Mar 05 01:08:28 PM PST 24
Peak memory	145456 kb
Host	smart-6caef145-f00b-4ba9-b27e-0ab625b97715
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127367229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2127367229
Directory	/workspace/1.prim_async_alert/latest

Test location	/workspace/coverage/default/10.prim_async_alert.3977424932
Short name	T48
Test name
Test status
Simulation time	11655306 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:16 PM PST 24
Finished	Mar 05 01:08:17 PM PST 24
Peak memory	145608 kb
Host	smart-59e450ab-b278-43d9-943f-eb7cc09d8f87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977424932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3977424932
Directory	/workspace/10.prim_async_alert/latest

Test location	/workspace/coverage/default/11.prim_async_alert.3407123350
Short name	T23
Test name
Test status
Simulation time	10875343 ps
CPU time	0.41 seconds
Started	Mar 05 01:08:15 PM PST 24
Finished	Mar 05 01:08:16 PM PST 24
Peak memory	145516 kb
Host	smart-d18b7bb1-a634-444c-8847-b5064b8f6721
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407123350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3407123350
Directory	/workspace/11.prim_async_alert/latest

Test location	/workspace/coverage/default/12.prim_async_alert.1102399374
Short name	T2
Test name
Test status
Simulation time	10898849 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:17 PM PST 24
Finished	Mar 05 01:08:17 PM PST 24
Peak memory	145616 kb
Host	smart-e3db649e-1d3b-453f-af55-d093440c11cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102399374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.1102399374
Directory	/workspace/12.prim_async_alert/latest

Test location	/workspace/coverage/default/14.prim_async_alert.2937717352
Short name	T8
Test name
Test status
Simulation time	10384233 ps
CPU time	0.4 seconds
Started	Mar 05 01:08:17 PM PST 24
Finished	Mar 05 01:08:17 PM PST 24
Peak memory	145540 kb
Host	smart-5a8f85a6-9063-41d9-8cda-0985387c93b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2937717352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2937717352
Directory	/workspace/14.prim_async_alert/latest

Test location	/workspace/coverage/default/15.prim_async_alert.1293725810
Short name	T18
Test name
Test status
Simulation time	10942605 ps
CPU time	0.41 seconds
Started	Mar 05 01:08:21 PM PST 24
Finished	Mar 05 01:08:23 PM PST 24
Peak memory	145484 kb
Host	smart-32ab5208-be91-4aa5-8bc1-36f10b6df80a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293725810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.1293725810
Directory	/workspace/15.prim_async_alert/latest

Test location	/workspace/coverage/default/17.prim_async_alert.60214650
Short name	T3
Test name
Test status
Simulation time	11975592 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:18 PM PST 24
Finished	Mar 05 01:08:19 PM PST 24
Peak memory	145592 kb
Host	smart-64e47b2c-c1e6-4e0d-8b17-27c0f78ed284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60214650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.60214650
Directory	/workspace/17.prim_async_alert/latest

Test location	/workspace/coverage/default/18.prim_async_alert.3081571294
Short name	T21
Test name
Test status
Simulation time	11370778 ps
CPU time	0.4 seconds
Started	Mar 05 01:08:18 PM PST 24
Finished	Mar 05 01:08:19 PM PST 24
Peak memory	145608 kb
Host	smart-cf63da59-c285-4214-b9da-912e2edf0b02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081571294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.3081571294
Directory	/workspace/18.prim_async_alert/latest

Test location	/workspace/coverage/default/19.prim_async_alert.3278554120
Short name	T7
Test name
Test status
Simulation time	11188723 ps
CPU time	0.4 seconds
Started	Mar 05 01:08:20 PM PST 24
Finished	Mar 05 01:08:22 PM PST 24
Peak memory	145424 kb
Host	smart-fbba66f5-604f-4f20-98a6-6ad50bb9ea76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278554120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3278554120
Directory	/workspace/19.prim_async_alert/latest

Test location	/workspace/coverage/default/2.prim_async_alert.2465089749
Short name	T1
Test name
Test status
Simulation time	11041222 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:26 PM PST 24
Finished	Mar 05 01:08:27 PM PST 24
Peak memory	145596 kb
Host	smart-0133841e-bb06-4bc3-8f36-de814d94b4ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2465089749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2465089749
Directory	/workspace/2.prim_async_alert/latest

Test location	/workspace/coverage/default/3.prim_async_alert.2167900080
Short name	T49
Test name
Test status
Simulation time	11137168 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:19 PM PST 24
Finished	Mar 05 01:08:20 PM PST 24
Peak memory	145556 kb
Host	smart-111c8059-1b28-4df8-b3bf-f4ceb5b586b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167900080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.2167900080
Directory	/workspace/3.prim_async_alert/latest

Test location	/workspace/coverage/default/4.prim_async_alert.636300704
Short name	T24
Test name
Test status
Simulation time	11013731 ps
CPU time	0.41 seconds
Started	Mar 05 01:08:17 PM PST 24
Finished	Mar 05 01:08:18 PM PST 24
Peak memory	145576 kb
Host	smart-b1cc463e-9195-4901-9a39-b71563bd6b10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636300704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.636300704
Directory	/workspace/4.prim_async_alert/latest

Test location	/workspace/coverage/default/5.prim_async_alert.1857848192
Short name	T9
Test name
Test status
Simulation time	10675602 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:17 PM PST 24
Finished	Mar 05 01:08:18 PM PST 24
Peak memory	145532 kb
Host	smart-2aca3e9c-6b97-4ced-83da-1920cbd7bb2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1857848192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1857848192
Directory	/workspace/5.prim_async_alert/latest

Test location	/workspace/coverage/default/6.prim_async_alert.4221425812
Short name	T22
Test name
Test status
Simulation time	10407513 ps
CPU time	0.42 seconds
Started	Mar 05 01:08:21 PM PST 24
Finished	Mar 05 01:08:23 PM PST 24
Peak memory	145424 kb
Host	smart-d60df880-72bb-454e-bee9-9bb1cac81146
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221425812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.4221425812
Directory	/workspace/6.prim_async_alert/latest

Test location	/workspace/coverage/default/7.prim_async_alert.942314310
Short name	T19
Test name
Test status
Simulation time	11476052 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:16 PM PST 24
Finished	Mar 05 01:08:17 PM PST 24
Peak memory	145500 kb
Host	smart-58c5f035-1d69-42f4-a74d-0d0f192cde16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=942314310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.942314310
Directory	/workspace/7.prim_async_alert/latest

Test location	/workspace/coverage/default/8.prim_async_alert.2456822000
Short name	T13
Test name
Test status
Simulation time	11733282 ps
CPU time	0.4 seconds
Started	Mar 05 01:08:19 PM PST 24
Finished	Mar 05 01:08:20 PM PST 24
Peak memory	145532 kb
Host	smart-13c536c1-08a4-4078-88f9-bb6588bf5a4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456822000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2456822000
Directory	/workspace/8.prim_async_alert/latest

Test location	/workspace/coverage/default/9.prim_async_alert.1454598339
Short name	T16
Test name
Test status
Simulation time	11527035 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:16 PM PST 24
Finished	Mar 05 01:08:17 PM PST 24
Peak memory	145676 kb
Host	smart-433e04af-5d29-41e0-8548-bcfcc2c2e639
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454598339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1454598339
Directory	/workspace/9.prim_async_alert/latest

Test location	/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3618160768
Short name	T53
Test name
Test status
Simulation time	30785811 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:18 PM PST 24
Finished	Mar 05 12:17:18 PM PST 24
Peak memory	145780 kb
Host	smart-b0916978-32e5-4b08-847f-dc98c6617dfb
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3618160768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3618160768
Directory	/workspace/0.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.557076876
Short name	T14
Test name
Test status
Simulation time	31852930 ps
CPU time	0.46 seconds
Started	Mar 05 12:17:06 PM PST 24
Finished	Mar 05 12:17:07 PM PST 24
Peak memory	145792 kb
Host	smart-dd7c9436-62bb-4c39-a53f-c34e942df8c9
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=557076876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.557076876
Directory	/workspace/1.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.777049757
Short name	T47
Test name
Test status
Simulation time	30659774 ps
CPU time	0.41 seconds
Started	Mar 05 12:17:13 PM PST 24
Finished	Mar 05 12:17:14 PM PST 24
Peak memory	145464 kb
Host	smart-a4e43919-c485-4972-b168-9fa446db7c25
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=777049757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.777049757
Directory	/workspace/10.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3755359292
Short name	T45
Test name
Test status
Simulation time	32571795 ps
CPU time	0.46 seconds
Started	Mar 05 12:17:53 PM PST 24
Finished	Mar 05 12:17:54 PM PST 24
Peak memory	145844 kb
Host	smart-350a03c6-e95c-427b-933c-8468ff13c1f0
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3755359292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3755359292
Directory	/workspace/11.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.3273662755
Short name	T46
Test name
Test status
Simulation time	26939308 ps
CPU time	0.39 seconds
Started	Mar 05 12:17:21 PM PST 24
Finished	Mar 05 12:17:22 PM PST 24
Peak memory	145720 kb
Host	smart-2db2523b-61d3-4b28-91bb-90ab07236a5c
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3273662755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.3273662755
Directory	/workspace/12.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2218306420
Short name	T42
Test name
Test status
Simulation time	30282348 ps
CPU time	0.41 seconds
Started	Mar 05 12:17:32 PM PST 24
Finished	Mar 05 12:17:33 PM PST 24
Peak memory	145060 kb
Host	smart-0fa94aa1-55f0-4637-b053-a71169c51846
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2218306420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2218306420
Directory	/workspace/13.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.72359689
Short name	T55
Test name
Test status
Simulation time	27973675 ps
CPU time	0.42 seconds
Started	Mar 05 12:20:40 PM PST 24
Finished	Mar 05 12:20:40 PM PST 24
Peak memory	145768 kb
Host	smart-6e42211e-a967-414d-9459-a42aa142c8ad
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=72359689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.72359689
Directory	/workspace/14.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3577631513
Short name	T58
Test name
Test status
Simulation time	30330638 ps
CPU time	0.42 seconds
Started	Mar 05 12:17:14 PM PST 24
Finished	Mar 05 12:17:14 PM PST 24
Peak memory	145668 kb
Host	smart-cce8f7ed-1963-4ad2-adba-4159c690132d
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3577631513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3577631513
Directory	/workspace/15.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.499778875
Short name	T54
Test name
Test status
Simulation time	28953589 ps
CPU time	0.43 seconds
Started	Mar 05 12:17:15 PM PST 24
Finished	Mar 05 12:17:15 PM PST 24
Peak memory	145764 kb
Host	smart-db79b9e1-2315-40e0-b3d1-0f29cb49b326
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=499778875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.499778875
Directory	/workspace/16.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1455638560
Short name	T43
Test name
Test status
Simulation time	30970234 ps
CPU time	0.42 seconds
Started	Mar 05 12:17:28 PM PST 24
Finished	Mar 05 12:17:28 PM PST 24
Peak memory	145632 kb
Host	smart-9206041a-3122-432a-b68f-5ac355697b9c
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1455638560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1455638560
Directory	/workspace/17.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1627618981
Short name	T56
Test name
Test status
Simulation time	29483873 ps
CPU time	0.42 seconds
Started	Mar 05 12:17:22 PM PST 24
Finished	Mar 05 12:17:23 PM PST 24
Peak memory	145616 kb
Host	smart-b3bbc8ec-bab0-4893-b7f9-2cd75c9116ab
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1627618981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1627618981
Directory	/workspace/18.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.2684276815
Short name	T50
Test name
Test status
Simulation time	29753369 ps
CPU time	0.41 seconds
Started	Mar 05 12:17:14 PM PST 24
Finished	Mar 05 12:17:15 PM PST 24
Peak memory	145764 kb
Host	smart-3e1e5ef0-ec68-4e49-baff-7aec8587b24f
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2684276815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.2684276815
Directory	/workspace/19.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.635192427
Short name	T44
Test name
Test status
Simulation time	28858366 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:22 PM PST 24
Finished	Mar 05 12:17:22 PM PST 24
Peak memory	145764 kb
Host	smart-34d4ee2d-2e38-4ba0-9e66-90da12226569
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=635192427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.635192427
Directory	/workspace/2.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3661051305
Short name	T57
Test name
Test status
Simulation time	29442006 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:18 PM PST 24
Finished	Mar 05 12:17:18 PM PST 24
Peak memory	145780 kb
Host	smart-9a6aae9c-5570-44c0-8b2c-4303247c658c
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3661051305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3661051305
Directory	/workspace/6.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.955903358
Short name	T41
Test name
Test status
Simulation time	31915016 ps
CPU time	0.41 seconds
Started	Mar 05 12:17:09 PM PST 24
Finished	Mar 05 12:17:10 PM PST 24
Peak memory	145724 kb
Host	smart-69ea99c3-acd3-4abc-a3ff-82641552e631
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=955903358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.955903358
Directory	/workspace/7.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.302110457
Short name	T52
Test name
Test status
Simulation time	28782754 ps
CPU time	0.52 seconds
Started	Mar 05 12:17:11 PM PST 24
Finished	Mar 05 12:17:12 PM PST 24
Peak memory	144856 kb
Host	smart-e2485c2a-5e21-4edf-aa89-a209487a89e3
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=302110457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.302110457
Directory	/workspace/8.prim_async_fatal_alert/latest

Test location	/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.4013936599
Short name	T51
Test name
Test status
Simulation time	31195247 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:09 PM PST 24
Finished	Mar 05 12:17:10 PM PST 24
Peak memory	145628 kb
Host	smart-5792e298-1bbe-4792-810b-6fee300a42b3
User	root
Command	/workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4013936599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.4013936599
Directory	/workspace/9.prim_async_fatal_alert/latest

Test location	/workspace/coverage/sync_alert/0.prim_sync_alert.2031607267
Short name	T63
Test name
Test status
Simulation time	9353115 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:19 PM PST 24
Finished	Mar 05 01:08:21 PM PST 24
Peak memory	145008 kb
Host	smart-65a6e40c-c87c-4482-a3f8-38f6bb7254c8
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2031607267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.2031607267
Directory	/workspace/0.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/1.prim_sync_alert.2238990355
Short name	T38
Test name
Test status
Simulation time	9405074 ps
CPU time	0.37 seconds
Started	Mar 05 01:08:16 PM PST 24
Finished	Mar 05 01:08:17 PM PST 24
Peak memory	145100 kb
Host	smart-b2db2880-2e3a-4dfd-a1b5-987d8ee71ca6
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2238990355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2238990355
Directory	/workspace/1.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/10.prim_sync_alert.2080321822
Short name	T37
Test name
Test status
Simulation time	10381353 ps
CPU time	0.37 seconds
Started	Mar 05 01:08:20 PM PST 24
Finished	Mar 05 01:08:22 PM PST 24
Peak memory	145024 kb
Host	smart-04940bf4-9ab2-44e2-b723-fcec0e513e4e
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2080321822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2080321822
Directory	/workspace/10.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/11.prim_sync_alert.1120263201
Short name	T60
Test name
Test status
Simulation time	9621849 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:17 PM PST 24
Finished	Mar 05 01:08:17 PM PST 24
Peak memory	144932 kb
Host	smart-c8978be6-7d63-416c-a956-1a2e914a28cc
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1120263201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.1120263201
Directory	/workspace/11.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/12.prim_sync_alert.2926237550
Short name	T61
Test name
Test status
Simulation time	9453261 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:18 PM PST 24
Finished	Mar 05 01:08:19 PM PST 24
Peak memory	145032 kb
Host	smart-215a9c29-9b69-415a-9fe9-caeeef99f175
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2926237550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2926237550
Directory	/workspace/12.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/13.prim_sync_alert.4126139027
Short name	T30
Test name
Test status
Simulation time	9063295 ps
CPU time	0.4 seconds
Started	Mar 05 01:08:22 PM PST 24
Finished	Mar 05 01:08:23 PM PST 24
Peak memory	145032 kb
Host	smart-8e46bfa7-cd3e-4787-b535-647d48f2f20f
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4126139027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.4126139027
Directory	/workspace/13.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/14.prim_sync_alert.1979692348
Short name	T62
Test name
Test status
Simulation time	8906593 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:19 PM PST 24
Finished	Mar 05 01:08:21 PM PST 24
Peak memory	145012 kb
Host	smart-7b85926d-b39d-4ed1-8b3c-225a140f40e8
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1979692348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1979692348
Directory	/workspace/14.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/15.prim_sync_alert.2509038534
Short name	T26
Test name
Test status
Simulation time	8995288 ps
CPU time	0.4 seconds
Started	Mar 05 01:08:19 PM PST 24
Finished	Mar 05 01:08:19 PM PST 24
Peak memory	145020 kb
Host	smart-214fef06-d1fb-43ec-9513-69f75b9095d4
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2509038534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2509038534
Directory	/workspace/15.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/16.prim_sync_alert.1782285573
Short name	T28
Test name
Test status
Simulation time	9285465 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:22 PM PST 24
Finished	Mar 05 01:08:24 PM PST 24
Peak memory	145088 kb
Host	smart-e0726cfc-ca6d-4b5e-9143-9c974434c299
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1782285573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1782285573
Directory	/workspace/16.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/17.prim_sync_alert.281880098
Short name	T34
Test name
Test status
Simulation time	9571024 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:20 PM PST 24
Finished	Mar 05 01:08:21 PM PST 24
Peak memory	145008 kb
Host	smart-a022e63b-c405-4460-a4f6-88c67526fa02
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=281880098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.281880098
Directory	/workspace/17.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/18.prim_sync_alert.847957521
Short name	T36
Test name
Test status
Simulation time	9542895 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:20 PM PST 24
Finished	Mar 05 01:08:21 PM PST 24
Peak memory	144940 kb
Host	smart-48d959b5-7c57-492a-b64b-93f89439fa83
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=847957521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.847957521
Directory	/workspace/18.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/19.prim_sync_alert.1978456503
Short name	T27
Test name
Test status
Simulation time	10098375 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:20 PM PST 24
Finished	Mar 05 01:08:21 PM PST 24
Peak memory	145088 kb
Host	smart-147bb756-e517-4bcd-a3ed-6bee0c902294
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1978456503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1978456503
Directory	/workspace/19.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/3.prim_sync_alert.1399051206
Short name	T32
Test name
Test status
Simulation time	9849246 ps
CPU time	0.39 seconds
Started	Mar 05 01:08:22 PM PST 24
Finished	Mar 05 01:08:23 PM PST 24
Peak memory	144940 kb
Host	smart-fb7a485a-bfb9-45c0-88e6-ae4b0f874ab7
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1399051206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1399051206
Directory	/workspace/3.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/4.prim_sync_alert.469005758
Short name	T31
Test name
Test status
Simulation time	9592509 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:31 PM PST 24
Finished	Mar 05 01:08:32 PM PST 24
Peak memory	144976 kb
Host	smart-edabacbe-3afc-4a70-bca3-8c7305067d77
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=469005758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.469005758
Directory	/workspace/4.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/6.prim_sync_alert.1223079880
Short name	T35
Test name
Test status
Simulation time	9728981 ps
CPU time	0.37 seconds
Started	Mar 05 01:08:21 PM PST 24
Finished	Mar 05 01:08:22 PM PST 24
Peak memory	145012 kb
Host	smart-3cd03520-f0f0-40db-a14f-17f956cce116
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1223079880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1223079880
Directory	/workspace/6.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/7.prim_sync_alert.447679687
Short name	T39
Test name
Test status
Simulation time	8865046 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:17 PM PST 24
Finished	Mar 05 01:08:18 PM PST 24
Peak memory	145008 kb
Host	smart-f7ed5a46-e4a4-4f9e-a903-cd6fcf1e6c5a
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=447679687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.447679687
Directory	/workspace/7.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/8.prim_sync_alert.3590576701
Short name	T29
Test name
Test status
Simulation time	8772919 ps
CPU time	0.37 seconds
Started	Mar 05 01:08:28 PM PST 24
Finished	Mar 05 01:08:29 PM PST 24
Peak memory	144900 kb
Host	smart-67c662b7-0683-45b6-b925-3564426dac27
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3590576701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3590576701
Directory	/workspace/8.prim_sync_alert/latest

Test location	/workspace/coverage/sync_alert/9.prim_sync_alert.256673388
Short name	T59
Test name
Test status
Simulation time	9389406 ps
CPU time	0.38 seconds
Started	Mar 05 01:08:22 PM PST 24
Finished	Mar 05 01:08:23 PM PST 24
Peak memory	144972 kb
Host	smart-f62f0c3d-b088-46bf-b344-7356ae794f34
User	root
Command	/workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=256673388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.256673388
Directory	/workspace/9.prim_sync_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.3827649831
Short name	T72
Test name
Test status
Simulation time	28238559 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:10 PM PST 24
Finished	Mar 05 12:17:11 PM PST 24
Peak memory	145020 kb
Host	smart-d5110926-8746-4642-8df1-80a2ad555f71
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3827649831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.3827649831
Directory	/workspace/0.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1697128213
Short name	T67
Test name
Test status
Simulation time	28418285 ps
CPU time	0.41 seconds
Started	Mar 05 12:17:06 PM PST 24
Finished	Mar 05 12:17:07 PM PST 24
Peak memory	145264 kb
Host	smart-764df2ac-457a-4a8e-907e-1f517b55888c
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1697128213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1697128213
Directory	/workspace/1.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2151512458
Short name	T65
Test name
Test status
Simulation time	27295580 ps
CPU time	0.42 seconds
Started	Mar 05 12:17:22 PM PST 24
Finished	Mar 05 12:17:23 PM PST 24
Peak memory	145120 kb
Host	smart-2597e1af-0fd8-4b4c-bbf6-cdbe4ea6575a
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2151512458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2151512458
Directory	/workspace/10.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1532584775
Short name	T66
Test name
Test status
Simulation time	26847846 ps
CPU time	0.41 seconds
Started	Mar 05 12:18:05 PM PST 24
Finished	Mar 05 12:18:06 PM PST 24
Peak memory	145136 kb
Host	smart-cf1f574e-b8e8-4094-9ca0-b3aa1acda316
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1532584775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1532584775
Directory	/workspace/11.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.1423614951
Short name	T70
Test name
Test status
Simulation time	29154817 ps
CPU time	0.43 seconds
Started	Mar 05 12:17:28 PM PST 24
Finished	Mar 05 12:17:29 PM PST 24
Peak memory	145124 kb
Host	smart-11094ebf-6147-4d03-a207-f4dc4fadc364
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1423614951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.1423614951
Directory	/workspace/12.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.2242973590
Short name	T69
Test name
Test status
Simulation time	27921009 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:30 PM PST 24
Finished	Mar 05 12:17:31 PM PST 24
Peak memory	145152 kb
Host	smart-a3c277e3-587a-4640-a1ab-a5593e5e7a60
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2242973590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.2242973590
Directory	/workspace/13.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1947437013
Short name	T77
Test name
Test status
Simulation time	27644881 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:15 PM PST 24
Finished	Mar 05 12:17:15 PM PST 24
Peak memory	145136 kb
Host	smart-ec1d1edb-f1b3-4506-8c20-4f07816c0890
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1947437013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1947437013
Directory	/workspace/14.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2045340663
Short name	T71
Test name
Test status
Simulation time	26094547 ps
CPU time	0.41 seconds
Started	Mar 05 12:17:28 PM PST 24
Finished	Mar 05 12:17:29 PM PST 24
Peak memory	145156 kb
Host	smart-073f0669-4fec-4f56-a351-faddccf28d47
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2045340663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2045340663
Directory	/workspace/15.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2684039552
Short name	T76
Test name
Test status
Simulation time	27422715 ps
CPU time	0.44 seconds
Started	Mar 05 12:17:28 PM PST 24
Finished	Mar 05 12:17:29 PM PST 24
Peak memory	145124 kb
Host	smart-6dcaa4ef-965e-46d2-b806-71ff7a67d8a4
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2684039552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2684039552
Directory	/workspace/16.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.547613584
Short name	T33
Test name
Test status
Simulation time	28075089 ps
CPU time	0.39 seconds
Started	Mar 05 12:22:26 PM PST 24
Finished	Mar 05 12:22:27 PM PST 24
Peak memory	145000 kb
Host	smart-4fca97fc-ef08-451d-af15-1fe0a95cf9ac
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=547613584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.547613584
Directory	/workspace/17.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1682614428
Short name	T79
Test name
Test status
Simulation time	27359313 ps
CPU time	0.42 seconds
Started	Mar 05 12:17:28 PM PST 24
Finished	Mar 05 12:17:29 PM PST 24
Peak memory	145020 kb
Host	smart-1bb903c1-489e-442b-8643-059f43a7481b
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1682614428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1682614428
Directory	/workspace/18.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3033788638
Short name	T11
Test name
Test status
Simulation time	26077137 ps
CPU time	0.39 seconds
Started	Mar 05 12:17:22 PM PST 24
Finished	Mar 05 12:17:23 PM PST 24
Peak memory	145152 kb
Host	smart-fa740e45-5411-43f0-8cd8-3236eab57974
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3033788638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3033788638
Directory	/workspace/19.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.398354558
Short name	T78
Test name
Test status
Simulation time	28643499 ps
CPU time	0.49 seconds
Started	Mar 05 12:17:11 PM PST 24
Finished	Mar 05 12:17:12 PM PST 24
Peak memory	143564 kb
Host	smart-16cd864f-868c-4550-8746-7e3d5d7a4071
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=398354558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.398354558
Directory	/workspace/2.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.389901088
Short name	T75
Test name
Test status
Simulation time	28326432 ps
CPU time	0.45 seconds
Started	Mar 05 12:17:06 PM PST 24
Finished	Mar 05 12:17:07 PM PST 24
Peak memory	145244 kb
Host	smart-6fa87412-0bb7-4f7f-9ed7-bfe1bf2cbc65
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=389901088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.389901088
Directory	/workspace/3.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.244273390
Short name	T5
Test name
Test status
Simulation time	26472087 ps
CPU time	0.38 seconds
Started	Mar 05 12:17:08 PM PST 24
Finished	Mar 05 12:17:08 PM PST 24
Peak memory	145020 kb
Host	smart-80bd31d5-9178-48fe-a3d1-516c223d3707
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=244273390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.244273390
Directory	/workspace/4.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.2007072722
Short name	T74
Test name
Test status
Simulation time	27297804 ps
CPU time	0.39 seconds
Started	Mar 05 12:17:22 PM PST 24
Finished	Mar 05 12:17:23 PM PST 24
Peak memory	145120 kb
Host	smart-b3df2cae-f361-4b02-aff0-ff504e7c10bc
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2007072722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.2007072722
Directory	/workspace/5.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2995910856
Short name	T73
Test name
Test status
Simulation time	27589289 ps
CPU time	0.4 seconds
Started	Mar 05 12:17:10 PM PST 24
Finished	Mar 05 12:17:11 PM PST 24
Peak memory	145132 kb
Host	smart-8fd703e4-3954-4dcc-80e2-1d1abbf23e26
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2995910856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2995910856
Directory	/workspace/6.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.636370720
Short name	T68
Test name
Test status
Simulation time	27119912 ps
CPU time	0.48 seconds
Started	Mar 05 12:17:11 PM PST 24
Finished	Mar 05 12:17:12 PM PST 24
Peak memory	143376 kb
Host	smart-b71f30dd-1cf1-4fcd-82be-8ec9df4e5b81
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=636370720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.636370720
Directory	/workspace/7.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2937563975
Short name	T6
Test name
Test status
Simulation time	27559225 ps
CPU time	0.42 seconds
Started	Mar 05 12:17:22 PM PST 24
Finished	Mar 05 12:17:23 PM PST 24
Peak memory	145120 kb
Host	smart-753f5991-2b80-400f-a593-701979b7f7b5
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2937563975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2937563975
Directory	/workspace/8.prim_sync_fatal_alert/latest

Test location	/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3464081582
Short name	T64
Test name
Test status
Simulation time	29952348 ps
CPU time	0.49 seconds
Started	Mar 05 12:17:11 PM PST 24
Finished	Mar 05 12:17:12 PM PST 24
Peak memory	143632 kb
Host	smart-302868de-88db-431c-b7d5-b5ece61b48c6
User	root
Command	/workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3464081582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3464081582
Directory	/workspace/9.prim_sync_fatal_alert/latest