Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T9,T4,T10

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T11,T12,T6	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T6,T13
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T14,T15,T16
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T11,T17,T18

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	153916	115960	0	160
AlertKnownO_A	154636	117672	0	0
InBandInitRequest_A	154636	4171	0	0
InBandInitSequence_A	154636	418	0	0
InitReq_A	154636	775	0	0
IntegFailKnownO_A	154636	117672	0	0
NoSpuriousAlertsDuringInit_A	154636	16546	0	0
NoSpuriousPingOksDuringInit_A	154636	16144	0	0
PingDiffOk_A	153738	116774	0	0
PingOkBypassDuringInit_A	154636	40	0	40
PingOkKnownO_A	154636	117672	0	0
PingPKnownO_A	154636	117672	0	0
PingPending_A	154636	838	0	120
PingRequest0_A	154636	0	0	80
PingResponse0_A	154636	772	0	0
gen_async_assert.Alert_A	82099	1374	0	0
gen_async_assert.PingResponse1_A	82099	312	0	0
gen_async_assert.SigInt_A	82099	247	0	93
gen_sync_assert.Alert_A	72537	3038	0	0
gen_sync_assert.PingResponse1_A	72537	353	0	0
gen_sync_assert.SigInt_A	72537	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153916	115960	0	160
T1	1057	957	0	2
T2	1061	998	0	2
T3	1119	1061	0	2
T7	1098	1037	0	2
T8	1048	976	0	2
T11	1206	1049	0	2
T12	1203	1011	0	2
T14	1020	958	0	2
T19	1039	984	0	2
T20	1120	1034	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	117672	0	0
T1	1073	975	0	0
T2	1076	1015	0	0
T3	1134	1078	0	0
T7	1113	1054	0	0
T8	1064	994	0	0
T11	1221	1068	0	0
T12	1217	1029	0	0
T14	1035	975	0	0
T19	1053	1000	0	0
T20	1134	1050	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	4171	0	0
T1	1073	41	0	0
T2	1076	60	0	0
T3	1134	72	0	0
T7	1113	73	0	0
T8	1064	54	0	0
T11	1221	44	0	0
T12	1217	35	0	0
T14	1035	41	0	0
T19	1053	44	0	0
T20	1134	65	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	418	0	0
T1	1073	1	0	0
T2	1076	4	0	0
T3	1134	2	0	0
T7	1113	4	0	0
T8	1064	3	0	0
T11	1221	1	0	0
T12	1217	1	0	0
T14	1035	2	0	0
T19	1053	1	0	0
T20	1134	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	775	0	0
T1	1073	7	0	0
T2	1076	9	0	0
T3	1134	11	0	0
T7	1113	11	0	0
T8	1064	9	0	0
T11	1221	10	0	0
T12	1217	6	0	0
T14	1035	6	0	0
T19	1053	9	0	0
T20	1134	11	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	117672	0	0
T1	1073	975	0	0
T2	1076	1015	0	0
T3	1134	1078	0	0
T7	1113	1054	0	0
T8	1064	994	0	0
T11	1221	1068	0	0
T12	1217	1029	0	0
T14	1035	975	0	0
T19	1053	1000	0	0
T20	1134	1050	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	16546	0	0
T1	1073	142	0	0
T2	1076	188	0	0
T3	1134	220	0	0
T7	1113	218	0	0
T8	1064	178	0	0
T11	1221	212	0	0
T12	1217	147	0	0
T14	1035	133	0	0
T19	1053	179	0	0
T20	1134	215	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	16144	0	0
T1	1073	120	0	0
T2	1076	182	0	0
T3	1134	216	0	0
T7	1113	204	0	0
T8	1064	161	0	0
T11	1221	210	0	0
T12	1217	147	0	0
T14	1035	131	0	0
T19	1053	177	0	0
T20	1134	213	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153738	116774	0	0
T1	1055	957	0	0
T2	1059	998	0	0
T3	1120	1064	0	0
T7	1098	1039	0	0
T8	1047	977	0	0
T11	1202	1049	0	0
T12	1200	1012	0	0
T14	1018	958	0	0
T19	1037	984	0	0
T20	1118	1034	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	40	0	40
T1	0	0	0	1
T3	1134	2	0	0
T5	1073	0	0	0
T6	1276	0	0	0
T7	1113	3	0	0
T8	1064	1	0	0
T11	1221	0	0	0
T12	1217	0	0	0
T13	0	0	0	1
T14	1035	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	1053	2	0	0
T20	1134	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	117672	0	0
T1	1073	975	0	0
T2	1076	1015	0	0
T3	1134	1078	0	0
T7	1113	1054	0	0
T8	1064	994	0	0
T11	1221	1068	0	0
T12	1217	1029	0	0
T14	1035	975	0	0
T19	1053	1000	0	0
T20	1134	1050	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	117672	0	0
T1	1073	975	0	0
T2	1076	1015	0	0
T3	1134	1078	0	0
T7	1113	1054	0	0
T8	1064	994	0	0
T11	1221	1068	0	0
T12	1217	1029	0	0
T14	1035	975	0	0
T19	1053	1000	0	0
T20	1134	1050	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	838	0	120
T1	1073	11	0	1
T2	1076	11	0	1
T3	1134	11	0	1
T7	1113	11	0	1
T8	1064	11	0	1
T11	1221	11	0	1
T12	1217	11	0	1
T14	1035	11	0	1
T19	1053	11	0	1
T20	1134	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	0	0	80

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154636	772	0	0
T1	1073	9	0	0
T2	1076	10	0	0
T3	1134	10	0	0
T7	1113	10	0	0
T8	1064	10	0	0
T11	1221	10	0	0
T12	1217	10	0	0
T14	1035	10	0	0
T19	1053	10	0	0
T20	1134	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82099	1374	0	0
T1	1073	10	0	0
T2	1076	8	0	0
T3	1134	9	0	0
T7	1113	9	0	0
T8	1064	8	0	0
T11	1221	6	0	0
T12	1217	10	0	0
T14	1035	8	0	0
T19	1053	7	0	0
T20	1134	4	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82099	312	0	0
T1	1073	8	0	0
T2	1076	7	0	0
T3	1134	7	0	0
T7	1113	6	0	0
T8	1064	8	0	0
T11	1221	9	0	0
T12	1217	10	0	0
T14	1035	9	0	0
T19	1053	8	0	0
T20	1134	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82099	247	0	93
T1	1073	6	0	3
T2	1076	8	0	2
T3	1134	6	0	2
T7	1113	5	0	2
T8	1064	7	0	2
T11	1221	5	0	3
T12	1217	7	0	2
T14	1035	6	0	3
T19	1053	5	0	2
T20	1134	6	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72537	3038	0	0
T25	1016	8	0	0
T26	957	8	0	0
T27	765	12	0	0
T33	994	11	0	0
T34	952	9	0	0
T35	1096	8	0	0
T36	913	8	0	0
T37	841	10	0	0
T38	914	10	0	0
T39	993	7	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72537	353	0	0
T25	1016	8	0	0
T26	957	7	0	0
T27	765	7	0	0
T33	994	10	0	0
T34	952	8	0	0
T35	1096	10	0	0
T36	913	8	0	0
T37	841	9	0	0
T38	914	9	0	0
T39	993	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72537	40	0	0
T25	1016	1	0	0
T26	957	1	0	0
T27	765	1	0	0
T33	994	1	0	0
T34	952	1	0	0
T35	1096	1	0	0
T36	913	1	0	0
T37	841	1	0	0
T38	914	1	0	0
T39	993	1	0	0