Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T10,T6	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T2,T3,T11
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T6,T12,T13
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T14,T15,T16
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T3,T17,T18

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	148098	111634	0	154
AlertKnownO_A	148755	113240	0	0
InBandInitRequest_A	148755	4205	0	0
InBandInitSequence_A	148755	445	0	0
InitReq_A	148755	758	0	0
IntegFailKnownO_A	148755	113240	0	0
NoSpuriousAlertsDuringInit_A	148755	15881	0	0
NoSpuriousPingOksDuringInit_A	148755	15602	0	0
PingDiffOk_A	147899	112384	0	0
PingOkBypassDuringInit_A	148755	44	0	40
PingOkKnownO_A	148755	113240	0	0
PingPKnownO_A	148755	113240	0	0
PingPending_A	148755	807	0	117
PingRequest0_A	148755	0	0	77
PingResponse0_A	148755	751	0	0
gen_async_assert.Alert_A	75650	1241	0	0
gen_async_assert.PingResponse1_A	75650	307	0	0
gen_async_assert.SigInt_A	75650	235	0	90
gen_sync_assert.Alert_A	73105	3050	0	0
gen_sync_assert.PingResponse1_A	73105	351	0	0
gen_sync_assert.SigInt_A	73105	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148098	111634	0	154
T1	1014	943	0	2
T2	1075	1012	0	2
T3	1235	1049	0	2
T5	1049	990	0	2
T6	1238	1055	0	2
T7	1141	1040	0	2
T10	1119	976	0	2
T11	1059	1003	0	2
T12	1134	1000	0	2
T19	1144	1056	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	113240	0	0
T1	1029	960	0	0
T2	1091	1030	0	0
T3	1249	1067	0	0
T5	1063	1006	0	0
T6	1253	1074	0	0
T7	1156	1057	0	0
T10	1132	993	0	0
T11	1073	1019	0	0
T12	1149	1019	0	0
T19	1158	1072	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	4205	0	0
T1	1029	27	0	0
T2	1091	49	0	0
T3	1249	50	0	0
T5	1063	28	0	0
T6	1253	76	0	0
T7	1156	72	0	0
T10	1132	54	0	0
T11	1073	49	0	0
T12	1149	51	0	0
T19	1158	61	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	445	0	0
T1	1029	2	0	0
T2	1091	1	0	0
T3	1249	1	0	0
T5	1063	2	0	0
T6	1253	2	0	0
T7	1156	3	0	0
T10	1132	3	0	0
T11	1073	1	0	0
T12	1149	1	0	0
T19	1158	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	758	0	0
T1	1029	4	0	0
T2	1091	9	0	0
T3	1249	9	0	0
T5	1063	8	0	0
T6	1253	13	0	0
T7	1156	11	0	0
T10	1132	8	0	0
T11	1073	10	0	0
T12	1149	10	0	0
T19	1158	10	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	113240	0	0
T1	1029	960	0	0
T2	1091	1030	0	0
T3	1249	1067	0	0
T5	1063	1006	0	0
T6	1253	1074	0	0
T7	1156	1057	0	0
T10	1132	993	0	0
T11	1073	1019	0	0
T12	1149	1019	0	0
T19	1158	1072	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	15881	0	0
T1	1029	89	0	0
T2	1091	177	0	0
T3	1249	198	0	0
T5	1063	164	0	0
T6	1253	260	0	0
T7	1156	224	0	0
T10	1132	179	0	0
T11	1073	199	0	0
T12	1149	215	0	0
T19	1158	199	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	15602	0	0
T1	1029	89	0	0
T2	1091	175	0	0
T3	1249	197	0	0
T5	1063	162	0	0
T6	1253	257	0	0
T7	1156	213	0	0
T10	1132	177	0	0
T11	1073	193	0	0
T12	1149	207	0	0
T19	1158	196	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147899	112384	0	0
T1	1013	944	0	0
T2	1076	1015	0	0
T3	1235	1053	0	0
T5	1048	991	0	0
T6	1238	1059	0	0
T7	1138	1039	0	0
T10	1118	979	0	0
T11	1058	1004	0	0
T12	1133	1003	0	0
T19	1141	1055	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	44	0	40
T5	1063	0	0	0
T6	1253	2	0	0
T7	1156	1	0	0
T10	1132	2	0	0
T12	1149	1	0	0
T14	0	1	0	0
T17	1165	0	0	0
T18	0	1	0	0
T19	1158	1	0	0
T20	1110	2	0	0
T21	1259	1	0	0
T22	0	1	0	0
T23	1101	0	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	113240	0	0
T1	1029	960	0	0
T2	1091	1030	0	0
T3	1249	1067	0	0
T5	1063	1006	0	0
T6	1253	1074	0	0
T7	1156	1057	0	0
T10	1132	993	0	0
T11	1073	1019	0	0
T12	1149	1019	0	0
T19	1158	1072	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	113240	0	0
T1	1029	960	0	0
T2	1091	1030	0	0
T3	1249	1067	0	0
T5	1063	1006	0	0
T6	1253	1074	0	0
T7	1156	1057	0	0
T10	1132	993	0	0
T11	1073	1019	0	0
T12	1149	1019	0	0
T19	1158	1072	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	807	0	117
T1	1029	11	0	1
T2	1091	11	0	1
T3	1249	11	0	1
T5	1063	11	0	1
T6	1253	11	0	1
T7	1156	11	0	1
T10	1132	11	0	1
T11	1073	11	0	1
T12	1149	11	0	1
T19	1158	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	0	0	77

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148755	751	0	0
T1	1029	10	0	0
T2	1091	10	0	0
T3	1249	9	0	0
T5	1063	9	0	0
T6	1253	9	0	0
T7	1156	10	0	0
T10	1132	10	0	0
T11	1073	10	0	0
T12	1149	9	0	0
T19	1158	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75650	1241	0	0
T1	1029	8	0	0
T2	1091	7	0	0
T3	1249	10	0	0
T5	1063	8	0	0
T6	1253	6	0	0
T7	1156	5	0	0
T10	1132	9	0	0
T11	1073	8	0	0
T12	1149	9	0	0
T19	1158	9	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75650	307	0	0
T1	1029	10	0	0
T2	1091	9	0	0
T3	1249	9	0	0
T5	1063	9	0	0
T6	1253	7	0	0
T7	1156	9	0	0
T10	1132	8	0	0
T11	1073	7	0	0
T12	1149	5	0	0
T19	1158	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75650	235	0	90
T1	1029	6	0	3
T2	1091	6	0	3
T3	1249	8	0	3
T5	1063	5	0	2
T6	1253	6	0	3
T7	1156	6	0	3
T10	1132	5	0	2
T11	1073	7	0	3
T12	1149	8	0	3
T19	1158	7	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105	3050	0	0
T24	902	9	0	0
T25	931	9	0	0
T26	1015	12	0	0
T27	883	8	0	0
T28	937	9	0	0
T29	870	12	0	0
T34	973	10	0	0
T35	897	12	0	0
T36	920	11	0	0
T37	962	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105	351	0	0
T24	902	7	0	0
T25	931	7	0	0
T26	1015	8	0	0
T27	883	9	0	0
T28	937	8	0	0
T29	870	9	0	0
T34	973	9	0	0
T35	897	10	0	0
T36	920	9	0	0
T37	962	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105	40	0	0
T24	902	1	0	0
T25	931	1	0	0
T26	1015	1	0	0
T27	883	1	0	0
T28	937	1	0	0
T29	870	1	0	0
T34	973	1	0	0
T35	897	1	0	0
T36	920	1	0	0
T37	962	1	0	0