Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.08 88.08 100.00 100.00 93.75 93.75 100.00 100.00 71.43 71.43 95.83 95.83 67.44 67.44 /workspace/coverage/default/4.prim_async_alert.1644485346
91.55 3.48 100.00 0.00 95.83 2.08 100.00 0.00 78.57 7.14 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/3.prim_sync_alert.3722912333
93.31 1.76 100.00 0.00 95.83 0.00 100.00 0.00 82.14 3.57 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.987974816
94.85 1.54 100.00 0.00 97.92 2.08 100.00 0.00 89.29 7.14 95.83 0.00 86.05 0.00 /workspace/coverage/default/14.prim_async_alert.2171447454
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1590620840

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.1573811701
/workspace/coverage/default/1.prim_async_alert.2610227670
/workspace/coverage/default/10.prim_async_alert.3301333024
/workspace/coverage/default/11.prim_async_alert.3381097585
/workspace/coverage/default/12.prim_async_alert.599439909
/workspace/coverage/default/13.prim_async_alert.1845049517
/workspace/coverage/default/15.prim_async_alert.383054206
/workspace/coverage/default/16.prim_async_alert.3987753285
/workspace/coverage/default/17.prim_async_alert.4292075735
/workspace/coverage/default/18.prim_async_alert.1785111120
/workspace/coverage/default/19.prim_async_alert.3144985939
/workspace/coverage/default/2.prim_async_alert.2337902450
/workspace/coverage/default/3.prim_async_alert.3454670446
/workspace/coverage/default/5.prim_async_alert.3625406653
/workspace/coverage/default/6.prim_async_alert.2664568239
/workspace/coverage/default/7.prim_async_alert.3010408215
/workspace/coverage/default/8.prim_async_alert.1340522785
/workspace/coverage/default/9.prim_async_alert.3516722689
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.780494894
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2373979181
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3423556560
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2384067875
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4014421434
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.766090666
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.67278045
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3413235949
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2267468973
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3168540595
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.348849025
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2535762503
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2677460000
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.671410536
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3061502825
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2530466430
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2992924515
/workspace/coverage/sync_alert/0.prim_sync_alert.3340679921
/workspace/coverage/sync_alert/1.prim_sync_alert.3519433063
/workspace/coverage/sync_alert/10.prim_sync_alert.3016680718
/workspace/coverage/sync_alert/11.prim_sync_alert.3858501931
/workspace/coverage/sync_alert/12.prim_sync_alert.2827078676
/workspace/coverage/sync_alert/13.prim_sync_alert.3532695630
/workspace/coverage/sync_alert/14.prim_sync_alert.2322556951
/workspace/coverage/sync_alert/15.prim_sync_alert.689875933
/workspace/coverage/sync_alert/16.prim_sync_alert.1071712122
/workspace/coverage/sync_alert/17.prim_sync_alert.1688509446
/workspace/coverage/sync_alert/18.prim_sync_alert.1361603388
/workspace/coverage/sync_alert/19.prim_sync_alert.57216431
/workspace/coverage/sync_alert/2.prim_sync_alert.227866496
/workspace/coverage/sync_alert/4.prim_sync_alert.3982602164
/workspace/coverage/sync_alert/5.prim_sync_alert.2523484894
/workspace/coverage/sync_alert/6.prim_sync_alert.4226308974
/workspace/coverage/sync_alert/7.prim_sync_alert.2026479138
/workspace/coverage/sync_alert/8.prim_sync_alert.2458318489
/workspace/coverage/sync_alert/9.prim_sync_alert.601036621
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.840810678
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3114606874
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4020658496
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3550806651
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3495138775
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3914897291
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.800516181
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1709321275
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2519737353
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3505098750
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4139099531
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2904967927
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2133673953
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2392182348
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3623145901
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1766335463
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2930853205
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4115902715
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1999216063
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3463663254



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.prim_async_alert.3010408215 Mar 28 12:16:38 PM PDT 24 Mar 28 12:16:48 PM PDT 24 11532839 ps
T2 /workspace/coverage/default/12.prim_async_alert.599439909 Mar 28 12:17:08 PM PDT 24 Mar 28 12:17:09 PM PDT 24 11646208 ps
T3 /workspace/coverage/default/6.prim_async_alert.2664568239 Mar 28 12:16:28 PM PDT 24 Mar 28 12:16:29 PM PDT 24 11193932 ps
T21 /workspace/coverage/default/17.prim_async_alert.4292075735 Mar 28 12:23:18 PM PDT 24 Mar 28 12:23:19 PM PDT 24 10932150 ps
T10 /workspace/coverage/default/4.prim_async_alert.1644485346 Mar 28 12:16:29 PM PDT 24 Mar 28 12:16:30 PM PDT 24 11316463 ps
T18 /workspace/coverage/default/10.prim_async_alert.3301333024 Mar 28 12:16:28 PM PDT 24 Mar 28 12:16:29 PM PDT 24 11042774 ps
T11 /workspace/coverage/default/8.prim_async_alert.1340522785 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:47 PM PDT 24 10772286 ps
T7 /workspace/coverage/default/16.prim_async_alert.3987753285 Mar 28 12:19:21 PM PDT 24 Mar 28 12:19:21 PM PDT 24 10748063 ps
T22 /workspace/coverage/default/18.prim_async_alert.1785111120 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:48 PM PDT 24 10963238 ps
T23 /workspace/coverage/default/1.prim_async_alert.2610227670 Mar 28 12:22:21 PM PDT 24 Mar 28 12:22:22 PM PDT 24 11650893 ps
T8 /workspace/coverage/default/14.prim_async_alert.2171447454 Mar 28 12:23:18 PM PDT 24 Mar 28 12:23:19 PM PDT 24 12383487 ps
T24 /workspace/coverage/default/19.prim_async_alert.3144985939 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:48 PM PDT 24 11384213 ps
T9 /workspace/coverage/default/15.prim_async_alert.383054206 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:47 PM PDT 24 11935319 ps
T25 /workspace/coverage/default/11.prim_async_alert.3381097585 Mar 28 12:16:37 PM PDT 24 Mar 28 12:16:38 PM PDT 24 12184426 ps
T51 /workspace/coverage/default/2.prim_async_alert.2337902450 Mar 28 12:16:41 PM PDT 24 Mar 28 12:16:48 PM PDT 24 11829597 ps
T26 /workspace/coverage/default/0.prim_async_alert.1573811701 Mar 28 12:16:38 PM PDT 24 Mar 28 12:16:46 PM PDT 24 11384305 ps
T17 /workspace/coverage/default/5.prim_async_alert.3625406653 Mar 28 12:16:38 PM PDT 24 Mar 28 12:16:48 PM PDT 24 11000112 ps
T52 /workspace/coverage/default/9.prim_async_alert.3516722689 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:47 PM PDT 24 11241509 ps
T53 /workspace/coverage/default/13.prim_async_alert.1845049517 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:48 PM PDT 24 12265177 ps
T41 /workspace/coverage/default/3.prim_async_alert.3454670446 Mar 28 12:18:26 PM PDT 24 Mar 28 12:18:27 PM PDT 24 11291681 ps
T19 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.987974816 Mar 28 12:29:22 PM PDT 24 Mar 28 12:29:23 PM PDT 24 27535229 ps
T42 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2373979181 Mar 28 12:29:09 PM PDT 24 Mar 28 12:29:10 PM PDT 24 29838092 ps
T43 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.766090666 Mar 28 12:29:30 PM PDT 24 Mar 28 12:29:30 PM PDT 24 28521221 ps
T44 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.67278045 Mar 28 12:28:56 PM PDT 24 Mar 28 12:28:57 PM PDT 24 28813125 ps
T45 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.348849025 Mar 28 12:29:19 PM PDT 24 Mar 28 12:29:19 PM PDT 24 30186874 ps
T46 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2535762503 Mar 28 12:29:17 PM PDT 24 Mar 28 12:29:18 PM PDT 24 29621628 ps
T47 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2530466430 Mar 28 12:29:26 PM PDT 24 Mar 28 12:29:26 PM PDT 24 29788246 ps
T48 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.671410536 Mar 28 12:29:25 PM PDT 24 Mar 28 12:29:26 PM PDT 24 29750415 ps
T49 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2992924515 Mar 28 12:29:12 PM PDT 24 Mar 28 12:29:13 PM PDT 24 28296569 ps
T50 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2267468973 Mar 28 12:29:12 PM PDT 24 Mar 28 12:29:13 PM PDT 24 30552668 ps
T15 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2384067875 Mar 28 12:29:32 PM PDT 24 Mar 28 12:29:33 PM PDT 24 30390425 ps
T54 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4014421434 Mar 28 12:29:20 PM PDT 24 Mar 28 12:29:21 PM PDT 24 30550472 ps
T55 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3423556560 Mar 28 12:28:57 PM PDT 24 Mar 28 12:29:04 PM PDT 24 29487422 ps
T20 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3061502825 Mar 28 12:29:24 PM PDT 24 Mar 28 12:29:25 PM PDT 24 30566880 ps
T4 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1590620840 Mar 28 12:28:57 PM PDT 24 Mar 28 12:28:58 PM PDT 24 27617437 ps
T56 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.780494894 Mar 28 12:29:28 PM PDT 24 Mar 28 12:29:29 PM PDT 24 30162808 ps
T57 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2677460000 Mar 28 12:29:09 PM PDT 24 Mar 28 12:29:10 PM PDT 24 30988613 ps
T58 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3413235949 Mar 28 12:28:58 PM PDT 24 Mar 28 12:28:59 PM PDT 24 30354564 ps
T59 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3168540595 Mar 28 12:29:14 PM PDT 24 Mar 28 12:29:15 PM PDT 24 29897766 ps
T27 /workspace/coverage/sync_alert/17.prim_sync_alert.1688509446 Mar 28 12:16:38 PM PDT 24 Mar 28 12:16:48 PM PDT 24 9743422 ps
T12 /workspace/coverage/sync_alert/3.prim_sync_alert.3722912333 Mar 28 12:23:17 PM PDT 24 Mar 28 12:23:18 PM PDT 24 10543840 ps
T28 /workspace/coverage/sync_alert/4.prim_sync_alert.3982602164 Mar 28 12:17:53 PM PDT 24 Mar 28 12:17:54 PM PDT 24 9768081 ps
T29 /workspace/coverage/sync_alert/8.prim_sync_alert.2458318489 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:47 PM PDT 24 10617672 ps
T36 /workspace/coverage/sync_alert/2.prim_sync_alert.227866496 Mar 28 12:16:36 PM PDT 24 Mar 28 12:16:38 PM PDT 24 9871395 ps
T37 /workspace/coverage/sync_alert/14.prim_sync_alert.2322556951 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:48 PM PDT 24 8668032 ps
T38 /workspace/coverage/sync_alert/19.prim_sync_alert.57216431 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:48 PM PDT 24 9188310 ps
T30 /workspace/coverage/sync_alert/1.prim_sync_alert.3519433063 Mar 28 12:17:20 PM PDT 24 Mar 28 12:17:20 PM PDT 24 9415135 ps
T39 /workspace/coverage/sync_alert/12.prim_sync_alert.2827078676 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:47 PM PDT 24 7980988 ps
T40 /workspace/coverage/sync_alert/15.prim_sync_alert.689875933 Mar 28 12:16:28 PM PDT 24 Mar 28 12:16:29 PM PDT 24 9833586 ps
T60 /workspace/coverage/sync_alert/6.prim_sync_alert.4226308974 Mar 28 12:16:41 PM PDT 24 Mar 28 12:16:48 PM PDT 24 8729157 ps
T61 /workspace/coverage/sync_alert/7.prim_sync_alert.2026479138 Mar 28 12:20:07 PM PDT 24 Mar 28 12:20:08 PM PDT 24 10083228 ps
T31 /workspace/coverage/sync_alert/11.prim_sync_alert.3858501931 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:48 PM PDT 24 10024850 ps
T62 /workspace/coverage/sync_alert/0.prim_sync_alert.3340679921 Mar 28 12:23:13 PM PDT 24 Mar 28 12:23:14 PM PDT 24 9946392 ps
T16 /workspace/coverage/sync_alert/18.prim_sync_alert.1361603388 Mar 28 12:18:17 PM PDT 24 Mar 28 12:18:17 PM PDT 24 10673003 ps
T63 /workspace/coverage/sync_alert/16.prim_sync_alert.1071712122 Mar 28 12:18:17 PM PDT 24 Mar 28 12:18:18 PM PDT 24 10298903 ps
T13 /workspace/coverage/sync_alert/13.prim_sync_alert.3532695630 Mar 28 12:20:35 PM PDT 24 Mar 28 12:20:35 PM PDT 24 9309816 ps
T64 /workspace/coverage/sync_alert/10.prim_sync_alert.3016680718 Mar 28 12:16:38 PM PDT 24 Mar 28 12:16:48 PM PDT 24 8780997 ps
T32 /workspace/coverage/sync_alert/5.prim_sync_alert.2523484894 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:48 PM PDT 24 8445272 ps
T65 /workspace/coverage/sync_alert/9.prim_sync_alert.601036621 Mar 28 12:16:40 PM PDT 24 Mar 28 12:16:48 PM PDT 24 9271087 ps
T66 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1766335463 Mar 28 12:19:33 PM PDT 24 Mar 28 12:19:33 PM PDT 24 28820973 ps
T5 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2392182348 Mar 28 12:16:41 PM PDT 24 Mar 28 12:16:48 PM PDT 24 27469483 ps
T67 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2519737353 Mar 28 12:18:22 PM PDT 24 Mar 28 12:18:22 PM PDT 24 27607787 ps
T68 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3914897291 Mar 28 12:22:51 PM PDT 24 Mar 28 12:22:52 PM PDT 24 28475824 ps
T6 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1709321275 Mar 28 12:17:53 PM PDT 24 Mar 28 12:17:54 PM PDT 24 25239816 ps
T14 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3463663254 Mar 28 12:17:43 PM PDT 24 Mar 28 12:17:44 PM PDT 24 27325626 ps
T69 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2930853205 Mar 28 12:22:32 PM PDT 24 Mar 28 12:22:33 PM PDT 24 28352286 ps
T33 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2133673953 Mar 28 12:16:39 PM PDT 24 Mar 28 12:16:47 PM PDT 24 28755330 ps
T34 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3114606874 Mar 28 12:23:18 PM PDT 24 Mar 28 12:23:19 PM PDT 24 27673922 ps
T70 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4020658496 Mar 28 12:23:13 PM PDT 24 Mar 28 12:23:14 PM PDT 24 27215531 ps
T35 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.800516181 Mar 28 12:20:03 PM PDT 24 Mar 28 12:20:04 PM PDT 24 30533716 ps
T71 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2904967927 Mar 28 12:20:07 PM PDT 24 Mar 28 12:20:08 PM PDT 24 27265612 ps
T72 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3623145901 Mar 28 12:22:21 PM PDT 24 Mar 28 12:22:22 PM PDT 24 27998989 ps
T73 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4115902715 Mar 28 12:22:51 PM PDT 24 Mar 28 12:22:52 PM PDT 24 27827198 ps
T74 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1999216063 Mar 28 12:19:30 PM PDT 24 Mar 28 12:19:31 PM PDT 24 28710885 ps
T75 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4139099531 Mar 28 12:18:29 PM PDT 24 Mar 28 12:18:30 PM PDT 24 27776466 ps
T76 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.840810678 Mar 28 12:21:07 PM PDT 24 Mar 28 12:21:07 PM PDT 24 26222877 ps
T77 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3495138775 Mar 28 12:22:51 PM PDT 24 Mar 28 12:22:52 PM PDT 24 26489163 ps
T78 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3505098750 Mar 28 12:17:39 PM PDT 24 Mar 28 12:17:40 PM PDT 24 26666953 ps
T79 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3550806651 Mar 28 12:23:14 PM PDT 24 Mar 28 12:23:14 PM PDT 24 27568102 ps

Test location /workspace/coverage/default/4.prim_async_alert.1644485346
Short name T10
Test name
Test status
Simulation time 11316463 ps
CPU time 0.42 seconds
Started Mar 28 12:16:29 PM PDT 24
Finished Mar 28 12:16:30 PM PDT 24
Peak memory 145152 kb
Host smart-ca769041-8b0a-477c-9350-da32db52def4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644485346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1644485346
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.3722912333
Short name T12
Test name
Test status
Simulation time 10543840 ps
CPU time 0.42 seconds
Started Mar 28 12:23:17 PM PDT 24
Finished Mar 28 12:23:18 PM PDT 24
Peak memory 144800 kb
Host smart-311e9738-b9f9-4b23-8b5a-cb835f1de670
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3722912333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3722912333
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.987974816
Short name T19
Test name
Test status
Simulation time 27535229 ps
CPU time 0.39 seconds
Started Mar 28 12:29:22 PM PDT 24
Finished Mar 28 12:29:23 PM PDT 24
Peak memory 145532 kb
Host smart-844791b7-a7bd-4d78-868f-93510f021e78
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=987974816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.987974816
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.2171447454
Short name T8
Test name
Test status
Simulation time 12383487 ps
CPU time 0.42 seconds
Started Mar 28 12:23:18 PM PDT 24
Finished Mar 28 12:23:19 PM PDT 24
Peak memory 145316 kb
Host smart-bd09b2f2-5a33-4be9-9583-f086b1853c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171447454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2171447454
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1590620840
Short name T4
Test name
Test status
Simulation time 27617437 ps
CPU time 0.44 seconds
Started Mar 28 12:28:57 PM PDT 24
Finished Mar 28 12:28:58 PM PDT 24
Peak memory 144196 kb
Host smart-c8c058b1-0705-4662-b124-836f9b6f0331
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1590620840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1590620840
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.1573811701
Short name T26
Test name
Test status
Simulation time 11384305 ps
CPU time 0.4 seconds
Started Mar 28 12:16:38 PM PDT 24
Finished Mar 28 12:16:46 PM PDT 24
Peak memory 145712 kb
Host smart-38124b7b-a339-4cb2-9663-541e5229b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573811701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1573811701
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.2610227670
Short name T23
Test name
Test status
Simulation time 11650893 ps
CPU time 0.38 seconds
Started Mar 28 12:22:21 PM PDT 24
Finished Mar 28 12:22:22 PM PDT 24
Peak memory 144772 kb
Host smart-4c5f8de9-9bae-4c55-89e5-41ce1ea04b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610227670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.2610227670
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3301333024
Short name T18
Test name
Test status
Simulation time 11042774 ps
CPU time 0.39 seconds
Started Mar 28 12:16:28 PM PDT 24
Finished Mar 28 12:16:29 PM PDT 24
Peak memory 145800 kb
Host smart-d9c62bbb-0988-45ab-b949-3d4822e56eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301333024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3301333024
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3381097585
Short name T25
Test name
Test status
Simulation time 12184426 ps
CPU time 0.4 seconds
Started Mar 28 12:16:37 PM PDT 24
Finished Mar 28 12:16:38 PM PDT 24
Peak memory 145580 kb
Host smart-bcd9ab98-901a-4100-9b04-81d9b58827aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381097585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3381097585
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.599439909
Short name T2
Test name
Test status
Simulation time 11646208 ps
CPU time 0.42 seconds
Started Mar 28 12:17:08 PM PDT 24
Finished Mar 28 12:17:09 PM PDT 24
Peak memory 145220 kb
Host smart-fa4c74d3-2eaa-4c98-90e1-f8387a634d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599439909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.599439909
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1845049517
Short name T53
Test name
Test status
Simulation time 12265177 ps
CPU time 0.39 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145660 kb
Host smart-258a2726-35a3-428a-9e08-e48b3c9908b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845049517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1845049517
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.383054206
Short name T9
Test name
Test status
Simulation time 11935319 ps
CPU time 0.38 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:47 PM PDT 24
Peak memory 145560 kb
Host smart-ea3df1e3-1c20-4d44-9e19-7b6c2527486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383054206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.383054206
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3987753285
Short name T7
Test name
Test status
Simulation time 10748063 ps
CPU time 0.41 seconds
Started Mar 28 12:19:21 PM PDT 24
Finished Mar 28 12:19:21 PM PDT 24
Peak memory 145604 kb
Host smart-c1dadc2b-d8cc-4835-89e7-8fa4d1e3b718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987753285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3987753285
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.4292075735
Short name T21
Test name
Test status
Simulation time 10932150 ps
CPU time 0.4 seconds
Started Mar 28 12:23:18 PM PDT 24
Finished Mar 28 12:23:19 PM PDT 24
Peak memory 145316 kb
Host smart-3c6d0015-867d-42e3-8f01-08beee6db76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292075735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.4292075735
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1785111120
Short name T22
Test name
Test status
Simulation time 10963238 ps
CPU time 0.39 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145692 kb
Host smart-2e7f5416-3202-4a04-a0ea-90de418017c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785111120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1785111120
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3144985939
Short name T24
Test name
Test status
Simulation time 11384213 ps
CPU time 0.43 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145708 kb
Host smart-1c1fb039-2cce-4de7-be8f-ed08401cf74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144985939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3144985939
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.2337902450
Short name T51
Test name
Test status
Simulation time 11829597 ps
CPU time 0.38 seconds
Started Mar 28 12:16:41 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145696 kb
Host smart-3d48e44a-8aea-4422-b857-050c868b28a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337902450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.2337902450
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.3454670446
Short name T41
Test name
Test status
Simulation time 11291681 ps
CPU time 0.41 seconds
Started Mar 28 12:18:26 PM PDT 24
Finished Mar 28 12:18:27 PM PDT 24
Peak memory 145812 kb
Host smart-32bff82d-6c6e-4302-b3c0-1323ee21d0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454670446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3454670446
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.3625406653
Short name T17
Test name
Test status
Simulation time 11000112 ps
CPU time 0.39 seconds
Started Mar 28 12:16:38 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145712 kb
Host smart-19777701-8d0a-4a66-8d71-9d359ceb936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625406653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.3625406653
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.2664568239
Short name T3
Test name
Test status
Simulation time 11193932 ps
CPU time 0.38 seconds
Started Mar 28 12:16:28 PM PDT 24
Finished Mar 28 12:16:29 PM PDT 24
Peak memory 145808 kb
Host smart-41cbf1a3-4486-4e9b-8715-1c768578f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664568239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2664568239
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.3010408215
Short name T1
Test name
Test status
Simulation time 11532839 ps
CPU time 0.41 seconds
Started Mar 28 12:16:38 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145712 kb
Host smart-2cb1b9bc-58ed-4d04-bff2-d37db7a8638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010408215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.3010408215
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.1340522785
Short name T11
Test name
Test status
Simulation time 10772286 ps
CPU time 0.38 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:47 PM PDT 24
Peak memory 145448 kb
Host smart-c4eecb85-dde5-4fbe-881b-1e8d1032bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340522785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.1340522785
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.3516722689
Short name T52
Test name
Test status
Simulation time 11241509 ps
CPU time 0.38 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:47 PM PDT 24
Peak memory 145412 kb
Host smart-9fa79309-fbda-490f-bf15-6573b8084698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516722689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.3516722689
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.780494894
Short name T56
Test name
Test status
Simulation time 30162808 ps
CPU time 0.45 seconds
Started Mar 28 12:29:28 PM PDT 24
Finished Mar 28 12:29:29 PM PDT 24
Peak memory 145896 kb
Host smart-eef2ac47-006b-4732-83cc-ccf271130424
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=780494894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.780494894
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2373979181
Short name T42
Test name
Test status
Simulation time 29838092 ps
CPU time 0.42 seconds
Started Mar 28 12:29:09 PM PDT 24
Finished Mar 28 12:29:10 PM PDT 24
Peak memory 145276 kb
Host smart-22c358aa-456a-41e5-9479-32a72d98abc5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2373979181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2373979181
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.3423556560
Short name T55
Test name
Test status
Simulation time 29487422 ps
CPU time 0.41 seconds
Started Mar 28 12:28:57 PM PDT 24
Finished Mar 28 12:29:04 PM PDT 24
Peak memory 145424 kb
Host smart-ba0ff470-3284-48ec-8bbf-228c312654af
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3423556560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.3423556560
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.2384067875
Short name T15
Test name
Test status
Simulation time 30390425 ps
CPU time 0.4 seconds
Started Mar 28 12:29:32 PM PDT 24
Finished Mar 28 12:29:33 PM PDT 24
Peak memory 145804 kb
Host smart-6a7a4371-d521-4d53-814b-c11f7a6c1bb8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2384067875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.2384067875
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.4014421434
Short name T54
Test name
Test status
Simulation time 30550472 ps
CPU time 0.44 seconds
Started Mar 28 12:29:20 PM PDT 24
Finished Mar 28 12:29:21 PM PDT 24
Peak memory 145500 kb
Host smart-bc8bd4e4-2dbd-4892-9711-3daeb0371fdf
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4014421434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.4014421434
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.766090666
Short name T43
Test name
Test status
Simulation time 28521221 ps
CPU time 0.41 seconds
Started Mar 28 12:29:30 PM PDT 24
Finished Mar 28 12:29:30 PM PDT 24
Peak memory 145532 kb
Host smart-8059cdba-94f0-443e-a17a-6ce5e0a24c13
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=766090666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.766090666
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.67278045
Short name T44
Test name
Test status
Simulation time 28813125 ps
CPU time 0.43 seconds
Started Mar 28 12:28:56 PM PDT 24
Finished Mar 28 12:28:57 PM PDT 24
Peak memory 145260 kb
Host smart-2b64925a-a340-4364-9020-7fd3f0147368
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=67278045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.67278045
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.3413235949
Short name T58
Test name
Test status
Simulation time 30354564 ps
CPU time 0.38 seconds
Started Mar 28 12:28:58 PM PDT 24
Finished Mar 28 12:28:59 PM PDT 24
Peak memory 145596 kb
Host smart-0c5b9f2a-6bfc-4834-84ac-66c459b27928
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3413235949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.3413235949
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.2267468973
Short name T50
Test name
Test status
Simulation time 30552668 ps
CPU time 0.45 seconds
Started Mar 28 12:29:12 PM PDT 24
Finished Mar 28 12:29:13 PM PDT 24
Peak memory 145252 kb
Host smart-0bebc67b-b946-47a2-984d-e7c973ab6a2b
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2267468973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.2267468973
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3168540595
Short name T59
Test name
Test status
Simulation time 29897766 ps
CPU time 0.4 seconds
Started Mar 28 12:29:14 PM PDT 24
Finished Mar 28 12:29:15 PM PDT 24
Peak memory 145628 kb
Host smart-52722e68-b962-4898-bac1-502cfcc3fe6a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3168540595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3168540595
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.348849025
Short name T45
Test name
Test status
Simulation time 30186874 ps
CPU time 0.41 seconds
Started Mar 28 12:29:19 PM PDT 24
Finished Mar 28 12:29:19 PM PDT 24
Peak memory 145764 kb
Host smart-27e0f653-1db2-48e8-81cd-030f4d626178
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=348849025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.348849025
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.2535762503
Short name T46
Test name
Test status
Simulation time 29621628 ps
CPU time 0.4 seconds
Started Mar 28 12:29:17 PM PDT 24
Finished Mar 28 12:29:18 PM PDT 24
Peak memory 145624 kb
Host smart-0e4c480d-c536-446f-ad24-6db8dd16fb47
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2535762503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.2535762503
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.2677460000
Short name T57
Test name
Test status
Simulation time 30988613 ps
CPU time 0.4 seconds
Started Mar 28 12:29:09 PM PDT 24
Finished Mar 28 12:29:10 PM PDT 24
Peak memory 145764 kb
Host smart-f39711fa-3508-4f7a-89a9-a96467418934
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2677460000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.2677460000
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.671410536
Short name T48
Test name
Test status
Simulation time 29750415 ps
CPU time 0.4 seconds
Started Mar 28 12:29:25 PM PDT 24
Finished Mar 28 12:29:26 PM PDT 24
Peak memory 145668 kb
Host smart-cbff9c16-c56f-4c7a-a499-b4da631d8037
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=671410536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.671410536
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.3061502825
Short name T20
Test name
Test status
Simulation time 30566880 ps
CPU time 0.46 seconds
Started Mar 28 12:29:24 PM PDT 24
Finished Mar 28 12:29:25 PM PDT 24
Peak memory 145240 kb
Host smart-5d2d5f22-552d-444a-9658-a2e602290b7f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3061502825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.3061502825
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.2530466430
Short name T47
Test name
Test status
Simulation time 29788246 ps
CPU time 0.41 seconds
Started Mar 28 12:29:26 PM PDT 24
Finished Mar 28 12:29:26 PM PDT 24
Peak memory 145500 kb
Host smart-9193fcab-5ead-4f1d-b1d9-5499f149b342
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2530466430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.2530466430
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2992924515
Short name T49
Test name
Test status
Simulation time 28296569 ps
CPU time 0.43 seconds
Started Mar 28 12:29:12 PM PDT 24
Finished Mar 28 12:29:13 PM PDT 24
Peak memory 145500 kb
Host smart-470e8075-f784-40d3-89ba-dffb8e2fc3f7
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2992924515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2992924515
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.3340679921
Short name T62
Test name
Test status
Simulation time 9946392 ps
CPU time 0.4 seconds
Started Mar 28 12:23:13 PM PDT 24
Finished Mar 28 12:23:14 PM PDT 24
Peak memory 143560 kb
Host smart-ce20c74e-ad54-40b9-a9b5-c68352f7183e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3340679921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3340679921
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.3519433063
Short name T30
Test name
Test status
Simulation time 9415135 ps
CPU time 0.37 seconds
Started Mar 28 12:17:20 PM PDT 24
Finished Mar 28 12:17:20 PM PDT 24
Peak memory 144860 kb
Host smart-64c26ea9-8ddf-47a9-a574-72c6009dbf3d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3519433063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.3519433063
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.3016680718
Short name T64
Test name
Test status
Simulation time 8780997 ps
CPU time 0.4 seconds
Started Mar 28 12:16:38 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145016 kb
Host smart-2262328a-4883-42f5-a9eb-f9f83fe2156b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3016680718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.3016680718
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3858501931
Short name T31
Test name
Test status
Simulation time 10024850 ps
CPU time 0.39 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145012 kb
Host smart-3953c0f6-c4a4-4606-b315-cb2b0159a8d6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3858501931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3858501931
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.2827078676
Short name T39
Test name
Test status
Simulation time 7980988 ps
CPU time 0.39 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:47 PM PDT 24
Peak memory 144644 kb
Host smart-2ba8ba37-f01e-4756-a0b7-5eee72ab87ab
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2827078676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2827078676
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.3532695630
Short name T13
Test name
Test status
Simulation time 9309816 ps
CPU time 0.37 seconds
Started Mar 28 12:20:35 PM PDT 24
Finished Mar 28 12:20:35 PM PDT 24
Peak memory 144928 kb
Host smart-c971365f-1be8-4b27-a93d-6d5d89f176f3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3532695630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.3532695630
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.2322556951
Short name T37
Test name
Test status
Simulation time 8668032 ps
CPU time 0.38 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 144940 kb
Host smart-b95ae83f-341f-4fd0-ac79-5fe77922ed11
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2322556951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.2322556951
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.689875933
Short name T40
Test name
Test status
Simulation time 9833586 ps
CPU time 0.38 seconds
Started Mar 28 12:16:28 PM PDT 24
Finished Mar 28 12:16:29 PM PDT 24
Peak memory 145128 kb
Host smart-c6932733-e7dc-4069-8b33-d36ca02ef5ad
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=689875933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.689875933
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1071712122
Short name T63
Test name
Test status
Simulation time 10298903 ps
CPU time 0.43 seconds
Started Mar 28 12:18:17 PM PDT 24
Finished Mar 28 12:18:18 PM PDT 24
Peak memory 144640 kb
Host smart-1a420fbc-43c4-4a9a-8569-1328730d128e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1071712122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1071712122
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1688509446
Short name T27
Test name
Test status
Simulation time 9743422 ps
CPU time 0.38 seconds
Started Mar 28 12:16:38 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 144928 kb
Host smart-f7e03261-69b4-4a20-b4c1-228e0dc66c17
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1688509446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1688509446
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1361603388
Short name T16
Test name
Test status
Simulation time 10673003 ps
CPU time 0.39 seconds
Started Mar 28 12:18:17 PM PDT 24
Finished Mar 28 12:18:17 PM PDT 24
Peak memory 144632 kb
Host smart-1b4018cd-ae47-4115-ab2a-b0d5664058b4
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1361603388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1361603388
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.57216431
Short name T38
Test name
Test status
Simulation time 9188310 ps
CPU time 0.38 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 144972 kb
Host smart-63b76a99-f0ac-4ddb-ab2d-6edddaa5b559
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=57216431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.57216431
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.227866496
Short name T36
Test name
Test status
Simulation time 9871395 ps
CPU time 0.45 seconds
Started Mar 28 12:16:36 PM PDT 24
Finished Mar 28 12:16:38 PM PDT 24
Peak memory 145340 kb
Host smart-592d5d48-0d2d-449d-b495-c96322488df3
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=227866496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.227866496
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3982602164
Short name T28
Test name
Test status
Simulation time 9768081 ps
CPU time 0.38 seconds
Started Mar 28 12:17:53 PM PDT 24
Finished Mar 28 12:17:54 PM PDT 24
Peak memory 144692 kb
Host smart-fb14e196-2b93-4942-b78c-d61b1888db46
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3982602164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3982602164
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.2523484894
Short name T32
Test name
Test status
Simulation time 8445272 ps
CPU time 0.39 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 144936 kb
Host smart-f4dd49bc-9861-4304-a095-76e47d3edac6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2523484894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.2523484894
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.4226308974
Short name T60
Test name
Test status
Simulation time 8729157 ps
CPU time 0.38 seconds
Started Mar 28 12:16:41 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 144964 kb
Host smart-d3cb79c7-b965-4c6a-a7fa-a56bbc6713b9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4226308974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.4226308974
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.2026479138
Short name T61
Test name
Test status
Simulation time 10083228 ps
CPU time 0.42 seconds
Started Mar 28 12:20:07 PM PDT 24
Finished Mar 28 12:20:08 PM PDT 24
Peak memory 144992 kb
Host smart-ef0f5555-b10c-4fa7-90a9-8e175f482c17
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2026479138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2026479138
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.2458318489
Short name T29
Test name
Test status
Simulation time 10617672 ps
CPU time 0.39 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:47 PM PDT 24
Peak memory 145008 kb
Host smart-5b11a0cf-d1b4-4bae-9b8a-3f3531c9dd00
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2458318489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2458318489
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.601036621
Short name T65
Test name
Test status
Simulation time 9271087 ps
CPU time 0.39 seconds
Started Mar 28 12:16:40 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 145012 kb
Host smart-668e47ec-de94-4cd4-b968-afabc9065711
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=601036621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.601036621
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.840810678
Short name T76
Test name
Test status
Simulation time 26222877 ps
CPU time 0.39 seconds
Started Mar 28 12:21:07 PM PDT 24
Finished Mar 28 12:21:07 PM PDT 24
Peak memory 144932 kb
Host smart-f853914b-c9e8-421a-89f5-c2d6e1463068
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=840810678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.840810678
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3114606874
Short name T34
Test name
Test status
Simulation time 27673922 ps
CPU time 0.43 seconds
Started Mar 28 12:23:18 PM PDT 24
Finished Mar 28 12:23:19 PM PDT 24
Peak memory 144628 kb
Host smart-ab6fa643-f24a-4d68-97b6-f53c70d6e063
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3114606874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3114606874
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.4020658496
Short name T70
Test name
Test status
Simulation time 27215531 ps
CPU time 0.43 seconds
Started Mar 28 12:23:13 PM PDT 24
Finished Mar 28 12:23:14 PM PDT 24
Peak memory 143192 kb
Host smart-c6463218-0bdf-4378-b341-07089c4161ed
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4020658496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.4020658496
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.3550806651
Short name T79
Test name
Test status
Simulation time 27568102 ps
CPU time 0.38 seconds
Started Mar 28 12:23:14 PM PDT 24
Finished Mar 28 12:23:14 PM PDT 24
Peak memory 145124 kb
Host smart-f57832df-da66-4d1d-a300-2fd9e52ba814
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3550806651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.3550806651
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.3495138775
Short name T77
Test name
Test status
Simulation time 26489163 ps
CPU time 0.39 seconds
Started Mar 28 12:22:51 PM PDT 24
Finished Mar 28 12:22:52 PM PDT 24
Peak memory 144808 kb
Host smart-0f771eff-efbb-412e-ad4e-6f90c17032de
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3495138775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.3495138775
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3914897291
Short name T68
Test name
Test status
Simulation time 28475824 ps
CPU time 0.39 seconds
Started Mar 28 12:22:51 PM PDT 24
Finished Mar 28 12:22:52 PM PDT 24
Peak memory 144748 kb
Host smart-37b52828-ffc5-4801-b65e-26f4165283ff
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3914897291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3914897291
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.800516181
Short name T35
Test name
Test status
Simulation time 30533716 ps
CPU time 0.4 seconds
Started Mar 28 12:20:03 PM PDT 24
Finished Mar 28 12:20:04 PM PDT 24
Peak memory 144884 kb
Host smart-5ea5f23d-7b9c-4455-a03f-ae4219400f3b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=800516181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.800516181
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1709321275
Short name T6
Test name
Test status
Simulation time 25239816 ps
CPU time 0.4 seconds
Started Mar 28 12:17:53 PM PDT 24
Finished Mar 28 12:17:54 PM PDT 24
Peak memory 144896 kb
Host smart-78b03d92-0940-42f9-b984-b0401e012486
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1709321275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1709321275
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.2519737353
Short name T67
Test name
Test status
Simulation time 27607787 ps
CPU time 0.39 seconds
Started Mar 28 12:18:22 PM PDT 24
Finished Mar 28 12:18:22 PM PDT 24
Peak memory 144896 kb
Host smart-04ee8b19-007c-4e56-904e-19c6979af367
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2519737353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.2519737353
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.3505098750
Short name T78
Test name
Test status
Simulation time 26666953 ps
CPU time 0.42 seconds
Started Mar 28 12:17:39 PM PDT 24
Finished Mar 28 12:17:40 PM PDT 24
Peak memory 144896 kb
Host smart-a4158a18-4573-4ca8-9a8f-12fa75eae50f
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3505098750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.3505098750
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.4139099531
Short name T75
Test name
Test status
Simulation time 27776466 ps
CPU time 0.39 seconds
Started Mar 28 12:18:29 PM PDT 24
Finished Mar 28 12:18:30 PM PDT 24
Peak memory 144976 kb
Host smart-81f476d0-8f5c-4155-898a-1858da75e9ae
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4139099531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.4139099531
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.2904967927
Short name T71
Test name
Test status
Simulation time 27265612 ps
CPU time 0.4 seconds
Started Mar 28 12:20:07 PM PDT 24
Finished Mar 28 12:20:08 PM PDT 24
Peak memory 144976 kb
Host smart-74c5f9d5-af58-4dfa-a012-fe98c9280775
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2904967927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.2904967927
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2133673953
Short name T33
Test name
Test status
Simulation time 28755330 ps
CPU time 0.38 seconds
Started Mar 28 12:16:39 PM PDT 24
Finished Mar 28 12:16:47 PM PDT 24
Peak memory 145000 kb
Host smart-5087d8f8-01f1-4991-bc3f-2a111095469e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2133673953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2133673953
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2392182348
Short name T5
Test name
Test status
Simulation time 27469483 ps
CPU time 0.45 seconds
Started Mar 28 12:16:41 PM PDT 24
Finished Mar 28 12:16:48 PM PDT 24
Peak memory 144984 kb
Host smart-7cddc383-350e-4041-b052-37bc7b6b8709
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2392182348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2392182348
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.3623145901
Short name T72
Test name
Test status
Simulation time 27998989 ps
CPU time 0.43 seconds
Started Mar 28 12:22:21 PM PDT 24
Finished Mar 28 12:22:22 PM PDT 24
Peak memory 143980 kb
Host smart-5d21b2aa-3e96-46ef-b64c-f92bb5f8c4f9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3623145901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.3623145901
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1766335463
Short name T66
Test name
Test status
Simulation time 28820973 ps
CPU time 0.4 seconds
Started Mar 28 12:19:33 PM PDT 24
Finished Mar 28 12:19:33 PM PDT 24
Peak memory 144860 kb
Host smart-07298aee-bec8-499e-8131-54881c19f79a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1766335463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1766335463
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.2930853205
Short name T69
Test name
Test status
Simulation time 28352286 ps
CPU time 0.41 seconds
Started Mar 28 12:22:32 PM PDT 24
Finished Mar 28 12:22:33 PM PDT 24
Peak memory 145340 kb
Host smart-70ac68db-73d8-42cf-a121-fc27cba8f2cb
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2930853205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2930853205
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.4115902715
Short name T73
Test name
Test status
Simulation time 27827198 ps
CPU time 0.39 seconds
Started Mar 28 12:22:51 PM PDT 24
Finished Mar 28 12:22:52 PM PDT 24
Peak memory 144728 kb
Host smart-1da5684a-1aba-43f9-a6dc-4356c7b4a750
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4115902715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.4115902715
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.1999216063
Short name T74
Test name
Test status
Simulation time 28710885 ps
CPU time 0.4 seconds
Started Mar 28 12:19:30 PM PDT 24
Finished Mar 28 12:19:31 PM PDT 24
Peak memory 145012 kb
Host smart-593b91d5-1039-4b00-b284-60b2efda0426
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1999216063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.1999216063
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3463663254
Short name T14
Test name
Test status
Simulation time 27325626 ps
CPU time 0.39 seconds
Started Mar 28 12:17:43 PM PDT 24
Finished Mar 28 12:17:44 PM PDT 24
Peak memory 144880 kb
Host smart-cf60b32b-7b48-4576-aa93-eb9822afbf36
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3463663254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3463663254
Directory /workspace/9.prim_sync_fatal_alert/latest
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