| ASSERT | PROPERTIES | SEQUENCES | |
| Total | 43 | 0 | 0 |
| Category 0 | 43 | 0 | 0 |
| ASSERT | PROPERTIES | SEQUENCES | |
| Total | 43 | 0 | 0 |
| Severity 0 | 43 | 0 | 0 |
| NUMBER | PERCENT | |
| Total Number | 43 | 100.00 |
| Uncovered | 6 | 13.95 |
| Success | 37 | 86.05 |
| Failure | 0 | 0.00 |
| Incomplete | 9 | 20.93 |
| Without Attempts | 0 | 0.00 |
| ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
| prim_alert_tb.i_alert_receiver.PingRequest0_A | 0 | 0 | 143928 | 0 | 0 | 75 | |
| prim_alert_tb.i_alert_sender.gen_recov_assert.AlertState2_A | 0 | 0 | 38002 | 0 | 0 | 0 | |
| prim_alert_tb.i_alert_sender.gen_sync_assert.InBandInitFsm_A | 0 | 0 | 72289 | 0 | 0 | 0 | |
| prim_alert_tb.i_alert_sender.gen_sync_assert.InBandInitPing_A | 0 | 0 | 72289 | 0 | 0 | 0 | |
| prim_alert_tb.i_alert_sender.gen_sync_assert.SigIntAck_A | 0 | 0 | 72289 | 0 | 0 | 0 | |
| prim_alert_tb.i_alert_sender.gen_sync_assert.SigIntPing_A | 0 | 0 | 72289 | 0 | 0 | 0 |
| ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
| prim_alert_tb.i_alert_receiver.AckDiffOk_A | 0 | 0 | 143299 | 107846 | 0 | 150 | |
| prim_alert_tb.i_alert_receiver.PingOkBypassDuringInit_A | 0 | 0 | 143928 | 44 | 0 | 40 | |
| prim_alert_tb.i_alert_receiver.PingPending_A | 0 | 0 | 143928 | 785 | 0 | 115 | |
| prim_alert_tb.i_alert_receiver.PingRequest0_A | 0 | 0 | 143928 | 0 | 0 | 75 | |
| prim_alert_tb.i_alert_receiver.gen_async_assert.SigInt_A | 0 | 0 | 71639 | 212 | 0 | 84 | |
| prim_alert_tb.i_alert_sender.gen_async_assert.InBandInitFsm_A | 0 | 0 | 71639 | 100 | 0 | 140 | |
| prim_alert_tb.i_alert_sender.gen_async_assert.InBandInitPing_A | 0 | 0 | 71639 | 100 | 0 | 140 | |
| prim_alert_tb.i_alert_sender.gen_async_assert.SigIntAck_A | 0 | 0 | 71639 | 100 | 0 | 175 | |
| prim_alert_tb.i_alert_sender.gen_async_assert.SigIntPing_A | 0 | 0 | 71639 | 100 | 0 | 175 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |