| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 94.85 | 100.00 | 97.92 | 100.00 | 89.29 | 95.83 | 86.05 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 89.82 | 89.82 | 100.00 | 100.00 | 95.83 | 95.83 | 100.00 | 100.00 | 82.14 | 82.14 | 95.83 | 95.83 | 65.12 | 65.12 | /workspace/coverage/default/7.prim_async_alert.1123478612 |
| 92.95 | 3.13 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 95.83 | 0.00 | 76.74 | 11.63 | /workspace/coverage/sync_alert/15.prim_sync_alert.874162012 |
| 94.50 | 1.55 | 100.00 | 0.00 | 95.83 | 0.00 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 9.30 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.245957857 |
| 94.85 | 0.35 | 100.00 | 0.00 | 97.92 | 2.08 | 100.00 | 0.00 | 89.29 | 0.00 | 95.83 | 0.00 | 86.05 | 0.00 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.34087323 |
| Name |
|---|
| /workspace/coverage/default/0.prim_async_alert.1260534881 |
| /workspace/coverage/default/1.prim_async_alert.1512487665 |
| /workspace/coverage/default/10.prim_async_alert.1103954419 |
| /workspace/coverage/default/11.prim_async_alert.4288058264 |
| /workspace/coverage/default/12.prim_async_alert.3555538244 |
| /workspace/coverage/default/13.prim_async_alert.3532210148 |
| /workspace/coverage/default/14.prim_async_alert.2510032075 |
| /workspace/coverage/default/15.prim_async_alert.3583744686 |
| /workspace/coverage/default/16.prim_async_alert.4139578260 |
| /workspace/coverage/default/17.prim_async_alert.772999759 |
| /workspace/coverage/default/19.prim_async_alert.3745557844 |
| /workspace/coverage/default/2.prim_async_alert.3922419119 |
| /workspace/coverage/default/3.prim_async_alert.1937327069 |
| /workspace/coverage/default/5.prim_async_alert.4156712768 |
| /workspace/coverage/default/6.prim_async_alert.4102575208 |
| /workspace/coverage/default/8.prim_async_alert.336148656 |
| /workspace/coverage/default/9.prim_async_alert.1960106352 |
| /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3888970161 |
| /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3159726559 |
| /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2040364738 |
| /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3648641224 |
| /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3298035286 |
| /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.597303227 |
| /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1992795706 |
| /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.481258410 |
| /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3138610568 |
| /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2391340526 |
| /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2001911453 |
| /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.761706507 |
| /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3602218951 |
| /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3124436109 |
| /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3749604403 |
| /workspace/coverage/sync_alert/0.prim_sync_alert.3135374930 |
| /workspace/coverage/sync_alert/1.prim_sync_alert.69687096 |
| /workspace/coverage/sync_alert/10.prim_sync_alert.1990394328 |
| /workspace/coverage/sync_alert/11.prim_sync_alert.4213866801 |
| /workspace/coverage/sync_alert/12.prim_sync_alert.2791379919 |
| /workspace/coverage/sync_alert/13.prim_sync_alert.4088518535 |
| /workspace/coverage/sync_alert/14.prim_sync_alert.4132627333 |
| /workspace/coverage/sync_alert/16.prim_sync_alert.2688592915 |
| /workspace/coverage/sync_alert/17.prim_sync_alert.585000110 |
| /workspace/coverage/sync_alert/18.prim_sync_alert.2068233246 |
| /workspace/coverage/sync_alert/19.prim_sync_alert.1168183374 |
| /workspace/coverage/sync_alert/2.prim_sync_alert.1963009782 |
| /workspace/coverage/sync_alert/3.prim_sync_alert.3663621809 |
| /workspace/coverage/sync_alert/4.prim_sync_alert.1847059186 |
| /workspace/coverage/sync_alert/5.prim_sync_alert.3958505649 |
| /workspace/coverage/sync_alert/6.prim_sync_alert.109226525 |
| /workspace/coverage/sync_alert/7.prim_sync_alert.2228258101 |
| /workspace/coverage/sync_alert/8.prim_sync_alert.2531573446 |
| /workspace/coverage/sync_alert/9.prim_sync_alert.3204453813 |
| /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.535011532 |
| /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3851341140 |
| /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3278886534 |
| /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.147138276 |
| /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2677975578 |
| /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.519553871 |
| /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3149482867 |
| /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1203649189 |
| /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3222508563 |
| /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.916738443 |
| /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1342121627 |
| /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.269249628 |
| /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.96322920 |
| /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2550479462 |
| /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.899909304 |
| /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1427028231 |
| /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1046764436 |
| /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3642290915 |
| /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2829297795 |
| /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.127990543 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_async_alert.772999759 | Mar 31 12:27:30 PM PDT 24 | Mar 31 12:27:30 PM PDT 24 | 10859553 ps | ||
| T2 | /workspace/coverage/default/7.prim_async_alert.1123478612 | Mar 31 12:26:56 PM PDT 24 | Mar 31 12:26:57 PM PDT 24 | 12213785 ps | ||
| T3 | /workspace/coverage/default/8.prim_async_alert.336148656 | Mar 31 12:28:46 PM PDT 24 | Mar 31 12:28:46 PM PDT 24 | 10760049 ps | ||
| T17 | /workspace/coverage/default/13.prim_async_alert.3532210148 | Mar 31 12:27:03 PM PDT 24 | Mar 31 12:27:04 PM PDT 24 | 10844865 ps | ||
| T9 | /workspace/coverage/default/2.prim_async_alert.3922419119 | Mar 31 12:28:46 PM PDT 24 | Mar 31 12:28:46 PM PDT 24 | 10553264 ps | ||
| T7 | /workspace/coverage/default/15.prim_async_alert.3583744686 | Mar 31 12:27:08 PM PDT 24 | Mar 31 12:27:09 PM PDT 24 | 11926408 ps | ||
| T11 | /workspace/coverage/default/6.prim_async_alert.4102575208 | Mar 31 12:27:00 PM PDT 24 | Mar 31 12:27:01 PM PDT 24 | 10966955 ps | ||
| T8 | /workspace/coverage/default/11.prim_async_alert.4288058264 | Mar 31 12:27:49 PM PDT 24 | Mar 31 12:27:50 PM PDT 24 | 10745117 ps | ||
| T14 | /workspace/coverage/default/3.prim_async_alert.1937327069 | Mar 31 12:28:24 PM PDT 24 | Mar 31 12:28:26 PM PDT 24 | 11297475 ps | ||
| T18 | /workspace/coverage/default/9.prim_async_alert.1960106352 | Mar 31 12:28:46 PM PDT 24 | Mar 31 12:28:46 PM PDT 24 | 10921941 ps | ||
| T43 | /workspace/coverage/default/0.prim_async_alert.1260534881 | Mar 31 12:27:23 PM PDT 24 | Mar 31 12:27:24 PM PDT 24 | 11903641 ps | ||
| T44 | /workspace/coverage/default/12.prim_async_alert.3555538244 | Mar 31 12:27:38 PM PDT 24 | Mar 31 12:27:39 PM PDT 24 | 11713322 ps | ||
| T13 | /workspace/coverage/default/5.prim_async_alert.4156712768 | Mar 31 12:28:44 PM PDT 24 | Mar 31 12:28:44 PM PDT 24 | 10581214 ps | ||
| T19 | /workspace/coverage/default/19.prim_async_alert.3745557844 | Mar 31 12:27:25 PM PDT 24 | Mar 31 12:27:26 PM PDT 24 | 11390803 ps | ||
| T20 | /workspace/coverage/default/1.prim_async_alert.1512487665 | Mar 31 12:27:03 PM PDT 24 | Mar 31 12:27:04 PM PDT 24 | 11259337 ps | ||
| T45 | /workspace/coverage/default/16.prim_async_alert.4139578260 | Mar 31 12:27:34 PM PDT 24 | Mar 31 12:27:34 PM PDT 24 | 11087889 ps | ||
| T21 | /workspace/coverage/default/10.prim_async_alert.1103954419 | Mar 31 12:27:09 PM PDT 24 | Mar 31 12:27:15 PM PDT 24 | 11131200 ps | ||
| T15 | /workspace/coverage/default/14.prim_async_alert.2510032075 | Mar 31 12:27:19 PM PDT 24 | Mar 31 12:27:20 PM PDT 24 | 11070800 ps | ||
| T10 | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.245957857 | Mar 31 12:29:08 PM PDT 24 | Mar 31 12:29:09 PM PDT 24 | 29549482 ps | ||
| T37 | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3138610568 | Mar 31 12:28:56 PM PDT 24 | Mar 31 12:28:57 PM PDT 24 | 27440445 ps | ||
| T16 | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.761706507 | Mar 31 12:29:37 PM PDT 24 | Mar 31 12:29:38 PM PDT 24 | 32041145 ps | ||
| T38 | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3602218951 | Mar 31 12:28:59 PM PDT 24 | Mar 31 12:29:00 PM PDT 24 | 31875638 ps | ||
| T39 | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2001911453 | Mar 31 12:28:53 PM PDT 24 | Mar 31 12:28:55 PM PDT 24 | 30284154 ps | ||
| T40 | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2040364738 | Mar 31 12:28:54 PM PDT 24 | Mar 31 12:28:55 PM PDT 24 | 31044500 ps | ||
| T12 | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3124436109 | Mar 31 12:29:03 PM PDT 24 | Mar 31 12:29:03 PM PDT 24 | 32766796 ps | ||
| T41 | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3749604403 | Mar 31 12:28:53 PM PDT 24 | Mar 31 12:28:54 PM PDT 24 | 30985665 ps | ||
| T4 | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.34087323 | Mar 31 12:28:57 PM PDT 24 | Mar 31 12:28:58 PM PDT 24 | 30692566 ps | ||
| T42 | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2391340526 | Mar 31 12:29:11 PM PDT 24 | Mar 31 12:29:12 PM PDT 24 | 31258112 ps | ||
| T46 | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3159726559 | Mar 31 12:29:14 PM PDT 24 | Mar 31 12:29:14 PM PDT 24 | 28626921 ps | ||
| T47 | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1992795706 | Mar 31 12:28:45 PM PDT 24 | Mar 31 12:28:46 PM PDT 24 | 28938098 ps | ||
| T48 | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3888970161 | Mar 31 12:28:53 PM PDT 24 | Mar 31 12:28:54 PM PDT 24 | 29099017 ps | ||
| T49 | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3298035286 | Mar 31 12:28:53 PM PDT 24 | Mar 31 12:28:53 PM PDT 24 | 29561722 ps | ||
| T50 | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.597303227 | Mar 31 12:29:17 PM PDT 24 | Mar 31 12:29:18 PM PDT 24 | 31009815 ps | ||
| T5 | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.481258410 | Mar 31 12:29:14 PM PDT 24 | Mar 31 12:29:14 PM PDT 24 | 29188962 ps | ||
| T51 | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3648641224 | Mar 31 12:29:08 PM PDT 24 | Mar 31 12:29:08 PM PDT 24 | 31499788 ps | ||
| T22 | /workspace/coverage/sync_alert/3.prim_sync_alert.3663621809 | Mar 31 12:35:33 PM PDT 24 | Mar 31 12:35:33 PM PDT 24 | 8696706 ps | ||
| T32 | /workspace/coverage/sync_alert/15.prim_sync_alert.874162012 | Mar 31 12:35:42 PM PDT 24 | Mar 31 12:35:42 PM PDT 24 | 9066176 ps | ||
| T23 | /workspace/coverage/sync_alert/9.prim_sync_alert.3204453813 | Mar 31 12:35:40 PM PDT 24 | Mar 31 12:35:40 PM PDT 24 | 8499220 ps | ||
| T33 | /workspace/coverage/sync_alert/6.prim_sync_alert.109226525 | Mar 31 12:35:45 PM PDT 24 | Mar 31 12:35:45 PM PDT 24 | 8855758 ps | ||
| T34 | /workspace/coverage/sync_alert/7.prim_sync_alert.2228258101 | Mar 31 12:35:43 PM PDT 24 | Mar 31 12:35:44 PM PDT 24 | 8133375 ps | ||
| T35 | /workspace/coverage/sync_alert/14.prim_sync_alert.4132627333 | Mar 31 12:35:33 PM PDT 24 | Mar 31 12:35:33 PM PDT 24 | 8569526 ps | ||
| T24 | /workspace/coverage/sync_alert/1.prim_sync_alert.69687096 | Mar 31 12:35:46 PM PDT 24 | Mar 31 12:35:46 PM PDT 24 | 9569174 ps | ||
| T25 | /workspace/coverage/sync_alert/17.prim_sync_alert.585000110 | Mar 31 12:35:42 PM PDT 24 | Mar 31 12:35:42 PM PDT 24 | 8687648 ps | ||
| T26 | /workspace/coverage/sync_alert/10.prim_sync_alert.1990394328 | Mar 31 12:35:32 PM PDT 24 | Mar 31 12:35:32 PM PDT 24 | 9345923 ps | ||
| T36 | /workspace/coverage/sync_alert/0.prim_sync_alert.3135374930 | Mar 31 12:35:44 PM PDT 24 | Mar 31 12:35:45 PM PDT 24 | 9156843 ps | ||
| T52 | /workspace/coverage/sync_alert/8.prim_sync_alert.2531573446 | Mar 31 12:35:33 PM PDT 24 | Mar 31 12:35:33 PM PDT 24 | 8669522 ps | ||
| T27 | /workspace/coverage/sync_alert/18.prim_sync_alert.2068233246 | Mar 31 12:35:40 PM PDT 24 | Mar 31 12:35:41 PM PDT 24 | 9204781 ps | ||
| T53 | /workspace/coverage/sync_alert/2.prim_sync_alert.1963009782 | Mar 31 12:35:44 PM PDT 24 | Mar 31 12:35:45 PM PDT 24 | 9726365 ps | ||
| T54 | /workspace/coverage/sync_alert/12.prim_sync_alert.2791379919 | Mar 31 12:35:31 PM PDT 24 | Mar 31 12:35:32 PM PDT 24 | 9327738 ps | ||
| T55 | /workspace/coverage/sync_alert/16.prim_sync_alert.2688592915 | Mar 31 12:35:44 PM PDT 24 | Mar 31 12:35:45 PM PDT 24 | 9034507 ps | ||
| T56 | /workspace/coverage/sync_alert/11.prim_sync_alert.4213866801 | Mar 31 12:35:42 PM PDT 24 | Mar 31 12:35:44 PM PDT 24 | 9046494 ps | ||
| T57 | /workspace/coverage/sync_alert/13.prim_sync_alert.4088518535 | Mar 31 12:35:44 PM PDT 24 | Mar 31 12:35:45 PM PDT 24 | 8914060 ps | ||
| T28 | /workspace/coverage/sync_alert/4.prim_sync_alert.1847059186 | Mar 31 12:35:37 PM PDT 24 | Mar 31 12:35:38 PM PDT 24 | 9376985 ps | ||
| T58 | /workspace/coverage/sync_alert/5.prim_sync_alert.3958505649 | Mar 31 12:35:41 PM PDT 24 | Mar 31 12:35:41 PM PDT 24 | 8957728 ps | ||
| T59 | /workspace/coverage/sync_alert/19.prim_sync_alert.1168183374 | Mar 31 12:35:44 PM PDT 24 | Mar 31 12:35:45 PM PDT 24 | 8700942 ps | ||
| T29 | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3222508563 | Mar 31 12:25:57 PM PDT 24 | Mar 31 12:25:58 PM PDT 24 | 27563170 ps | ||
| T6 | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2829297795 | Mar 31 12:25:53 PM PDT 24 | Mar 31 12:25:53 PM PDT 24 | 29129784 ps | ||
| T30 | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1427028231 | Mar 31 12:25:59 PM PDT 24 | Mar 31 12:26:00 PM PDT 24 | 26920072 ps | ||
| T31 | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1203649189 | Mar 31 12:25:57 PM PDT 24 | Mar 31 12:25:58 PM PDT 24 | 27070803 ps | ||
| T60 | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.535011532 | Mar 31 12:25:54 PM PDT 24 | Mar 31 12:25:55 PM PDT 24 | 27060525 ps | ||
| T61 | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.519553871 | Mar 31 12:25:57 PM PDT 24 | Mar 31 12:25:57 PM PDT 24 | 28788866 ps | ||
| T62 | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3642290915 | Mar 31 12:26:00 PM PDT 24 | Mar 31 12:26:01 PM PDT 24 | 27789466 ps | ||
| T63 | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.147138276 | Mar 31 12:26:10 PM PDT 24 | Mar 31 12:26:11 PM PDT 24 | 25605862 ps | ||
| T64 | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.96322920 | Mar 31 12:25:55 PM PDT 24 | Mar 31 12:25:55 PM PDT 24 | 26596733 ps | ||
| T65 | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3149482867 | Mar 31 12:26:08 PM PDT 24 | Mar 31 12:26:09 PM PDT 24 | 26457358 ps | ||
| T66 | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1046764436 | Mar 31 12:25:59 PM PDT 24 | Mar 31 12:25:59 PM PDT 24 | 27883386 ps | ||
| T67 | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1342121627 | Mar 31 12:26:01 PM PDT 24 | Mar 31 12:26:02 PM PDT 24 | 27560426 ps | ||
| T68 | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.899909304 | Mar 31 12:25:57 PM PDT 24 | Mar 31 12:25:57 PM PDT 24 | 26527116 ps | ||
| T69 | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.127990543 | Mar 31 12:25:59 PM PDT 24 | Mar 31 12:26:00 PM PDT 24 | 26420732 ps | ||
| T70 | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.269249628 | Mar 31 12:25:56 PM PDT 24 | Mar 31 12:25:57 PM PDT 24 | 28400659 ps | ||
| T71 | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2550479462 | Mar 31 12:25:54 PM PDT 24 | Mar 31 12:25:55 PM PDT 24 | 26100438 ps | ||
| T72 | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.916738443 | Mar 31 12:25:59 PM PDT 24 | Mar 31 12:26:00 PM PDT 24 | 27973882 ps | ||
| T73 | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3851341140 | Mar 31 12:26:05 PM PDT 24 | Mar 31 12:26:06 PM PDT 24 | 26263546 ps | ||
| T74 | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3278886534 | Mar 31 12:25:54 PM PDT 24 | Mar 31 12:25:55 PM PDT 24 | 27283904 ps | ||
| T75 | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2677975578 | Mar 31 12:26:07 PM PDT 24 | Mar 31 12:26:08 PM PDT 24 | 26742910 ps |
| Test location | /workspace/coverage/default/7.prim_async_alert.1123478612 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12213785 ps |
| CPU time | 0.42 seconds |
| Started | Mar 31 12:26:56 PM PDT 24 |
| Finished | Mar 31 12:26:57 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-181e00e7-9c86-4928-be76-6c665aa4a6ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123478612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.1123478612 |
| Directory | /workspace/7.prim_async_alert/latest |
| Test location | /workspace/coverage/sync_alert/15.prim_sync_alert.874162012 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9066176 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:35:42 PM PDT 24 |
| Finished | Mar 31 12:35:42 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-941b91fd-7f86-4992-8bd5-e280cbbce030 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=874162012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.874162012 |
| Directory | /workspace/15.prim_sync_alert/latest |
| Test location | /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.245957857 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 29549482 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:29:08 PM PDT 24 |
| Finished | Mar 31 12:29:09 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-7fa0ed17-335d-460d-8d63-294c34777576 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=245957857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.245957857 |
| Directory | /workspace/12.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.34087323 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30692566 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:28:57 PM PDT 24 |
| Finished | Mar 31 12:28:58 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-9808570e-27a6-4e7d-b4d5-37957f1013e5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=34087323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.34087323 |
| Directory | /workspace/14.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/default/0.prim_async_alert.1260534881 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11903641 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:27:23 PM PDT 24 |
| Finished | Mar 31 12:27:24 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-830ad510-91bd-436a-903f-237abc1af07e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1260534881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.1260534881 |
| Directory | /workspace/0.prim_async_alert/latest |
| Test location | /workspace/coverage/default/1.prim_async_alert.1512487665 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11259337 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:27:03 PM PDT 24 |
| Finished | Mar 31 12:27:04 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-65ccac90-d285-455e-8f6d-56e9a16d20f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1512487665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1512487665 |
| Directory | /workspace/1.prim_async_alert/latest |
| Test location | /workspace/coverage/default/10.prim_async_alert.1103954419 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11131200 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:27:09 PM PDT 24 |
| Finished | Mar 31 12:27:15 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-5a457480-4b96-4c8c-8a77-7d3df18a0c76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103954419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1103954419 |
| Directory | /workspace/10.prim_async_alert/latest |
| Test location | /workspace/coverage/default/11.prim_async_alert.4288058264 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10745117 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:27:49 PM PDT 24 |
| Finished | Mar 31 12:27:50 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-774df861-1e44-4a93-93af-3907749a6516 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288058264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.4288058264 |
| Directory | /workspace/11.prim_async_alert/latest |
| Test location | /workspace/coverage/default/12.prim_async_alert.3555538244 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11713322 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:27:38 PM PDT 24 |
| Finished | Mar 31 12:27:39 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-707460a5-bce8-44f7-a2eb-a2be3599a1ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555538244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3555538244 |
| Directory | /workspace/12.prim_async_alert/latest |
| Test location | /workspace/coverage/default/13.prim_async_alert.3532210148 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10844865 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:27:03 PM PDT 24 |
| Finished | Mar 31 12:27:04 PM PDT 24 |
| Peak memory | 145640 kb |
| Host | smart-6e24a1d2-5928-468a-bb08-23cbaa477861 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532210148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3532210148 |
| Directory | /workspace/13.prim_async_alert/latest |
| Test location | /workspace/coverage/default/14.prim_async_alert.2510032075 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11070800 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:27:19 PM PDT 24 |
| Finished | Mar 31 12:27:20 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-d39aac78-c938-4b7f-a771-ec318f97bdb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510032075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.2510032075 |
| Directory | /workspace/14.prim_async_alert/latest |
| Test location | /workspace/coverage/default/15.prim_async_alert.3583744686 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11926408 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:27:08 PM PDT 24 |
| Finished | Mar 31 12:27:09 PM PDT 24 |
| Peak memory | 145660 kb |
| Host | smart-7a740e7e-7b0d-4827-94ae-9d74a02388e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583744686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3583744686 |
| Directory | /workspace/15.prim_async_alert/latest |
| Test location | /workspace/coverage/default/16.prim_async_alert.4139578260 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11087889 ps |
| CPU time | 0.41 seconds |
| Started | Mar 31 12:27:34 PM PDT 24 |
| Finished | Mar 31 12:27:34 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-4de67ec4-7b0c-4653-9ea2-fbd73cb4b1bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139578260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.4139578260 |
| Directory | /workspace/16.prim_async_alert/latest |
| Test location | /workspace/coverage/default/17.prim_async_alert.772999759 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10859553 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:27:30 PM PDT 24 |
| Finished | Mar 31 12:27:30 PM PDT 24 |
| Peak memory | 145656 kb |
| Host | smart-ee9cd38e-e73b-408d-a25e-a7d13f342ce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772999759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.772999759 |
| Directory | /workspace/17.prim_async_alert/latest |
| Test location | /workspace/coverage/default/19.prim_async_alert.3745557844 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11390803 ps |
| CPU time | 0.4 seconds |
| Started | Mar 31 12:27:25 PM PDT 24 |
| Finished | Mar 31 12:27:26 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-a99805dd-ee9f-4e50-bb29-2a36f9c84cdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745557844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3745557844 |
| Directory | /workspace/19.prim_async_alert/latest |
| Test location | /workspace/coverage/default/2.prim_async_alert.3922419119 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10553264 ps |
| CPU time | 0.41 seconds |
| Started | Mar 31 12:28:46 PM PDT 24 |
| Finished | Mar 31 12:28:46 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-9f1a6678-7bc5-4d57-a2fd-fdac586386c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922419119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3922419119 |
| Directory | /workspace/2.prim_async_alert/latest |
| Test location | /workspace/coverage/default/3.prim_async_alert.1937327069 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11297475 ps |
| CPU time | 0.44 seconds |
| Started | Mar 31 12:28:24 PM PDT 24 |
| Finished | Mar 31 12:28:26 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-92be2888-8fa0-481a-a5a7-549e145850d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937327069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.1937327069 |
| Directory | /workspace/3.prim_async_alert/latest |
| Test location | /workspace/coverage/default/5.prim_async_alert.4156712768 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10581214 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:28:44 PM PDT 24 |
| Finished | Mar 31 12:28:44 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-c324e7ea-00ec-41f9-aa6f-4cfb60b26e46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4156712768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.4156712768 |
| Directory | /workspace/5.prim_async_alert/latest |
| Test location | /workspace/coverage/default/6.prim_async_alert.4102575208 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10966955 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:27:00 PM PDT 24 |
| Finished | Mar 31 12:27:01 PM PDT 24 |
| Peak memory | 145664 kb |
| Host | smart-afa33a18-668e-49dd-a850-8fa14c845928 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102575208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.4102575208 |
| Directory | /workspace/6.prim_async_alert/latest |
| Test location | /workspace/coverage/default/8.prim_async_alert.336148656 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10760049 ps |
| CPU time | 0.4 seconds |
| Started | Mar 31 12:28:46 PM PDT 24 |
| Finished | Mar 31 12:28:46 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-195f4b16-86f5-480b-88cb-26c53e5f23f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336148656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.336148656 |
| Directory | /workspace/8.prim_async_alert/latest |
| Test location | /workspace/coverage/default/9.prim_async_alert.1960106352 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10921941 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:28:46 PM PDT 24 |
| Finished | Mar 31 12:28:46 PM PDT 24 |
| Peak memory | 145464 kb |
| Host | smart-8b490ebb-affc-411d-9aa8-700f1eb69444 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960106352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.1960106352 |
| Directory | /workspace/9.prim_async_alert/latest |
| Test location | /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.3888970161 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29099017 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:28:53 PM PDT 24 |
| Finished | Mar 31 12:28:54 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-c9e12692-c1c9-4ec0-86d6-f95a213e42d5 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3888970161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3888970161 |
| Directory | /workspace/0.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.3159726559 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 28626921 ps |
| CPU time | 0.41 seconds |
| Started | Mar 31 12:29:14 PM PDT 24 |
| Finished | Mar 31 12:29:14 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-781aeee3-8c13-4f95-8da4-6ff25bc24eb0 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3159726559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.3159726559 |
| Directory | /workspace/10.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.2040364738 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 31044500 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:28:54 PM PDT 24 |
| Finished | Mar 31 12:28:55 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-8895e7c0-90da-4979-843b-1d3c8658eb30 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2040364738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.2040364738 |
| Directory | /workspace/11.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3648641224 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 31499788 ps |
| CPU time | 0.41 seconds |
| Started | Mar 31 12:29:08 PM PDT 24 |
| Finished | Mar 31 12:29:08 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-6bb8334b-b4da-4fc6-bb9e-d7d4218fbaac |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3648641224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3648641224 |
| Directory | /workspace/13.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.3298035286 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 29561722 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:28:53 PM PDT 24 |
| Finished | Mar 31 12:28:53 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-63452472-c04c-4d22-a606-5e5e58bba43b |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3298035286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.3298035286 |
| Directory | /workspace/15.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.597303227 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 31009815 ps |
| CPU time | 0.44 seconds |
| Started | Mar 31 12:29:17 PM PDT 24 |
| Finished | Mar 31 12:29:18 PM PDT 24 |
| Peak memory | 145744 kb |
| Host | smart-4423aeb1-d541-43d6-9040-c92bf6c96877 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=597303227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.597303227 |
| Directory | /workspace/16.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1992795706 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28938098 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:28:45 PM PDT 24 |
| Finished | Mar 31 12:28:46 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-173bbf73-3c4f-4cb7-a693-c84a9d8f926e |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1992795706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1992795706 |
| Directory | /workspace/17.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.481258410 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29188962 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:29:14 PM PDT 24 |
| Finished | Mar 31 12:29:14 PM PDT 24 |
| Peak memory | 145800 kb |
| Host | smart-5ea8a061-a4c0-42c6-9bd0-bb31f982b5af |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=481258410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.481258410 |
| Directory | /workspace/18.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3138610568 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 27440445 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:28:56 PM PDT 24 |
| Finished | Mar 31 12:28:57 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-45b5f91d-f8fb-4dbc-9cc6-826646d8b373 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3138610568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3138610568 |
| Directory | /workspace/19.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.2391340526 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 31258112 ps |
| CPU time | 0.4 seconds |
| Started | Mar 31 12:29:11 PM PDT 24 |
| Finished | Mar 31 12:29:12 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-6b845513-6966-4b27-aebb-6e4fa81a0c4c |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2391340526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.2391340526 |
| Directory | /workspace/2.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.2001911453 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 30284154 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:28:53 PM PDT 24 |
| Finished | Mar 31 12:28:55 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-fa4480cc-8279-42f3-9ccc-fd24baa581af |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2001911453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.2001911453 |
| Directory | /workspace/5.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.761706507 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 32041145 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:29:37 PM PDT 24 |
| Finished | Mar 31 12:29:38 PM PDT 24 |
| Peak memory | 145644 kb |
| Host | smart-445c246f-c34b-4ab8-956c-24b31f5440c4 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=761706507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.761706507 |
| Directory | /workspace/6.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.3602218951 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 31875638 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:28:59 PM PDT 24 |
| Finished | Mar 31 12:29:00 PM PDT 24 |
| Peak memory | 145672 kb |
| Host | smart-b01f16c7-ab36-4497-b15a-1e983f128a39 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3602218951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.3602218951 |
| Directory | /workspace/7.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.3124436109 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 32766796 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:29:03 PM PDT 24 |
| Finished | Mar 31 12:29:03 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-4c7f1573-d7cd-48c6-8139-861b09d41e86 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3124436109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3124436109 |
| Directory | /workspace/8.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.3749604403 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30985665 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:28:53 PM PDT 24 |
| Finished | Mar 31 12:28:54 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-7a35d103-a669-41d1-b352-8dce35c5aa03 |
| User | root |
| Command | /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3749604403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.3749604403 |
| Directory | /workspace/9.prim_async_fatal_alert/latest |
| Test location | /workspace/coverage/sync_alert/0.prim_sync_alert.3135374930 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9156843 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:35:44 PM PDT 24 |
| Finished | Mar 31 12:35:45 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-2aa83d4b-7f57-4622-a621-6a51ac2bb969 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3135374930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.3135374930 |
| Directory | /workspace/0.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/1.prim_sync_alert.69687096 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9569174 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:35:46 PM PDT 24 |
| Finished | Mar 31 12:35:46 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-3f533b8e-23b2-4ba1-a3d2-942ed74784cf |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=69687096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.69687096 |
| Directory | /workspace/1.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/10.prim_sync_alert.1990394328 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9345923 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:35:32 PM PDT 24 |
| Finished | Mar 31 12:35:32 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-28cdcf57-64a5-4dc0-a019-265ce56ddb4e |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1990394328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.1990394328 |
| Directory | /workspace/10.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/11.prim_sync_alert.4213866801 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9046494 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:35:42 PM PDT 24 |
| Finished | Mar 31 12:35:44 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-d970aad6-e5f9-42be-8a3c-358415190693 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4213866801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4213866801 |
| Directory | /workspace/11.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/12.prim_sync_alert.2791379919 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 9327738 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:35:31 PM PDT 24 |
| Finished | Mar 31 12:35:32 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-ac9a2ead-98ad-431c-834e-927ef89721ea |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2791379919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.2791379919 |
| Directory | /workspace/12.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/13.prim_sync_alert.4088518535 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8914060 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:35:44 PM PDT 24 |
| Finished | Mar 31 12:35:45 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-462824f6-d6ab-4275-85b3-e0b2ac910514 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4088518535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.4088518535 |
| Directory | /workspace/13.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/14.prim_sync_alert.4132627333 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8569526 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:35:33 PM PDT 24 |
| Finished | Mar 31 12:35:33 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-90b72c33-a4b2-404f-8f5a-677b56530e60 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=4132627333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.4132627333 |
| Directory | /workspace/14.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/16.prim_sync_alert.2688592915 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 9034507 ps |
| CPU time | 0.4 seconds |
| Started | Mar 31 12:35:44 PM PDT 24 |
| Finished | Mar 31 12:35:45 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-bc78e4e1-da57-4ce4-a310-ada92bb02d43 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2688592915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.2688592915 |
| Directory | /workspace/16.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/17.prim_sync_alert.585000110 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8687648 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:35:42 PM PDT 24 |
| Finished | Mar 31 12:35:42 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-152d4778-3c75-4eff-bbb5-3907802c4266 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=585000110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.585000110 |
| Directory | /workspace/17.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/18.prim_sync_alert.2068233246 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9204781 ps |
| CPU time | 0.42 seconds |
| Started | Mar 31 12:35:40 PM PDT 24 |
| Finished | Mar 31 12:35:41 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-74d1b4b4-befa-4af5-9349-461a65f63917 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2068233246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.2068233246 |
| Directory | /workspace/18.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/19.prim_sync_alert.1168183374 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8700942 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:35:44 PM PDT 24 |
| Finished | Mar 31 12:35:45 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-c0cf0ac9-8428-4d70-8a9f-92b880cd9897 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1168183374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1168183374 |
| Directory | /workspace/19.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/2.prim_sync_alert.1963009782 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 9726365 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:35:44 PM PDT 24 |
| Finished | Mar 31 12:35:45 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-36654024-7944-4554-9897-ead81610abff |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1963009782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.1963009782 |
| Directory | /workspace/2.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/3.prim_sync_alert.3663621809 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8696706 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:35:33 PM PDT 24 |
| Finished | Mar 31 12:35:33 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-a5808c24-0042-4f13-983d-1b0bb0cf6242 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3663621809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3663621809 |
| Directory | /workspace/3.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/4.prim_sync_alert.1847059186 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9376985 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:35:37 PM PDT 24 |
| Finished | Mar 31 12:35:38 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-bd75d545-5411-406d-8977-32fce02f4195 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=1847059186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1847059186 |
| Directory | /workspace/4.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/5.prim_sync_alert.3958505649 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8957728 ps |
| CPU time | 0.36 seconds |
| Started | Mar 31 12:35:41 PM PDT 24 |
| Finished | Mar 31 12:35:41 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-fef2f131-152d-461d-b787-dbce41a3d007 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3958505649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.3958505649 |
| Directory | /workspace/5.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/6.prim_sync_alert.109226525 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8855758 ps |
| CPU time | 0.4 seconds |
| Started | Mar 31 12:35:45 PM PDT 24 |
| Finished | Mar 31 12:35:45 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-2782be9c-89aa-47e4-80c9-ab4d7df1a643 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=109226525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.109226525 |
| Directory | /workspace/6.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/7.prim_sync_alert.2228258101 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8133375 ps |
| CPU time | 0.41 seconds |
| Started | Mar 31 12:35:43 PM PDT 24 |
| Finished | Mar 31 12:35:44 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-443145cc-d29e-48b6-a890-3b3816fd0551 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2228258101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.2228258101 |
| Directory | /workspace/7.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/8.prim_sync_alert.2531573446 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 8669522 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:35:33 PM PDT 24 |
| Finished | Mar 31 12:35:33 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-5db4f683-31cb-4c3c-bbaa-c3e5a3bd74f7 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=2531573446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.2531573446 |
| Directory | /workspace/8.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_alert/9.prim_sync_alert.3204453813 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8499220 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:35:40 PM PDT 24 |
| Finished | Mar 31 12:35:40 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-cea7fb37-06e9-416f-9136-a2754d628431 |
| User | root |
| Command | /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to ols/sim.tcl +ntb_random_seed=3204453813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.3204453813 |
| Directory | /workspace/9.prim_sync_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.535011532 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 27060525 ps |
| CPU time | 0.44 seconds |
| Started | Mar 31 12:25:54 PM PDT 24 |
| Finished | Mar 31 12:25:55 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-a1223e4a-58a3-48b4-a92c-07080e88a202 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=535011532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.535011532 |
| Directory | /workspace/0.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.3851341140 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 26263546 ps |
| CPU time | 0.4 seconds |
| Started | Mar 31 12:26:05 PM PDT 24 |
| Finished | Mar 31 12:26:06 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-b2955e0c-4d52-4e68-8773-9b6448430619 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3851341140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.3851341140 |
| Directory | /workspace/1.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.3278886534 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 27283904 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:25:54 PM PDT 24 |
| Finished | Mar 31 12:25:55 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-f148da5f-2599-4557-8c54-b583eb7471bf |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3278886534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.3278886534 |
| Directory | /workspace/10.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.147138276 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 25605862 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:26:10 PM PDT 24 |
| Finished | Mar 31 12:26:11 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-62f8be56-373d-4b6a-856f-1e042f3a2a87 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=147138276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.147138276 |
| Directory | /workspace/11.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2677975578 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 26742910 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:26:07 PM PDT 24 |
| Finished | Mar 31 12:26:08 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-5260afca-1139-41d2-95e1-16d8a2e244d1 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2677975578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2677975578 |
| Directory | /workspace/12.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.519553871 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 28788866 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:25:57 PM PDT 24 |
| Finished | Mar 31 12:25:57 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-b61bdda4-8114-4b39-9468-03744dea7735 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=519553871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.519553871 |
| Directory | /workspace/13.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3149482867 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26457358 ps |
| CPU time | 0.41 seconds |
| Started | Mar 31 12:26:08 PM PDT 24 |
| Finished | Mar 31 12:26:09 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-6dd430b1-80a2-4b86-a2a8-367caba692e5 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3149482867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3149482867 |
| Directory | /workspace/14.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.1203649189 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 27070803 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:25:57 PM PDT 24 |
| Finished | Mar 31 12:25:58 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-ad0b4f5d-ce8d-44c9-bf31-574ae6749430 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1203649189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.1203649189 |
| Directory | /workspace/15.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.3222508563 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 27563170 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:25:57 PM PDT 24 |
| Finished | Mar 31 12:25:58 PM PDT 24 |
| Peak memory | 144900 kb |
| Host | smart-4951e7d1-9b61-452e-8d6c-2a5dcbec3dbe |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3222508563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.3222508563 |
| Directory | /workspace/16.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.916738443 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27973882 ps |
| CPU time | 0.4 seconds |
| Started | Mar 31 12:25:59 PM PDT 24 |
| Finished | Mar 31 12:26:00 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-29846427-4e1b-4acd-b644-fcb98c252662 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=916738443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.916738443 |
| Directory | /workspace/17.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.1342121627 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 27560426 ps |
| CPU time | 0.42 seconds |
| Started | Mar 31 12:26:01 PM PDT 24 |
| Finished | Mar 31 12:26:02 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-722d996b-6075-4a85-be3b-7d8556b2aa53 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1342121627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.1342121627 |
| Directory | /workspace/18.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.269249628 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 28400659 ps |
| CPU time | 0.38 seconds |
| Started | Mar 31 12:25:56 PM PDT 24 |
| Finished | Mar 31 12:25:57 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-11ab5bef-c2df-4254-a647-fb1b651e769b |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=269249628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.269249628 |
| Directory | /workspace/19.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.96322920 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26596733 ps |
| CPU time | 0.37 seconds |
| Started | Mar 31 12:25:55 PM PDT 24 |
| Finished | Mar 31 12:25:55 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-e71d404c-8d49-489c-8f35-ef887c6ada77 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=96322920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.96322920 |
| Directory | /workspace/2.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2550479462 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26100438 ps |
| CPU time | 0.44 seconds |
| Started | Mar 31 12:25:54 PM PDT 24 |
| Finished | Mar 31 12:25:55 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-1f36b8db-1e2b-4776-9f47-6f6f06d8681f |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2550479462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2550479462 |
| Directory | /workspace/3.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.899909304 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26527116 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:25:57 PM PDT 24 |
| Finished | Mar 31 12:25:57 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-d741d04c-cf12-4f7e-be16-431e14f913a3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=899909304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.899909304 |
| Directory | /workspace/4.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1427028231 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 26920072 ps |
| CPU time | 0.41 seconds |
| Started | Mar 31 12:25:59 PM PDT 24 |
| Finished | Mar 31 12:26:00 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-89b13915-5e8c-4e44-9984-f4752bf5acc4 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1427028231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1427028231 |
| Directory | /workspace/5.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.1046764436 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 27883386 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:25:59 PM PDT 24 |
| Finished | Mar 31 12:25:59 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-a47d18fd-6649-4108-a017-a9f57cc7bce3 |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1046764436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.1046764436 |
| Directory | /workspace/6.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3642290915 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 27789466 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:26:00 PM PDT 24 |
| Finished | Mar 31 12:26:01 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-eb562e46-7edc-4be1-a57e-0bc39dec81eb |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3642290915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3642290915 |
| Directory | /workspace/7.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.2829297795 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 29129784 ps |
| CPU time | 0.4 seconds |
| Started | Mar 31 12:25:53 PM PDT 24 |
| Finished | Mar 31 12:25:53 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-d50ab013-537a-4d31-bc5a-232fa035f0ab |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2829297795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.2829297795 |
| Directory | /workspace/8.prim_sync_fatal_alert/latest |
| Test location | /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.127990543 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 26420732 ps |
| CPU time | 0.39 seconds |
| Started | Mar 31 12:25:59 PM PDT 24 |
| Finished | Mar 31 12:26:00 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-d61dd68e-ff9c-4ee0-bbe8-b1bb632c7f5e |
| User | root |
| Command | /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=127990543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.127990543 |
| Directory | /workspace/9.prim_sync_fatal_alert/latest |
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