Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T8
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T10	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T11,T5
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T7,T12,T13
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T14,T4,T15

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	154989	116864	0	160
AlertKnownO_A	155695	118558	0	0
InBandInitRequest_A	155695	4175	0	0
InBandInitSequence_A	155695	404	0	0
InitReq_A	155695	763	0	0
IntegFailKnownO_A	155695	118558	0	0
NoSpuriousAlertsDuringInit_A	155695	16571	0	0
NoSpuriousPingOksDuringInit_A	155695	16214	0	0
PingDiffOk_A	154771	117634	0	0
PingOkBypassDuringInit_A	155695	48	0	40
PingOkKnownO_A	155695	118558	0	0
PingPKnownO_A	155695	118558	0	0
PingPending_A	155695	840	0	120
PingRequest0_A	155695	0	0	80
PingResponse0_A	155695	783	0	0
gen_async_assert.Alert_A	82534	1354	0	0
gen_async_assert.PingResponse1_A	82534	335	0	0
gen_async_assert.SigInt_A	82534	241	0	99
gen_sync_assert.Alert_A	73161	3145	0	0
gen_sync_assert.PingResponse1_A	73161	351	0	0
gen_sync_assert.SigInt_A	73161	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154989	116864	0	160
T1	1192	1003	0	2
T2	1085	1029	0	2
T3	1136	1000	0	2
T7	1111	1025	0	2
T9	1163	1094	0	2
T12	1126	1039	0	2
T16	1079	981	0	2
T17	1080	1018	0	2
T18	1101	1001	0	2
T19	1140	1068	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	118558	0	0
T1	1207	1022	0	0
T2	1100	1046	0	0
T3	1151	1019	0	0
T7	1125	1041	0	0
T9	1179	1112	0	0
T12	1141	1056	0	0
T16	1094	998	0	0
T17	1095	1035	0	0
T18	1115	1017	0	0
T19	1155	1085	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	4175	0	0
T1	1207	48	0	0
T2	1100	56	0	0
T3	1151	45	0	0
T7	1125	55	0	0
T9	1179	67	0	0
T12	1141	71	0	0
T16	1094	42	0	0
T17	1095	46	0	0
T18	1115	38	0	0
T19	1155	69	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	404	0	0
T1	1207	3	0	0
T2	1100	2	0	0
T3	1151	1	0	0
T7	1125	2	0	0
T9	1179	1	0	0
T12	1141	1	0	0
T16	1094	1	0	0
T17	1095	2	0	0
T18	1115	1	0	0
T19	1155	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	763	0	0
T1	1207	8	0	0
T2	1100	11	0	0
T3	1151	7	0	0
T7	1125	10	0	0
T9	1179	13	0	0
T12	1141	13	0	0
T16	1094	9	0	0
T17	1095	10	0	0
T18	1115	10	0	0
T19	1155	12	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	118558	0	0
T1	1207	1022	0	0
T2	1100	1046	0	0
T3	1151	1019	0	0
T7	1125	1041	0	0
T9	1179	1112	0	0
T12	1141	1056	0	0
T16	1094	998	0	0
T17	1095	1035	0	0
T18	1115	1017	0	0
T19	1155	1085	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	16571	0	0
T1	1207	184	0	0
T2	1100	207	0	0
T3	1151	174	0	0
T7	1125	205	0	0
T9	1179	250	0	0
T12	1141	257	0	0
T16	1094	186	0	0
T17	1095	198	0	0
T18	1115	201	0	0
T19	1155	238	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	16214	0	0
T1	1207	168	0	0
T2	1100	203	0	0
T3	1151	168	0	0
T7	1125	201	0	0
T9	1179	238	0	0
T12	1141	251	0	0
T16	1094	181	0	0
T17	1095	196	0	0
T18	1115	197	0	0
T19	1155	236	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154771	117634	0	0
T1	1191	1006	0	0
T2	1088	1034	0	0
T3	1135	1003	0	0
T7	1110	1026	0	0
T9	1162	1095	0	0
T12	1128	1043	0	0
T16	1076	980	0	0
T17	1077	1017	0	0
T18	1098	1000	0	0
T19	1141	1071	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	48	0	40
T1	1207	1	0	0
T2	1100	0	0	0
T3	1151	0	0	0
T7	1125	1	0	0
T9	1179	0	0	0
T12	1141	4	0	0
T14	0	2	0	0
T15	0	0	0	1
T16	1094	1	0	0
T17	1095	0	0	0
T18	1115	0	0	0
T19	1155	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	118558	0	0
T1	1207	1022	0	0
T2	1100	1046	0	0
T3	1151	1019	0	0
T7	1125	1041	0	0
T9	1179	1112	0	0
T12	1141	1056	0	0
T16	1094	998	0	0
T17	1095	1035	0	0
T18	1115	1017	0	0
T19	1155	1085	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	118558	0	0
T1	1207	1022	0	0
T2	1100	1046	0	0
T3	1151	1019	0	0
T7	1125	1041	0	0
T9	1179	1112	0	0
T12	1141	1056	0	0
T16	1094	998	0	0
T17	1095	1035	0	0
T18	1115	1017	0	0
T19	1155	1085	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	840	0	120
T1	1207	11	0	1
T2	1100	11	0	1
T3	1151	11	0	1
T7	1125	11	0	1
T9	1179	11	0	1
T12	1141	11	0	1
T16	1094	11	0	1
T17	1095	11	0	1
T18	1115	11	0	1
T19	1155	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	0	0	80

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155695	783	0	0
T1	1207	10	0	0
T2	1100	9	0	0
T3	1151	10	0	0
T7	1125	9	0	0
T9	1179	10	0	0
T12	1141	10	0	0
T16	1094	10	0	0
T17	1095	10	0	0
T18	1115	10	0	0
T19	1155	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82534	1354	0	0
T1	1207	9	0	0
T2	1100	6	0	0
T3	1151	10	0	0
T7	1125	9	0	0
T9	1179	3	0	0
T12	1141	7	0	0
T16	1094	7	0	0
T17	1095	5	0	0
T18	1115	6	0	0
T19	1155	5	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82534	335	0	0
T1	1207	8	0	0
T2	1100	8	0	0
T3	1151	7	0	0
T7	1125	7	0	0
T9	1179	9	0	0
T12	1141	5	0	0
T16	1094	7	0	0
T17	1095	9	0	0
T18	1115	8	0	0
T19	1155	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82534	241	0	99
T1	1207	5	0	3
T2	1100	6	0	2
T3	1151	8	0	2
T7	1125	6	0	3
T9	1179	8	0	3
T12	1141	6	0	3
T16	1094	6	0	2
T17	1095	6	0	2
T18	1115	5	0	2
T19	1155	6	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73161	3145	0	0
T15	936	7	0	0
T24	976	11	0	0
T25	964	7	0	0
T26	906	11	0	0
T27	822	9	0	0
T28	877	7	0	0
T29	945	8	0	0
T30	838	10	0	0
T31	870	10	0	0
T33	972	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73161	351	0	0
T15	936	6	0	0
T24	976	9	0	0
T25	964	9	0	0
T26	906	9	0	0
T27	822	8	0	0
T28	877	8	0	0
T29	945	9	0	0
T30	838	8	0	0
T31	870	8	0	0
T33	972	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73161	40	0	0
T15	936	1	0	0
T24	976	1	0	0
T25	964	1	0	0
T26	906	1	0	0
T27	822	1	0	0
T28	877	1	0	0
T29	945	1	0	0
T30	838	1	0	0
T31	870	1	0	0
T33	972	1	0	0