Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T9

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T10	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T10,T11,T12
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T1,T2,T7
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T8,T13,T14

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	153760	115803	0	158
AlertKnownO_A	154464	117487	0	0
InBandInitRequest_A	154464	4122	0	0
InBandInitSequence_A	154464	413	0	0
InitReq_A	154464	766	0	0
IntegFailKnownO_A	154464	117487	0	0
NoSpuriousAlertsDuringInit_A	154464	16192	0	0
NoSpuriousPingOksDuringInit_A	154464	15823	0	0
PingDiffOk_A	153593	116616	0	0
PingOkBypassDuringInit_A	154464	62	0	40
PingOkKnownO_A	154464	117487	0	0
PingPKnownO_A	154464	117487	0	0
PingPending_A	154464	827	0	119
PingRequest0_A	154464	0	0	79
PingResponse0_A	154464	759	0	0
gen_async_assert.Alert_A	80409	1363	0	0
gen_async_assert.PingResponse1_A	80409	305	0	0
gen_async_assert.SigInt_A	80409	256	0	91
gen_sync_assert.Alert_A	74055	3182	0	0
gen_sync_assert.PingResponse1_A	74055	338	0	0
gen_sync_assert.SigInt_A	74055	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153760	115803	0	158
T1	1227	1059	0	2
T2	1110	1026	0	2
T3	1141	978	0	2
T6	1116	1026	0	2
T7	1092	1016	0	2
T8	1033	968	0	2
T13	1092	1025	0	2
T14	1059	997	0	2
T15	1103	1001	0	2
T16	1044	953	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	117487	0	0
T1	1242	1078	0	0
T2	1126	1044	0	0
T3	1155	996	0	0
T6	1131	1043	0	0
T7	1108	1034	0	0
T8	1049	986	0	0
T13	1106	1041	0	0
T14	1073	1013	0	0
T15	1117	1017	0	0
T16	1058	969	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	4122	0	0
T1	1242	45	0	0
T2	1126	59	0	0
T3	1155	43	0	0
T6	1131	47	0	0
T7	1108	52	0	0
T8	1049	34	0	0
T13	1106	51	0	0
T14	1073	61	0	0
T15	1117	39	0	0
T16	1058	43	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	413	0	0
T1	1242	2	0	0
T2	1126	2	0	0
T3	1155	2	0	0
T6	1131	2	0	0
T7	1108	2	0	0
T8	1049	1	0	0
T10	0	3	0	0
T13	1106	0	0	0
T14	1073	2	0	0
T15	1117	0	0	0
T16	1058	3	0	0
T17	0	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	766	0	0
T1	1242	10	0	0
T2	1126	13	0	0
T3	1155	7	0	0
T6	1131	10	0	0
T7	1108	8	0	0
T8	1049	6	0	0
T13	1106	13	0	0
T14	1073	11	0	0
T15	1117	9	0	0
T16	1058	7	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	117487	0	0
T1	1242	1078	0	0
T2	1126	1044	0	0
T3	1155	996	0	0
T6	1131	1043	0	0
T7	1108	1034	0	0
T8	1049	986	0	0
T13	1106	1041	0	0
T14	1073	1013	0	0
T15	1117	1017	0	0
T16	1058	969	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	16192	0	0
T1	1242	209	0	0
T2	1126	251	0	0
T3	1155	149	0	0
T6	1131	207	0	0
T7	1108	165	0	0
T8	1049	128	0	0
T13	1106	247	0	0
T14	1073	215	0	0
T15	1117	183	0	0
T16	1058	140	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	15823	0	0
T1	1242	209	0	0
T2	1126	245	0	0
T3	1155	134	0	0
T6	1131	198	0	0
T7	1108	153	0	0
T8	1049	112	0	0
T13	1106	233	0	0
T14	1073	211	0	0
T15	1117	182	0	0
T16	1058	138	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153593	116616	0	0
T1	1227	1063	0	0
T2	1113	1031	0	0
T3	1136	977	0	0
T6	1117	1029	0	0
T7	1094	1020	0	0
T8	1037	974	0	0
T13	1091	1026	0	0
T14	1068	1008	0	0
T15	1105	1005	0	0
T16	1046	957	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	62	0	40
T2	1126	1	0	0
T3	1155	0	0	0
T6	1131	0	0	0
T7	1108	0	0	0
T8	1049	0	0	0
T10	1234	0	0	0
T11	0	1	0	0
T12	0	0	0	1
T13	1106	2	0	0
T14	1073	2	0	0
T15	1117	1	0	0
T16	1058	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	0	0	1
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	117487	0	0
T1	1242	1078	0	0
T2	1126	1044	0	0
T3	1155	996	0	0
T6	1131	1043	0	0
T7	1108	1034	0	0
T8	1049	986	0	0
T13	1106	1041	0	0
T14	1073	1013	0	0
T15	1117	1017	0	0
T16	1058	969	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	117487	0	0
T1	1242	1078	0	0
T2	1126	1044	0	0
T3	1155	996	0	0
T6	1131	1043	0	0
T7	1108	1034	0	0
T8	1049	986	0	0
T13	1106	1041	0	0
T14	1073	1013	0	0
T15	1117	1017	0	0
T16	1058	969	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	827	0	119
T1	1242	11	0	1
T2	1126	11	0	1
T3	1155	11	0	1
T6	1131	11	0	1
T7	1108	11	0	1
T8	1049	11	0	1
T13	1106	11	0	1
T14	1073	10	0	1
T15	1117	11	0	1
T16	1058	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	0	0	79

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154464	759	0	0
T1	1242	10	0	0
T2	1126	9	0	0
T3	1155	9	0	0
T6	1131	9	0	0
T7	1108	10	0	0
T8	1049	10	0	0
T13	1106	10	0	0
T14	1073	9	0	0
T15	1117	10	0	0
T16	1058	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80409	1363	0	0
T1	1242	8	0	0
T2	1126	5	0	0
T3	1155	10	0	0
T6	1131	10	0	0
T7	1108	8	0	0
T8	1049	9	0	0
T13	1106	7	0	0
T14	1073	7	0	0
T15	1117	6	0	0
T16	1058	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80409	305	0	0
T1	1242	10	0	0
T2	1126	6	0	0
T3	1155	9	0	0
T6	1131	5	0	0
T7	1108	9	0	0
T8	1049	9	0	0
T13	1106	6	0	0
T14	1073	7	0	0
T15	1117	9	0	0
T16	1058	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80409	256	0	91
T1	1242	5	0	3
T2	1126	6	0	2
T3	1155	6	0	3
T6	1131	6	0	3
T7	1108	8	0	2
T8	1049	6	0	2
T10	0	0	0	2
T13	1106	7	0	3
T14	1073	7	0	0
T15	1117	6	0	0
T16	1058	6	0	2
T17	0	0	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74055	3182	0	0
T12	990	11	0	0
T22	859	9	0	0
T23	878	10	0	0
T24	852	10	0	0
T25	948	10	0	0
T26	963	9	0	0
T27	816	11	0	0
T31	904	12	0	0
T32	1053	9	0	0
T33	1000	7	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74055	338	0	0
T12	990	9	0	0
T22	859	9	0	0
T23	878	8	0	0
T24	852	9	0	0
T25	948	9	0	0
T26	963	8	0	0
T27	816	7	0	0
T31	904	9	0	0
T32	1053	9	0	0
T33	1000	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74055	40	0	0
T12	990	1	0	0
T22	859	1	0	0
T23	878	1	0	0
T24	852	1	0	0
T25	948	1	0	0
T26	963	1	0	0
T27	816	1	0	0
T31	904	1	0	0
T32	1053	1	0	0
T33	1000	1	0	0