Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_sender	95.52	100.00	100.00	100.00	100.00	95.83	77.27

---

Module Instance : prim_alert_tb.i_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	193	32	32	100.00
ALWAYS	276	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	1	1
145	1	1
146	1	1
163	1	1
167	1	1
171	1	1
172	1	1
175	1	1
177	1	1
178	1	1
182	1	1
183	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
214	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE
226	1	1
227	1	1
229	1	1
230	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
242	1	1
246	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
282	1	1
283	1	1
284	1	1
285	1	1

---

Cond Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (ack_sigint | ping_sigint)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (alert_req | alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (alert_clr ? 1'b0 : alert_req_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (alert_test_i | alert_test_set_q)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (alert_clr ? 1'b0 : alert_test_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (alert_req_trigger | alert_test_trigger)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       177
 EXPRESSION (ping_set_q | ping_event)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (ping_clr ? 1'b0 : ping_trigger)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       182
 EXPRESSION (alert_clr & alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       202
 EXPRESSION (alert_trigger || ping_trigger)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (alert_trigger ? AlertHsPhase1 : PingHsPhase1)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T11,T12	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_ack_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_alert_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertHsPhase1	203	Covered	T1,T2,T3
AlertHsPhase2	211	Covered	T1,T2,T3
Idle	246	Covered	T1,T2,T3
Pause0	220	Covered	T1,T2,T3
Pause1	242	Covered	T1,T2,T3
PingHsPhase1	203	Covered	T1,T2,T3
PingHsPhase2	227	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertHsPhase1->AlertHsPhase2	211	Covered	T1,T2,T3
AlertHsPhase1->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Idle	256	Covered	T2,T7,T8
AlertHsPhase2->Pause0	220	Covered	T1,T2,T3
Idle->AlertHsPhase1	203	Covered	T1,T2,T3
Idle->PingHsPhase1	203	Covered	T1,T2,T3
Pause0->Idle	256	Covered	T18,T40,T26
Pause0->Pause1	242	Covered	T1,T2,T3
Pause1->Idle	246	Covered	T1,T2,T3
PingHsPhase1->Idle	256	Covered	T2,T3,T7
PingHsPhase1->PingHsPhase2	227	Covered	T1,T2,T3
PingHsPhase2->Idle	256	Covered	T1,T2,T7
PingHsPhase2->Pause0	237	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	172	2	2	100.00
TERNARY	178	2	2	100.00
TERNARY	167	2	2	100.00
CASE	199	14	13	92.86
IF	255	2	2	100.00
IF	276	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	(ping_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	199	case (state_q)
-2-:	202	if ((alert_trigger || ping_trigger))
-3-:	203	(alert_trigger) ? 
-4-:	210	if (ack_level)
-5-:	219	if ((!ack_level))
-6-:	226	if (ack_level)
-7-:	235	if ((!ack_level))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	1	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	0	-	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	1	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	0	-	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	1	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	0	-	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	1	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	0	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	255	if (sigint_detected)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	276	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	17	77.27
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	17	77.27

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertHs_A	152503	1082	0	0
AlertPKnownO_A	152503	116159	0	0
AlertState0_A	152503	116159	0	0
AlertTest1_A	152503	79	0	0
AlertTestHs_A	152503	79	0	0
gen_async_assert.DiffEncoding_A	79864	54333	0	0
gen_async_assert.InBandInitFsm_A	79864	108	0	156
gen_async_assert.InBandInitPing_A	79864	108	0	156
gen_async_assert.PingHs_A	79864	368	0	0
gen_async_assert.SigIntAck_A	79864	108	0	195
gen_async_assert.SigIntPing_A	79864	108	0	195
gen_fatal_assert.AlertState1_A	110914	6147	0	0
gen_fatal_assert.AlertState2_A	110914	44205	0	0
gen_fatal_assert.AlertState3_A	110914	4110	0	0
gen_recov_assert.AlertState1_A	41589	6630	0	0
gen_recov_assert.AlertState2_A	41589	0	0	0
gen_sync_assert.DiffEncoding_A	72639	50812	0	0
gen_sync_assert.InBandInitFsm_A	72639	0	0	0
gen_sync_assert.InBandInitPing_A	72639	0	0	0
gen_sync_assert.PingHs_A	72639	368	0	0
gen_sync_assert.SigIntAck_A	72639	0	0	0
gen_sync_assert.SigIntPing_A	72639	0	0	0

AlertHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152503	1082	0	0
T1	1090	14	0	0
T2	1191	17	0	0
T3	1148	14	0	0
T7	1113	14	0	0
T8	1187	12	0	0
T9	1112	16	0	0
T11	1216	15	0	0
T12	1287	18	0	0
T18	1159	13	0	0
T19	1088	14	0	0

AlertPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152503	116159	0	0
T1	1090	998	0	0
T2	1191	1103	0	0
T3	1148	1059	0	0
T7	1113	1034	0	0
T8	1187	1015	0	0
T9	1112	1041	0	0
T11	1216	1056	0	0
T12	1287	1149	0	0
T18	1159	1081	0	0
T19	1088	1022	0	0

AlertState0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152503	116159	0	0
T1	1090	998	0	0
T2	1191	1103	0	0
T3	1148	1059	0	0
T7	1113	1034	0	0
T8	1187	1015	0	0
T9	1112	1041	0	0
T11	1216	1056	0	0
T12	1287	1149	0	0
T18	1159	1081	0	0
T19	1088	1022	0	0

AlertTest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152503	79	0	0
T1	1090	1	0	0
T2	1191	1	0	0
T3	1148	1	0	0
T7	1113	1	0	0
T8	1187	1	0	0
T9	1112	1	0	0
T11	1216	1	0	0
T12	1287	1	0	0
T18	1159	1	0	0
T19	1088	1	0	0

AlertTestHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152503	79	0	0
T1	1090	1	0	0
T2	1191	1	0	0
T3	1148	1	0	0
T7	1113	1	0	0
T8	1187	1	0	0
T9	1112	1	0	0
T11	1216	1	0	0
T12	1287	1	0	0
T18	1159	1	0	0
T19	1088	1	0	0

gen_async_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79864	54333	0	0
T1	1090	893	0	0
T2	1191	938	0	0
T3	1148	924	0	0
T7	1113	922	0	0
T8	1187	907	0	0
T9	1112	906	0	0
T11	1216	933	0	0
T12	1287	974	0	0
T18	1159	960	0	0
T19	1088	926	0	0

gen_async_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79864	108	0	156
T1	1090	3	0	4
T2	1191	2	0	4
T3	1148	3	0	4
T7	1113	3	0	4
T8	1187	3	0	4
T9	1112	3	0	4
T11	1216	4	0	4
T12	1287	3	0	4
T18	1159	3	0	4
T19	1088	3	0	4

gen_async_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79864	108	0	156
T1	1090	3	0	4
T2	1191	2	0	4
T3	1148	3	0	4
T7	1113	3	0	4
T8	1187	3	0	4
T9	1112	3	0	4
T11	1216	4	0	4
T12	1287	3	0	4
T18	1159	3	0	4
T19	1088	3	0	4

gen_async_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79864	368	0	0
T1	1090	9	0	0
T2	1191	10	0	0
T3	1148	7	0	0
T7	1113	10	0	0
T8	1187	10	0	0
T9	1112	9	0	0
T11	1216	11	0	0
T12	1287	9	0	0
T18	1159	9	0	0
T19	1088	11	0	0

gen_async_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79864	108	0	195
T1	1090	3	0	5
T2	1191	2	0	5
T3	1148	3	0	5
T7	1113	3	0	5
T8	1187	3	0	5
T9	1112	3	0	5
T11	1216	4	0	5
T12	1287	3	0	5
T18	1159	3	0	5
T19	1088	3	0	5

gen_async_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79864	108	0	195
T1	1090	3	0	5
T2	1191	2	0	5
T3	1148	3	0	5
T7	1113	3	0	5
T8	1187	3	0	5
T9	1112	3	0	5
T11	1216	4	0	5
T12	1287	3	0	5
T18	1159	3	0	5
T19	1088	3	0	5

gen_fatal_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110914	6147	0	0
T4	2991	294	0	0
T13	3080	300	0	0
T24	2953	234	0	0
T25	3006	240	0	0
T40	3156	221	0	0
T41	2911	268	0	0
T42	2903	261	0	0
T43	3062	230	0	0
T44	3049	223	0	0
T45	2969	221	0	0

gen_fatal_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110914	44205	0	0
T4	2991	1217	0	0
T13	3080	1310	0	0
T24	2953	1208	0	0
T25	3006	1178	0	0
T40	3156	1276	0	0
T41	2911	1188	0	0
T42	2903	1143	0	0
T43	3062	1289	0	0
T44	3049	1201	0	0
T45	2969	1265	0	0

gen_fatal_assert.AlertState3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110914	4110	0	0
T4	2991	61	0	0
T13	3080	63	0	0
T24	2953	61	0	0
T25	3006	60	0	0
T40	3156	68	0	0
T41	2911	59	0	0
T42	2903	57	0	0
T43	3062	67	0	0
T44	3049	62	0	0
T45	2969	65	0	0

gen_recov_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41589	6630	0	0
T1	1090	220	0	0
T2	1191	263	0	0
T3	1148	220	0	0
T7	1113	224	0	0
T8	1187	187	0	0
T9	1112	250	0	0
T11	1216	225	0	0
T12	1287	297	0	0
T18	1159	214	0	0
T19	1088	228	0	0

gen_recov_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41589	0	0	0

gen_sync_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72639	50812	0	0
T14	998	791	0	0
T26	848	736	0	0
T27	948	807	0	0
T28	907	745	0	0
T29	889	730	0	0
T30	976	809	0	0
T36	884	734	0	0
T37	994	852	0	0
T38	832	698	0	0
T39	895	773	0	0

gen_sync_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72639	0	0	0

gen_sync_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72639	0	0	0

gen_sync_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72639	368	0	0
T14	998	10	0	0
T26	848	9	0	0
T27	948	8	0	0
T28	907	9	0	0
T29	889	8	0	0
T30	976	8	0	0
T36	884	10	0	0
T37	994	10	0	0
T38	832	10	0	0
T39	895	10	0	0

gen_sync_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72639	0	0	0

gen_sync_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72639	0	0	0