Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_sender	95.52	100.00	100.00	100.00	100.00	95.83	77.27

---

Module Instance : prim_alert_tb.i_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	193	32	32	100.00
ALWAYS	276	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	1	1
145	1	1
146	1	1
163	1	1
167	1	1
171	1	1
172	1	1
175	1	1
177	1	1
178	1	1
182	1	1
183	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
214	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE
226	1	1
227	1	1
229	1	1
230	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
242	1	1
246	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
282	1	1
283	1	1
284	1	1
285	1	1

---

Cond Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (ack_sigint | ping_sigint)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (alert_req | alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (alert_clr ? 1'b0 : alert_req_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (alert_test_i | alert_test_set_q)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (alert_clr ? 1'b0 : alert_test_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (alert_req_trigger | alert_test_trigger)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       177
 EXPRESSION (ping_set_q | ping_event)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (ping_clr ? 1'b0 : ping_trigger)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       182
 EXPRESSION (alert_clr & alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       202
 EXPRESSION (alert_trigger || ping_trigger)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (alert_trigger ? AlertHsPhase1 : PingHsPhase1)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T11,T12	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_ack_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_alert_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertHsPhase1	203	Covered	T1,T2,T3
AlertHsPhase2	211	Covered	T1,T2,T3
Idle	246	Covered	T1,T2,T3
Pause0	220	Covered	T1,T2,T3
Pause1	242	Covered	T1,T2,T3
PingHsPhase1	203	Covered	T1,T2,T3
PingHsPhase2	227	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertHsPhase1->AlertHsPhase2	211	Covered	T1,T2,T3
AlertHsPhase1->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Pause0	220	Covered	T1,T2,T3
Idle->AlertHsPhase1	203	Covered	T1,T2,T3
Idle->PingHsPhase1	203	Covered	T1,T2,T3
Pause0->Idle	256	Covered	T39,T33,T35
Pause0->Pause1	242	Covered	T1,T2,T3
Pause1->Idle	246	Covered	T1,T2,T3
PingHsPhase1->Idle	256	Covered	T1,T2,T3
PingHsPhase1->PingHsPhase2	227	Covered	T1,T2,T3
PingHsPhase2->Idle	256	Covered	T2,T3,T7
PingHsPhase2->Pause0	237	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	172	2	2	100.00
TERNARY	178	2	2	100.00
TERNARY	167	2	2	100.00
CASE	199	14	13	92.86
IF	255	2	2	100.00
IF	276	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	(ping_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	199	case (state_q)
-2-:	202	if ((alert_trigger || ping_trigger))
-3-:	203	(alert_trigger) ? 
-4-:	210	if (ack_level)
-5-:	219	if ((!ack_level))
-6-:	226	if (ack_level)
-7-:	235	if ((!ack_level))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	1	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	0	-	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	1	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	0	-	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	1	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	0	-	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	1	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	0	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	255	if (sigint_detected)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	276	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	17	77.27
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	17	77.27

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertHs_A	156596	1104	0	0
AlertPKnownO_A	156596	118808	0	0
AlertState0_A	156596	118808	0	0
AlertTest1_A	156596	80	0	0
AlertTestHs_A	156596	80	0	0
gen_async_assert.DiffEncoding_A	82768	56590	0	5
gen_async_assert.InBandInitFsm_A	82768	115	0	153
gen_async_assert.InBandInitPing_A	82768	115	0	153
gen_async_assert.PingHs_A	82768	382	0	2
gen_async_assert.SigIntAck_A	82768	115	0	193
gen_async_assert.SigIntPing_A	82768	115	0	193
gen_fatal_assert.AlertState1_A	115395	6362	0	0
gen_fatal_assert.AlertState2_A	115395	46599	0	0
gen_fatal_assert.AlertState3_A	115395	4295	0	0
gen_recov_assert.AlertState1_A	41201	6582	0	0
gen_recov_assert.AlertState2_A	41201	0	0	0
gen_sync_assert.DiffEncoding_A	73828	51210	0	0
gen_sync_assert.InBandInitFsm_A	73828	0	0	0
gen_sync_assert.InBandInitPing_A	73828	0	0	0
gen_sync_assert.PingHs_A	73828	362	0	0
gen_sync_assert.SigIntAck_A	73828	0	0	0
gen_sync_assert.SigIntPing_A	73828	0	0	0

AlertHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156596	1104	0	0
T1	1196	19	0	0
T2	1106	14	0	0
T3	1166	18	0	0
T7	1081	14	0	0
T8	1096	14	0	0
T9	1110	19	0	0
T15	1072	15	0	0
T16	1057	15	0	0
T17	1146	16	0	0
T18	1067	17	0	0

AlertPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156596	118808	0	0
T1	1196	1045	0	0
T2	1106	1043	0	0
T3	1166	1089	0	0
T7	1081	995	0	0
T8	1096	1013	0	0
T9	1110	1051	0	0
T15	1072	1006	0	0
T16	1057	1006	0	0
T17	1146	1079	0	0
T18	1067	1013	0	0

AlertState0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156596	118808	0	0
T1	1196	1045	0	0
T2	1106	1043	0	0
T3	1166	1089	0	0
T7	1081	995	0	0
T8	1096	1013	0	0
T9	1110	1051	0	0
T15	1072	1006	0	0
T16	1057	1006	0	0
T17	1146	1079	0	0
T18	1067	1013	0	0

AlertTest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156596	80	0	0
T1	1196	1	0	0
T2	1106	1	0	0
T3	1166	1	0	0
T7	1081	1	0	0
T8	1096	1	0	0
T9	1110	1	0	0
T15	1072	1	0	0
T16	1057	1	0	0
T17	1146	1	0	0
T18	1067	1	0	0

AlertTestHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156596	80	0	0
T1	1196	1	0	0
T2	1106	1	0	0
T3	1166	1	0	0
T7	1081	1	0	0
T8	1096	1	0	0
T9	1110	1	0	0
T15	1072	1	0	0
T16	1057	1	0	0
T17	1146	1	0	0
T18	1067	1	0	0

gen_async_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82768	56590	0	5
T1	1196	896	0	0
T2	1106	939	0	0
T3	1166	934	0	0
T7	1081	881	0	0
T8	1096	906	0	0
T9	1110	897	0	0
T15	1072	893	0	0
T16	1057	915	0	0
T17	1146	933	0	0
T18	1067	914	0	0
T22	0	0	0	3
T40	0	0	0	2

gen_async_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82768	115	0	153
T1	1196	2	0	4
T2	1106	3	0	4
T3	1166	2	0	4
T7	1081	3	0	4
T8	1096	3	0	4
T9	1110	3	0	4
T15	1072	3	0	4
T16	1057	2	0	4
T17	1146	3	0	4
T18	1067	4	0	4

gen_async_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82768	115	0	153
T1	1196	2	0	4
T2	1106	3	0	4
T3	1166	2	0	4
T7	1081	3	0	4
T8	1096	3	0	4
T9	1110	3	0	4
T15	1072	3	0	4
T16	1057	2	0	4
T17	1146	3	0	4
T18	1067	4	0	4

gen_async_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82768	382	0	2
T1	1196	9	0	0
T2	1106	10	0	0
T3	1166	9	0	0
T7	1081	9	0	0
T8	1096	10	0	0
T9	1110	9	0	0
T15	1072	11	0	0
T16	1057	10	0	0
T17	1146	9	0	0
T18	1067	10	0	0
T22	0	0	0	1
T40	0	0	0	1

gen_async_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82768	115	0	193
T1	1196	2	0	5
T2	1106	3	0	5
T3	1166	2	0	5
T7	1081	3	0	5
T8	1096	3	0	5
T9	1110	3	0	5
T15	1072	3	0	5
T16	1057	2	0	5
T17	1146	3	0	5
T18	1067	4	0	5

gen_async_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82768	115	0	193
T1	1196	2	0	5
T2	1106	3	0	5
T3	1166	2	0	5
T7	1081	3	0	5
T8	1096	3	0	5
T9	1110	3	0	5
T15	1072	3	0	5
T16	1057	2	0	5
T17	1146	3	0	5
T18	1067	4	0	5

gen_fatal_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115395	6362	0	0
T4	2986	278	0	0
T13	3056	215	0	0
T22	2855	235	0	0
T41	3054	254	0	0
T42	3092	290	0	0
T43	3035	222	0	0
T44	3056	216	0	0
T45	2904	230	0	0
T46	3135	287	0	0
T47	2950	248	0	0

gen_fatal_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115395	46599	0	0
T4	2986	1222	0	0
T13	3056	1271	0	0
T22	2855	1188	0	0
T41	3054	1375	0	0
T42	3092	1291	0	0
T43	3035	1319	0	0
T44	3056	1270	0	0
T45	2904	1205	0	0
T46	3135	1272	0	0
T47	2950	1278	0	0

gen_fatal_assert.AlertState3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115395	4295	0	0
T4	2986	61	0	0
T13	3056	66	0	0
T22	2855	61	0	0
T41	3054	69	0	0
T42	3092	64	0	0
T43	3035	69	0	0
T44	3056	66	0	0
T45	2904	62	0	0
T46	3135	62	0	0
T47	2950	66	0	0

gen_recov_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41201	6582	0	0
T1	1196	283	0	0
T2	1106	215	0	0
T3	1166	302	0	0
T7	1081	214	0	0
T8	1096	209	0	0
T9	1110	285	0	0
T15	1072	232	0	0
T16	1057	229	0	0
T17	1146	265	0	0
T18	1067	268	0	0

gen_recov_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41201	0	0	0

gen_sync_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828	51210	0	0
T23	928	773	0	0
T24	970	807	0	0
T25	929	754	0	0
T32	897	757	0	0
T33	951	765	0	0
T34	866	747	0	0
T35	983	814	0	0
T36	889	702	0	0
T37	1076	818	0	0
T38	949	798	0	0

gen_sync_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828	0	0	0

gen_sync_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828	0	0	0

gen_sync_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828	362	0	0
T23	928	9	0	0
T24	970	7	0	0
T25	929	9	0	0
T32	897	9	0	0
T33	951	10	0	0
T34	866	10	0	0
T35	983	10	0	0
T36	889	10	0	0
T37	1076	10	0	0
T38	949	10	0	0

gen_sync_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828	0	0	0

gen_sync_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828	0	0	0