Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T2,T6,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T8,T9	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T3,T10
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T1,T9,T11
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T12,T13,T14
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T15,T16,T17

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	150161	113079	0	154
AlertKnownO_A	150831	114729	0	0
InBandInitRequest_A	150831	4066	0	0
InBandInitSequence_A	150831	424	0	0
InitReq_A	150831	757	0	0
IntegFailKnownO_A	150831	114729	0	0
NoSpuriousAlertsDuringInit_A	150831	16028	0	0
NoSpuriousPingOksDuringInit_A	150831	15679	0	0
PingDiffOk_A	149939	113837	0	0
PingOkBypassDuringInit_A	150831	45	0	40
PingOkKnownO_A	150831	114729	0	0
PingPKnownO_A	150831	114729	0	0
PingPending_A	150831	807	0	117
PingRequest0_A	150831	0	0	0
PingResponse0_A	150831	747	0	0
gen_async_assert.Alert_A	77340	1272	0	0
gen_async_assert.PingResponse1_A	77340	307	0	0
gen_async_assert.SigInt_A	77340	239	0	91
gen_sync_assert.Alert_A	73491	3213	0	0
gen_sync_assert.PingResponse1_A	73491	350	0	0
gen_sync_assert.SigInt_A	73491	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150161	113079	0	154
T1	1236	1085	0	2
T2	1071	994	0	2
T3	1139	1047	0	2
T6	1086	1018	0	2
T8	1162	1052	0	2
T9	1229	1045	0	2
T10	1136	1047	0	2
T15	1124	1042	0	2
T18	1032	968	0	2
T19	1090	1035	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	114729	0	0
T1	1252	1105	0	0
T2	1086	1011	0	0
T3	1153	1063	0	0
T6	1101	1035	0	0
T8	1178	1070	0	0
T9	1243	1063	0	0
T10	1150	1063	0	0
T15	1139	1059	0	0
T18	1046	984	0	0
T19	1104	1051	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	4066	0	0
T1	1252	65	0	0
T2	1086	43	0	0
T3	1153	49	0	0
T6	1101	75	0	0
T8	1178	73	0	0
T9	1243	33	0	0
T10	1150	83	0	0
T15	1139	50	0	0
T18	1046	46	0	0
T19	1104	65	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	424	0	0
T1	1252	1	0	0
T2	1086	0	0	0
T3	1153	1	0	0
T6	1101	4	0	0
T8	1178	5	0	0
T9	1243	1	0	0
T10	1150	4	0	0
T15	1139	3	0	0
T18	1046	2	0	0
T19	1104	3	0	0
T20	0	1	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	757	0	0
T1	1252	14	0	0
T2	1086	11	0	0
T3	1153	11	0	0
T6	1101	12	0	0
T8	1178	11	0	0
T9	1243	9	0	0
T10	1150	13	0	0
T15	1139	11	0	0
T18	1046	8	0	0
T19	1104	10	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	114729	0	0
T1	1252	1105	0	0
T2	1086	1011	0	0
T3	1153	1063	0	0
T6	1101	1035	0	0
T8	1178	1070	0	0
T9	1243	1063	0	0
T10	1150	1063	0	0
T15	1139	1059	0	0
T18	1046	984	0	0
T19	1104	1051	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	16028	0	0
T1	1252	287	0	0
T2	1086	212	0	0
T3	1153	216	0	0
T6	1101	233	0	0
T8	1178	220	0	0
T9	1243	186	0	0
T10	1150	253	0	0
T15	1139	210	0	0
T18	1046	160	0	0
T19	1104	199	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	15679	0	0
T1	1252	274	0	0
T2	1086	208	0	0
T3	1153	205	0	0
T6	1101	219	0	0
T8	1178	220	0	0
T9	1243	186	0	0
T10	1150	246	0	0
T15	1139	207	0	0
T18	1046	159	0	0
T19	1104	194	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149939	113837	0	0
T1	1239	1092	0	0
T2	1069	994	0	0
T3	1135	1045	0	0
T6	1084	1018	0	0
T8	1160	1052	0	0
T9	1230	1050	0	0
T10	1135	1048	0	0
T15	1125	1045	0	0
T18	1034	972	0	0
T19	1092	1039	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	45	0	40
T1	1252	1	0	0
T2	1086	0	0	0
T3	1153	0	0	0
T6	1101	0	0	0
T7	0	1	0	0
T8	1178	0	0	0
T9	1243	0	0	0
T10	1150	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	1139	1	0	0
T18	1046	1	0	0
T19	1104	1	0	0
T21	0	1	0	0
T22	0	4	0	0
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	114729	0	0
T1	1252	1105	0	0
T2	1086	1011	0	0
T3	1153	1063	0	0
T6	1101	1035	0	0
T8	1178	1070	0	0
T9	1243	1063	0	0
T10	1150	1063	0	0
T15	1139	1059	0	0
T18	1046	984	0	0
T19	1104	1051	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	114729	0	0
T1	1252	1105	0	0
T2	1086	1011	0	0
T3	1153	1063	0	0
T6	1101	1035	0	0
T8	1178	1070	0	0
T9	1243	1063	0	0
T10	1150	1063	0	0
T15	1139	1059	0	0
T18	1046	984	0	0
T19	1104	1051	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	807	0	117
T1	1252	11	0	1
T2	1086	11	0	1
T3	1153	11	0	1
T6	1101	11	0	1
T8	1178	11	0	1
T9	1243	11	0	1
T10	1150	11	0	1
T15	1139	11	0	1
T18	1046	11	0	1
T19	1104	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150831	747	0	0
T1	1252	10	0	0
T2	1086	9	0	0
T3	1153	10	0	0
T6	1101	9	0	0
T8	1178	10	0	0
T9	1243	10	0	0
T10	1150	10	0	0
T15	1139	10	0	0
T18	1046	10	0	0
T19	1104	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77340	1272	0	0
T1	1252	6	0	0
T2	1086	4	0	0
T3	1153	6	0	0
T6	1101	7	0	0
T8	1178	4	0	0
T9	1243	7	0	0
T10	1150	5	0	0
T15	1139	8	0	0
T18	1046	7	0	0
T19	1104	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77340	307	0	0
T1	1252	8	0	0
T2	1086	8	0	0
T3	1153	9	0	0
T6	1101	8	0	0
T8	1178	10	0	0
T9	1243	10	0	0
T10	1150	6	0	0
T15	1139	8	0	0
T18	1046	9	0	0
T19	1104	7	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77340	239	0	91
T1	1252	8	0	1
T2	1086	7	0	2
T3	1153	5	0	3
T6	1101	6	0	3
T8	1178	6	0	2
T9	1243	7	0	2
T10	1150	7	0	3
T15	1139	6	0	2
T18	1046	7	0	2
T19	1104	7	0	1

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73491	3213	0	0
T17	932	9	0	0
T23	929	8	0	0
T24	775	12	0	0
T25	895	9	0	0
T26	931	9	0	0
T27	863	11	0	0
T28	868	11	0	0
T33	944	9	0	0
T34	1007	8	0	0
T35	816	8	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73491	350	0	0
T17	932	9	0	0
T23	929	8	0	0
T24	775	9	0	0
T25	895	7	0	0
T26	931	8	0	0
T27	863	8	0	0
T28	868	7	0	0
T33	944	10	0	0
T34	1007	10	0	0
T35	816	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73491	40	0	0
T17	932	1	0	0
T23	929	1	0	0
T24	775	1	0	0
T25	895	1	0	0
T26	931	1	0	0
T27	863	1	0	0
T28	868	1	0	0
T33	944	1	0	0
T34	1007	1	0	0
T35	816	1	0	0