Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T13,T14

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T15,T10	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T3,T15,T8
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T16,T17,T18
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T7,T19,T20

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	154420	116107	0	158
AlertKnownO_A	155118	117805	0	0
InBandInitRequest_A	155118	4083	0	0
InBandInitSequence_A	155118	411	0	0
InitReq_A	155118	740	0	0
IntegFailKnownO_A	155118	117805	0	0
NoSpuriousAlertsDuringInit_A	155118	16064	0	0
NoSpuriousPingOksDuringInit_A	155118	15745	0	0
PingDiffOk_A	154241	116928	0	0
PingOkBypassDuringInit_A	155118	44	0	40
PingOkKnownO_A	155118	117805	0	0
PingPKnownO_A	155118	117805	0	0
PingPending_A	155118	826	0	119
PingRequest0_A	155118	0	0	0
PingResponse0_A	155118	764	0	0
gen_async_assert.Alert_A	82279	1402	0	0
gen_async_assert.PingResponse1_A	82279	318	0	0
gen_async_assert.SigInt_A	82279	245	0	83
gen_sync_assert.Alert_A	72839	3102	0	0
gen_sync_assert.PingResponse1_A	72839	345	0	0
gen_sync_assert.SigInt_A	72839	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154420	116107	0	158
T1	1191	1125	0	2
T2	1082	1019	0	2
T3	1194	1004	0	2
T7	1126	1042	0	2
T9	1008	933	0	2
T10	1151	1003	0	2
T15	1200	1051	0	2
T21	1091	1024	0	2
T22	1110	1057	0	2
T23	1063	1010	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	117805	0	0
T1	1204	1140	0	0
T2	1096	1035	0	0
T3	1209	1023	0	0
T7	1142	1060	0	0
T9	1022	949	0	0
T10	1165	1021	0	0
T15	1213	1068	0	0
T21	1107	1042	0	0
T22	1125	1074	0	0
T23	1078	1027	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	4083	0	0
T1	1204	104	0	0
T2	1096	66	0	0
T3	1209	51	0	0
T7	1142	76	0	0
T9	1022	36	0	0
T10	1165	46	0	0
T15	1213	41	0	0
T21	1107	43	0	0
T22	1125	57	0	0
T23	1078	58	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	411	0	0
T1	1204	6	0	0
T2	1096	5	0	0
T3	1209	1	0	0
T7	1142	7	0	0
T9	1022	2	0	0
T10	1165	2	0	0
T15	1213	1	0	0
T21	1107	2	0	0
T22	1125	3	0	0
T23	1078	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	740	0	0
T1	1204	14	0	0
T2	1096	11	0	0
T3	1209	8	0	0
T7	1142	9	0	0
T9	1022	6	0	0
T10	1165	8	0	0
T15	1213	11	0	0
T21	1107	10	0	0
T22	1125	10	0	0
T23	1078	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	117805	0	0
T1	1204	1140	0	0
T2	1096	1035	0	0
T3	1209	1023	0	0
T7	1142	1060	0	0
T9	1022	949	0	0
T10	1165	1021	0	0
T15	1213	1068	0	0
T21	1107	1042	0	0
T22	1125	1074	0	0
T23	1078	1027	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	16064	0	0
T1	1204	276	0	0
T2	1096	221	0	0
T3	1209	178	0	0
T7	1142	181	0	0
T9	1022	123	0	0
T10	1165	181	0	0
T15	1213	235	0	0
T21	1107	197	0	0
T22	1125	200	0	0
T23	1078	182	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	15745	0	0
T1	1204	272	0	0
T2	1096	214	0	0
T3	1209	176	0	0
T7	1142	180	0	0
T9	1022	106	0	0
T10	1165	165	0	0
T15	1213	233	0	0
T21	1107	193	0	0
T22	1125	198	0	0
T23	1078	180	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154241	116928	0	0
T1	1187	1123	0	0
T2	1082	1021	0	0
T3	1195	1009	0	0
T7	1128	1046	0	0
T9	1006	933	0	0
T10	1149	1005	0	0
T15	1196	1051	0	0
T21	1102	1037	0	0
T22	1109	1058	0	0
T23	1061	1010	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	44	0	40
T1	1204	1	0	0
T2	1096	1	0	0
T3	1209	0	0	0
T4	0	0	0	1
T7	1142	0	0	0
T9	1022	1	0	0
T10	1165	1	0	0
T15	1213	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	0	2	0	0
T21	1107	0	0	0
T22	1125	0	0	0
T23	1078	0	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	117805	0	0
T1	1204	1140	0	0
T2	1096	1035	0	0
T3	1209	1023	0	0
T7	1142	1060	0	0
T9	1022	949	0	0
T10	1165	1021	0	0
T15	1213	1068	0	0
T21	1107	1042	0	0
T22	1125	1074	0	0
T23	1078	1027	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	117805	0	0
T1	1204	1140	0	0
T2	1096	1035	0	0
T3	1209	1023	0	0
T7	1142	1060	0	0
T9	1022	949	0	0
T10	1165	1021	0	0
T15	1213	1068	0	0
T21	1107	1042	0	0
T22	1125	1074	0	0
T23	1078	1027	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	826	0	119
T1	1204	11	0	1
T2	1096	11	0	1
T3	1209	11	0	1
T7	1142	11	0	1
T9	1022	11	0	1
T10	1165	11	0	1
T15	1213	11	0	1
T21	1107	10	0	1
T22	1125	11	0	1
T23	1078	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155118	764	0	0
T1	1204	9	0	0
T2	1096	10	0	0
T3	1209	10	0	0
T7	1142	9	0	0
T9	1022	10	0	0
T10	1165	10	0	0
T15	1213	10	0	0
T21	1107	10	0	0
T22	1125	10	0	0
T23	1078	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82279	1402	0	0
T1	1204	4	0	0
T2	1096	7	0	0
T3	1209	7	0	0
T7	1142	8	0	0
T9	1022	10	0	0
T10	1165	9	0	0
T15	1213	5	0	0
T21	1107	6	0	0
T22	1125	6	0	0
T23	1078	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82279	318	0	0
T1	1204	7	0	0
T2	1096	6	0	0
T3	1209	9	0	0
T7	1142	9	0	0
T9	1022	8	0	0
T10	1165	7	0	0
T15	1213	9	0	0
T21	1107	8	0	0
T22	1125	9	0	0
T23	1078	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82279	245	0	83
T1	1204	5	0	2
T2	1096	6	0	3
T3	1209	6	0	3
T7	1142	6	0	2
T9	1022	7	0	2
T10	1165	5	0	2
T11	0	0	0	2
T15	1213	7	0	3
T21	1107	8	0	0
T22	1125	8	0	2
T23	1078	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72839	3102	0	0
T12	1015	10	0	0
T13	927	10	0	0
T14	1040	10	0	0
T27	959	7	0	0
T28	912	11	0	0
T36	923	9	0	0
T37	944	11	0	0
T38	925	10	0	0
T39	1008	8	0	0
T40	962	13	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72839	345	0	0
T12	1015	9	0	0
T13	927	9	0	0
T14	1040	8	0	0
T27	959	9	0	0
T28	912	9	0	0
T36	923	9	0	0
T37	944	8	0	0
T38	925	9	0	0
T39	1008	10	0	0
T40	962	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72839	40	0	0
T12	1015	1	0	0
T13	927	1	0	0
T14	1040	1	0	0
T27	959	1	0	0
T28	912	1	0	0
T36	923	1	0	0
T37	944	1	0	0
T38	925	1	0	0
T39	1008	1	0	0
T40	962	1	0	0