Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T7

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T6	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T6,T5,T8
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T9,T10,T11
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T2,T5,T12

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	152753	115221	0	158
AlertKnownO_A	153450	116888	0	0
InBandInitRequest_A	153450	4214	0	0
InBandInitSequence_A	153450	414	0	0
InitReq_A	153450	781	0	0
IntegFailKnownO_A	153450	116888	0	0
NoSpuriousAlertsDuringInit_A	153450	16390	0	0
NoSpuriousPingOksDuringInit_A	153450	15981	0	0
PingDiffOk_A	152516	115954	0	0
PingOkBypassDuringInit_A	153450	49	0	40
PingOkKnownO_A	153450	116888	0	0
PingPKnownO_A	153450	116888	0	0
PingPending_A	153450	829	0	119
PingRequest0_A	153450	0	0	0
PingResponse0_A	153450	767	0	0
gen_async_assert.Alert_A	79800	1320	0	0
gen_async_assert.PingResponse1_A	79800	325	0	0
gen_async_assert.SigInt_A	79800	239	0	93
gen_sync_assert.Alert_A	73650	3156	0	0
gen_sync_assert.PingResponse1_A	73650	357	0	0
gen_sync_assert.SigInt_A	73650	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152753	115221	0	158
T1	1044	971	0	2
T2	1176	1012	0	2
T3	1180	1014	0	2
T5	1119	976	0	2
T6	1175	1027	0	2
T13	1098	1010	0	2
T14	1158	1062	0	2
T15	1035	981	0	2
T16	1123	964	0	2
T17	1102	1013	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	116888	0	0
T1	1058	987	0	0
T2	1192	1031	0	0
T3	1195	1033	0	0
T5	1133	994	0	0
T6	1190	1046	0	0
T13	1114	1028	0	0
T14	1173	1079	0	0
T15	1049	997	0	0
T16	1139	984	0	0
T17	1116	1029	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	4214	0	0
T1	1058	47	0	0
T2	1192	51	0	0
T3	1195	41	0	0
T5	1133	38	0	0
T6	1190	52	0	0
T13	1114	30	0	0
T14	1173	72	0	0
T15	1049	40	0	0
T16	1139	31	0	0
T17	1116	53	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	414	0	0
T1	1058	1	0	0
T2	1192	1	0	0
T3	1195	3	0	0
T5	1133	0	0	0
T6	1190	2	0	0
T13	1114	1	0	0
T14	1173	1	0	0
T15	1049	1	0	0
T16	1139	2	0	0
T17	1116	1	0	0
T18	0	1	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	781	0	0
T1	1058	8	0	0
T2	1192	10	0	0
T3	1195	8	0	0
T5	1133	8	0	0
T6	1190	10	0	0
T13	1114	9	0	0
T14	1173	12	0	0
T15	1049	7	0	0
T16	1139	6	0	0
T17	1116	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	116888	0	0
T1	1058	987	0	0
T2	1192	1031	0	0
T3	1195	1033	0	0
T5	1133	994	0	0
T6	1190	1046	0	0
T13	1114	1028	0	0
T14	1173	1079	0	0
T15	1049	997	0	0
T16	1139	984	0	0
T17	1116	1029	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	16390	0	0
T1	1058	162	0	0
T2	1192	204	0	0
T3	1195	171	0	0
T5	1133	176	0	0
T6	1190	207	0	0
T13	1114	175	0	0
T14	1173	233	0	0
T15	1049	149	0	0
T16	1139	147	0	0
T17	1116	187	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	15981	0	0
T1	1058	151	0	0
T2	1192	202	0	0
T3	1195	154	0	0
T5	1133	169	0	0
T6	1190	198	0	0
T13	1114	159	0	0
T14	1173	231	0	0
T15	1049	149	0	0
T16	1139	143	0	0
T17	1116	187	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152516	115954	0	0
T1	1041	970	0	0
T2	1174	1013	0	0
T3	1180	1018	0	0
T5	1118	979	0	0
T6	1172	1028	0	0
T13	1095	1009	0	0
T14	1157	1063	0	0
T15	1032	980	0	0
T16	1123	968	0	0
T17	1105	1018	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	49	0	40
T1	1058	1	0	0
T2	1192	1	0	0
T3	1195	0	0	0
T5	1133	0	0	0
T6	1190	1	0	0
T7	0	0	0	1
T10	0	2	0	0
T11	0	0	0	1
T13	1114	0	0	0
T14	1173	0	0	0
T15	1049	0	0	0
T16	1139	0	0	0
T17	1116	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	116888	0	0
T1	1058	987	0	0
T2	1192	1031	0	0
T3	1195	1033	0	0
T5	1133	994	0	0
T6	1190	1046	0	0
T13	1114	1028	0	0
T14	1173	1079	0	0
T15	1049	997	0	0
T16	1139	984	0	0
T17	1116	1029	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	116888	0	0
T1	1058	987	0	0
T2	1192	1031	0	0
T3	1195	1033	0	0
T5	1133	994	0	0
T6	1190	1046	0	0
T13	1114	1028	0	0
T14	1173	1079	0	0
T15	1049	997	0	0
T16	1139	984	0	0
T17	1116	1029	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	829	0	119
T1	1058	11	0	1
T2	1192	11	0	1
T3	1195	11	0	1
T5	1133	11	0	1
T6	1190	11	0	1
T13	1114	11	0	1
T14	1173	11	0	1
T15	1049	11	0	1
T16	1139	11	0	1
T17	1116	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153450	767	0	0
T1	1058	10	0	0
T2	1192	9	0	0
T3	1195	9	0	0
T5	1133	8	0	0
T6	1190	10	0	0
T13	1114	9	0	0
T14	1173	10	0	0
T15	1049	10	0	0
T16	1139	10	0	0
T17	1116	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79800	1320	0	0
T1	1058	8	0	0
T2	1192	8	0	0
T3	1195	8	0	0
T5	1133	10	0	0
T6	1190	8	0	0
T13	1114	8	0	0
T14	1173	9	0	0
T15	1049	6	0	0
T16	1139	8	0	0
T17	1116	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79800	325	0	0
T1	1058	9	0	0
T2	1192	8	0	0
T3	1195	9	0	0
T5	1133	6	0	0
T6	1190	9	0	0
T13	1114	9	0	0
T14	1173	9	0	0
T15	1049	10	0	0
T16	1139	8	0	0
T17	1116	10	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79800	239	0	93
T1	1058	6	0	3
T2	1192	8	0	3
T3	1195	6	0	2
T5	1133	5	0	2
T6	1190	6	0	2
T13	1114	6	0	3
T14	1173	6	0	2
T15	1049	8	0	2
T16	1139	8	0	2
T17	1116	6	0	0
T18	0	0	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73650	3156	0	0
T7	966	9	0	0
T11	937	10	0	0
T24	930	12	0	0
T25	873	10	0	0
T26	1057	7	0	0
T27	952	10	0	0
T32	979	6	0	0
T33	801	9	0	0
T34	859	10	0	0
T35	862	7	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73650	357	0	0
T7	966	8	0	0
T11	937	8	0	0
T24	930	8	0	0
T25	873	7	0	0
T26	1057	9	0	0
T27	952	9	0	0
T32	979	10	0	0
T33	801	10	0	0
T34	859	10	0	0
T35	862	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73650	40	0	0
T7	966	1	0	0
T11	937	1	0	0
T24	930	1	0	0
T25	873	1	0	0
T26	1057	1	0	0
T27	952	1	0	0
T32	979	1	0	0
T33	801	1	0	0
T34	859	1	0	0
T35	862	1	0	0