Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T13,T14	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T3,T9
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T3,T13,T14
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T14,T15,T16
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T17,T18,T19

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	150101	113413	0	156
AlertKnownO_A	150781	115042	0	0
InBandInitRequest_A	150781	4171	0	0
InBandInitSequence_A	150781	445	0	0
InitReq_A	150781	750	0	0
IntegFailKnownO_A	150781	115042	0	0
NoSpuriousAlertsDuringInit_A	150781	15616	0	0
NoSpuriousPingOksDuringInit_A	150781	15357	0	0
PingDiffOk_A	149876	114137	0	0
PingOkBypassDuringInit_A	150781	42	0	40
PingOkKnownO_A	150781	115042	0	0
PingPKnownO_A	150781	115042	0	0
PingPending_A	150781	817	0	118
PingRequest0_A	150781	0	0	0
PingResponse0_A	150781	763	0	0
gen_async_assert.Alert_A	76338	1266	0	0
gen_async_assert.PingResponse1_A	76338	316	0	0
gen_async_assert.SigInt_A	76338	225	0	93
gen_sync_assert.Alert_A	74443	3226	0	0
gen_sync_assert.PingResponse1_A	74443	360	0	0
gen_sync_assert.SigInt_A	74443	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150101	113413	0	156
T1	1047	976	0	2
T2	1051	956	0	2
T3	1107	962	0	2
T7	1081	1017	0	2
T8	1097	1037	0	2
T9	1061	999	0	2
T10	1059	982	0	2
T17	1162	1087	0	2
T20	1032	939	0	2
T21	1163	1079	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	115042	0	0
T1	1062	993	0	0
T2	1066	973	0	0
T3	1122	981	0	0
T7	1096	1034	0	0
T8	1111	1053	0	0
T9	1076	1016	0	0
T10	1075	1000	0	0
T17	1177	1104	0	0
T20	1047	956	0	0
T21	1178	1096	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	4171	0	0
T1	1062	47	0	0
T2	1066	12	0	0
T3	1122	34	0	0
T7	1096	45	0	0
T8	1111	55	0	0
T9	1076	33	0	0
T10	1075	51	0	0
T17	1177	86	0	0
T20	1047	20	0	0
T21	1178	57	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	445	0	0
T1	1062	1	0	0
T2	1066	0	0	0
T3	1122	1	0	0
T7	1096	1	0	0
T8	1111	2	0	0
T9	1076	0	0	0
T10	1075	4	0	0
T11	0	4	0	0
T17	1177	4	0	0
T20	1047	1	0	0
T21	1178	3	0	0
T22	0	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	750	0	0
T1	1062	8	0	0
T2	1066	5	0	0
T3	1122	6	0	0
T7	1096	10	0	0
T8	1111	11	0	0
T9	1076	7	0	0
T10	1075	8	0	0
T17	1177	14	0	0
T20	1047	4	0	0
T21	1178	11	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	115042	0	0
T1	1062	993	0	0
T2	1066	973	0	0
T3	1122	981	0	0
T7	1096	1034	0	0
T8	1111	1053	0	0
T9	1076	1016	0	0
T10	1075	1000	0	0
T17	1177	1104	0	0
T20	1047	956	0	0
T21	1178	1096	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	15616	0	0
T1	1062	163	0	0
T2	1066	109	0	0
T3	1122	146	0	0
T7	1096	201	0	0
T8	1111	224	0	0
T9	1076	141	0	0
T10	1075	168	0	0
T17	1177	275	0	0
T20	1047	88	0	0
T21	1178	212	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	15357	0	0
T1	1062	161	0	0
T2	1066	107	0	0
T3	1122	144	0	0
T7	1096	199	0	0
T8	1111	219	0	0
T9	1076	121	0	0
T10	1075	149	0	0
T17	1177	266	0	0
T20	1047	88	0	0
T21	1178	211	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149876	114137	0	0
T1	1046	977	0	0
T2	1050	957	0	0
T3	1105	964	0	0
T7	1077	1015	0	0
T8	1096	1038	0	0
T9	1058	998	0	0
T10	1058	983	0	0
T17	1161	1088	0	0
T20	1031	940	0	0
T21	1167	1085	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	42	0	40
T1	1062	2	0	0
T2	1066	0	0	0
T3	1122	0	0	0
T7	1096	1	0	0
T8	1111	0	0	0
T9	1076	0	0	0
T10	1075	0	0	0
T11	0	2	0	0
T13	0	1	0	0
T15	0	1	0	0
T17	1177	0	0	0
T19	0	1	0	0
T20	1047	0	0	0
T21	1178	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	2	0	0
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	115042	0	0
T1	1062	993	0	0
T2	1066	973	0	0
T3	1122	981	0	0
T7	1096	1034	0	0
T8	1111	1053	0	0
T9	1076	1016	0	0
T10	1075	1000	0	0
T17	1177	1104	0	0
T20	1047	956	0	0
T21	1178	1096	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	115042	0	0
T1	1062	993	0	0
T2	1066	973	0	0
T3	1122	981	0	0
T7	1096	1034	0	0
T8	1111	1053	0	0
T9	1076	1016	0	0
T10	1075	1000	0	0
T17	1177	1104	0	0
T20	1047	956	0	0
T21	1178	1096	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	817	0	118
T1	1062	11	0	1
T2	1066	11	0	1
T3	1122	11	0	1
T7	1096	11	0	1
T8	1111	11	0	1
T9	1076	11	0	1
T10	1075	11	0	1
T17	1177	11	0	1
T20	1047	11	0	1
T21	1178	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150781	763	0	0
T1	1062	10	0	0
T2	1066	10	0	0
T3	1122	8	0	0
T7	1096	9	0	0
T8	1111	9	0	0
T9	1076	10	0	0
T10	1075	9	0	0
T17	1177	9	0	0
T20	1047	10	0	0
T21	1178	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76338	1266	0	0
T1	1062	7	0	0
T2	1066	9	0	0
T3	1122	10	0	0
T7	1096	6	0	0
T8	1111	7	0	0
T9	1076	10	0	0
T10	1075	9	0	0
T17	1177	6	0	0
T20	1047	9	0	0
T21	1178	8	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76338	316	0	0
T1	1062	8	0	0
T2	1066	9	0	0
T3	1122	8	0	0
T7	1096	8	0	0
T8	1111	7	0	0
T9	1076	10	0	0
T10	1075	8	0	0
T17	1177	5	0	0
T20	1047	10	0	0
T21	1178	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76338	225	0	93
T1	1062	7	0	3
T2	1066	7	0	2
T3	1122	5	0	2
T7	1096	5	0	3
T8	1111	6	0	2
T9	1076	6	0	3
T10	1075	6	0	3
T17	1177	5	0	2
T20	1047	7	0	3
T21	1178	6	0	1

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74443	3226	0	0
T25	977	10	0	0
T26	931	7	0	0
T27	889	10	0	0
T35	919	8	0	0
T36	813	12	0	0
T37	899	9	0	0
T38	1022	8	0	0
T39	943	9	0	0
T40	964	7	0	0
T41	991	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74443	360	0	0
T25	977	8	0	0
T26	931	9	0	0
T27	889	8	0	0
T35	919	10	0	0
T36	813	9	0	0
T37	899	9	0	0
T38	1022	10	0	0
T39	943	10	0	0
T40	964	10	0	0
T41	991	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74443	40	0	0
T25	977	1	0	0
T26	931	1	0	0
T27	889	1	0	0
T35	919	1	0	0
T36	813	1	0	0
T37	899	1	0	0
T38	1022	1	0	0
T39	943	1	0	0
T40	964	1	0	0
T41	991	1	0	0