Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.18 100.00 100.00 100.00 80.00 95.83 95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_alert_tb.i_alert_receiver 95.18 100.00 100.00 100.00 80.00 95.83 95.24



Module Instance : prim_alert_tb.i_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.18 100.00 100.00 100.00 80.00 95.83 95.24


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.18 100.00 100.00 100.00 80.00 95.83 95.24


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_alert_tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_alert_receiver
Line No.TotalCoveredPercent
TOTAL6060100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
ALWAYS1594343100.00
ALWAYS25377100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
106 1 1
107 1 1
111 1 1
112 1 1
144 1 1
147 1 1
148 1 1
150 1 1
151 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
166 1 1
168 1 1
171 1 1
172 1 1
173 1 1
175 1 1
176 1 1
178 1 1
MISSING_ELSE
184 1 1
185 1 1
187 1 1
191 1 1
192 1 1
197 1 1
199 1 1
204 1 1
205 1 1
208 1 1
209 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
223 1 1
MISSING_ELSE
231 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
242 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
MISSING_ELSE
MISSING_ELSE
253 1 1
256 1 1
257 1 1
258 1 1
260 1 1
261 1 1
262 1 1


Cond Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------
-1--2--3-StatusTests
011CoveredT4,T5
101CoveredT2,T6,T7
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T8
10CoveredT9,T10

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T8,T11,T12 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ping_ok_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
integ_fail_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT


FSM Coverage for Module : prim_alert_receiver
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 15 12 80.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
HsAckWait 172 Covered T1,T2,T3
Idle 192 Covered T1,T2,T3
InitAckWait 209 Covered T1,T2,T3
InitReq 234 Covered T1,T2,T3
Pause0 185 Covered T1,T2,T3
Pause1 191 Covered T1,T2,T3


transitionsLine No.CoveredTests
HsAckWait->Idle 243 Covered T1,T2,T3
HsAckWait->InitReq 234 Covered T2,T3,T8
HsAckWait->Pause0 185 Covered T1,T2,T3
Idle->HsAckWait 172 Covered T1,T2,T3
Idle->InitReq 234 Covered T1,T2,T3
InitAckWait->Idle 243 Not Covered
InitAckWait->InitReq 234 Covered T13,T6,T14
InitAckWait->Pause0 219 Covered T1,T2,T3
InitReq->Idle 243 Not Covered
InitReq->InitAckWait 209 Covered T1,T2,T3
Pause0->Idle 243 Not Covered
Pause0->InitReq 234 Covered T15,T12,T16
Pause0->Pause1 191 Covered T1,T2,T3
Pause1->Idle 192 Covered T1,T2,T3
Pause1->InitReq 234 Covered T8,T17,T11



Branch Coverage for Module : prim_alert_receiver
Line No.TotalCoveredPercent
Branches 24 23 95.83
TERNARY 107 3 3 100.00
TERNARY 111 2 2 100.00
CASE 168 13 12 92.31
IF 231 4 4 100.00
IF 253 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 107 (send_init) ? -2-: 107 (send_ping) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 (send_init) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 168 case (state_q) -2-: 171 if (alert_level) -3-: 175 if (ping_pending_q) -4-: 184 if ((!alert_level)) -5-: 204 if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i)) -6-: 208 if (alert_sigint) -7-: 218 if ((!alert_sigint))

Branches:
-1--2--3--4--5--6--7-StatusTests
Idle 1 1 - - - - Covered T1,T2,T3
Idle 1 0 - - - - Covered T1,T2,T3
Idle 0 - - - - - Covered T1,T2,T3
HsAckWait - - 1 - - - Covered T1,T2,T3
HsAckWait - - 0 - - - Covered T1,T2,T3
Pause0 - - - - - - Covered T1,T2,T3
Pause1 - - - - - - Covered T1,T2,T3
InitReq - - - 1 - - Covered T1,T2,T3
InitReq - - - 0 1 - Covered T1,T2,T3
InitReq - - - 0 0 - Covered T1,T2,T3
InitAckWait - - - - - 1 Covered T1,T2,T3
InitAckWait - - - - - 0 Covered T1,T2,T3
default - - - - - - Not Covered


LineNo. Expression -1-: 231 if ((!(state_q inside {InitReq, InitAckWait}))) -2-: 233 if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i)) -3-: 242 if (alert_sigint)

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 1 Covered T1,T2,T3
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_alert_receiver
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 21 21 100.00 20 95.24
Cover properties 0 0 0
Cover sequences 0 0 0
Total 21 21 100.00 20 95.24




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckDiffOk_A 155091 116761 0 160
AlertKnownO_A 155803 118471 0 0
InBandInitRequest_A 155803 4030 0 0
InBandInitSequence_A 155803 387 0 0
InitReq_A 155803 740 0 0
IntegFailKnownO_A 155803 118471 0 0
NoSpuriousAlertsDuringInit_A 155803 16324 0 0
NoSpuriousPingOksDuringInit_A 155803 15928 0 0
PingDiffOk_A 154898 117566 0 0
PingOkBypassDuringInit_A 155803 41 0 40
PingOkKnownO_A 155803 118471 0 0
PingPKnownO_A 155803 118471 0 0
PingPending_A 155803 840 0 120
PingRequest0_A 155803 0 0 0
PingResponse0_A 155803 774 0 0
gen_async_assert.Alert_A 82492 1357 0 0
gen_async_assert.PingResponse1_A 82492 330 0 0
gen_async_assert.SigInt_A 82492 246 0 98
gen_sync_assert.Alert_A 73311 3215 0 0
gen_sync_assert.PingResponse1_A 73311 348 0 0
gen_sync_assert.SigInt_A 73311 40 0 0


AckDiffOk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155091 116761 0 160
T1 1117 1062 0 2
T2 1080 996 0 2
T3 1087 1001 0 2
T8 1194 1014 0 2
T11 1159 1014 0 2
T12 1236 1071 0 2
T15 1095 1026 0 2
T17 1186 1114 0 2
T18 1135 1059 0 2
T19 1059 974 0 2

AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 118471 0 0
T1 1132 1079 0 0
T2 1095 1013 0 0
T3 1101 1017 0 0
T8 1208 1032 0 0
T11 1174 1033 0 0
T12 1252 1091 0 0
T15 1111 1044 0 0
T17 1199 1129 0 0
T18 1150 1076 0 0
T19 1075 992 0 0

InBandInitRequest_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 4030 0 0
T1 1132 38 0 0
T2 1095 52 0 0
T3 1101 53 0 0
T8 1208 47 0 0
T11 1174 44 0 0
T12 1252 66 0 0
T15 1111 59 0 0
T17 1199 76 0 0
T18 1150 53 0 0
T19 1075 44 0 0

InBandInitSequence_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 387 0 0
T1 1132 1 0 0
T2 1095 2 0 0
T3 1101 2 0 0
T8 1208 2 0 0
T11 1174 3 0 0
T12 1252 3 0 0
T13 0 3 0 0
T15 1111 4 0 0
T17 1199 2 0 0
T18 1150 0 0 0
T19 1075 0 0 0
T20 0 3 0 0

InitReq_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 740 0 0
T1 1132 9 0 0
T2 1095 10 0 0
T3 1101 9 0 0
T8 1208 8 0 0
T11 1174 10 0 0
T12 1252 11 0 0
T15 1111 9 0 0
T17 1199 12 0 0
T18 1150 11 0 0
T19 1075 7 0 0

IntegFailKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 118471 0 0
T1 1132 1079 0 0
T2 1095 1013 0 0
T3 1101 1017 0 0
T8 1208 1032 0 0
T11 1174 1033 0 0
T12 1252 1091 0 0
T15 1111 1044 0 0
T17 1199 1129 0 0
T18 1150 1076 0 0
T19 1075 992 0 0

NoSpuriousAlertsDuringInit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 16324 0 0
T1 1132 180 0 0
T2 1095 190 0 0
T3 1101 175 0 0
T8 1208 172 0 0
T11 1174 201 0 0
T12 1252 229 0 0
T15 1111 179 0 0
T17 1199 237 0 0
T18 1150 219 0 0
T19 1075 149 0 0

NoSpuriousPingOksDuringInit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 15928 0 0
T1 1132 178 0 0
T2 1095 173 0 0
T3 1101 157 0 0
T8 1208 161 0 0
T11 1174 198 0 0
T12 1252 227 0 0
T15 1111 173 0 0
T17 1199 237 0 0
T18 1150 217 0 0
T19 1075 147 0 0

PingDiffOk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 154898 117566 0 0
T1 1118 1065 0 0
T2 1080 998 0 0
T3 1083 999 0 0
T8 1190 1014 0 0
T11 1159 1018 0 0
T12 1236 1075 0 0
T15 1097 1030 0 0
T17 1184 1114 0 0
T18 1134 1060 0 0
T19 1063 980 0 0

PingOkBypassDuringInit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 41 0 40
T2 1095 1 0 0
T3 1101 0 0 0
T4 0 0 0 1
T6 0 1 0 0
T7 0 1 0 0
T8 1208 0 0 0
T9 0 0 0 1
T11 1174 1 0 0
T12 1252 0 0 0
T15 1111 0 0 0
T16 0 1 0 0
T17 1199 0 0 0
T18 1150 0 0 0
T19 1075 0 0 0
T20 1083 0 0 0
T21 0 1 0 0
T22 0 1 0 0
T23 0 1 0 0
T24 0 1 0 0
T25 0 2 0 0
T26 0 0 0 1
T27 0 0 0 1
T28 0 0 0 1
T29 0 0 0 1
T30 0 0 0 1
T31 0 0 0 1
T32 0 0 0 1
T33 0 0 0 1

PingOkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 118471 0 0
T1 1132 1079 0 0
T2 1095 1013 0 0
T3 1101 1017 0 0
T8 1208 1032 0 0
T11 1174 1033 0 0
T12 1252 1091 0 0
T15 1111 1044 0 0
T17 1199 1129 0 0
T18 1150 1076 0 0
T19 1075 992 0 0

PingPKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 118471 0 0
T1 1132 1079 0 0
T2 1095 1013 0 0
T3 1101 1017 0 0
T8 1208 1032 0 0
T11 1174 1033 0 0
T12 1252 1091 0 0
T15 1111 1044 0 0
T17 1199 1129 0 0
T18 1150 1076 0 0
T19 1075 992 0 0

PingPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 840 0 120
T1 1132 11 0 1
T2 1095 11 0 1
T3 1101 11 0 1
T8 1208 11 0 1
T11 1174 11 0 1
T12 1252 11 0 1
T15 1111 11 0 1
T17 1199 11 0 1
T18 1150 11 0 1
T19 1075 11 0 1

PingRequest0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 0 0 0

PingResponse0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155803 774 0 0
T1 1132 10 0 0
T2 1095 9 0 0
T3 1101 10 0 0
T8 1208 10 0 0
T11 1174 10 0 0
T12 1252 10 0 0
T15 1111 10 0 0
T17 1199 10 0 0
T18 1150 10 0 0
T19 1075 10 0 0

gen_async_assert.Alert_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 82492 1357 0 0
T1 1132 7 0 0
T2 1095 8 0 0
T3 1101 7 0 0
T8 1208 9 0 0
T11 1174 7 0 0
T12 1252 4 0 0
T15 1111 8 0 0
T17 1199 7 0 0
T18 1150 6 0 0
T19 1075 9 0 0

gen_async_assert.PingResponse1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 82492 330 0 0
T1 1132 9 0 0
T2 1095 8 0 0
T3 1101 10 0 0
T8 1208 10 0 0
T11 1174 8 0 0
T12 1252 9 0 0
T15 1111 7 0 0
T17 1199 10 0 0
T18 1150 9 0 0
T19 1075 9 0 0

gen_async_assert.SigInt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 82492 246 0 98
T1 1132 5 0 3
T2 1095 5 0 2
T3 1101 5 0 3
T8 1208 5 0 2
T11 1174 8 0 2
T12 1252 7 0 2
T15 1111 6 0 2
T17 1199 6 0 2
T18 1150 8 0 3
T19 1075 6 0 2

gen_sync_assert.Alert_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73311 3215 0 0
T9 947 10 0 0
T26 895 10 0 0
T27 940 12 0 0
T28 1008 9 0 0
T29 814 10 0 0
T34 938 10 0 0
T35 877 13 0 0
T36 927 11 0 0
T37 885 10 0 0
T38 913 10 0 0

gen_sync_assert.PingResponse1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73311 348 0 0
T9 947 7 0 0
T26 895 7 0 0
T27 940 9 0 0
T28 1008 6 0 0
T29 814 9 0 0
T34 938 7 0 0
T35 877 10 0 0
T36 927 7 0 0
T37 885 10 0 0
T38 913 9 0 0

gen_sync_assert.SigInt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73311 40 0 0
T9 947 1 0 0
T26 895 1 0 0
T27 940 1 0 0
T28 1008 1 0 0
T29 814 1 0 0
T34 938 1 0 0
T35 877 1 0 0
T36 927 1 0 0
T37 885 1 0 0
T38 913 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%