Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T7,T10	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T1,T7,T10
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T2,T11,T10
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T2,T3,T8

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	153498	115234	0	158
AlertKnownO_A	154198	116909	0	0
InBandInitRequest_A	154198	4108	0	0
InBandInitSequence_A	154198	437	0	0
InitReq_A	154198	780	0	0
IntegFailKnownO_A	154198	116909	0	0
NoSpuriousAlertsDuringInit_A	154198	16183	0	0
NoSpuriousPingOksDuringInit_A	154198	15804	0	0
PingDiffOk_A	153314	116025	0	0
PingOkBypassDuringInit_A	154198	46	0	40
PingOkKnownO_A	154198	116909	0	0
PingPKnownO_A	154198	116909	0	0
PingPending_A	154198	829	0	119
PingRequest0_A	154198	0	0	0
PingResponse0_A	154198	769	0	0
gen_async_assert.Alert_A	79936	1322	0	0
gen_async_assert.PingResponse1_A	79936	329	0	0
gen_async_assert.SigInt_A	79936	249	0	91
gen_sync_assert.Alert_A	74262	3129	0	0
gen_sync_assert.PingResponse1_A	74262	349	0	0
gen_sync_assert.SigInt_A	74262	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153498	115234	0	158
T1	1294	1120	0	2
T2	1125	1048	0	2
T3	1193	1134	0	2
T7	1200	1014	0	2
T8	1015	929	0	2
T12	1077	990	0	2
T13	1083	1028	0	2
T14	1078	989	0	2
T15	1102	1001	0	2
T16	1203	1105	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	116909	0	0
T1	1308	1138	0	0
T2	1140	1065	0	0
T3	1209	1152	0	0
T7	1215	1033	0	0
T8	1031	947	0	0
T12	1092	1007	0	0
T13	1097	1044	0	0
T14	1091	1004	0	0
T15	1117	1018	0	0
T16	1219	1123	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	4108	0	0
T1	1308	66	0	0
T2	1140	47	0	0
T3	1209	73	0	0
T7	1215	57	0	0
T8	1031	40	0	0
T12	1092	45	0	0
T13	1097	49	0	0
T14	1091	46	0	0
T15	1117	51	0	0
T16	1219	105	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	437	0	0
T1	1308	2	0	0
T2	1140	1	0	0
T3	1209	4	0	0
T7	1215	2	0	0
T8	1031	2	0	0
T12	1092	2	0	0
T13	1097	2	0	0
T14	1091	3	0	0
T15	1117	2	0	0
T16	1219	5	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	780	0	0
T1	1308	12	0	0
T2	1140	11	0	0
T3	1209	14	0	0
T7	1215	10	0	0
T8	1031	7	0	0
T12	1092	8	0	0
T13	1097	10	0	0
T14	1091	8	0	0
T15	1117	9	0	0
T16	1219	15	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	116909	0	0
T1	1308	1138	0	0
T2	1140	1065	0	0
T3	1209	1152	0	0
T7	1215	1033	0	0
T8	1031	947	0	0
T12	1092	1007	0	0
T13	1097	1044	0	0
T14	1091	1004	0	0
T15	1117	1018	0	0
T16	1219	1123	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	16183	0	0
T1	1308	244	0	0
T2	1140	223	0	0
T3	1209	278	0	0
T7	1215	210	0	0
T8	1031	143	0	0
T12	1092	154	0	0
T13	1097	199	0	0
T14	1091	167	0	0
T15	1117	176	0	0
T16	1219	292	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	15804	0	0
T1	1308	237	0	0
T2	1140	209	0	0
T3	1209	249	0	0
T7	1215	196	0	0
T8	1031	137	0	0
T12	1092	150	0	0
T13	1097	185	0	0
T14	1091	165	0	0
T15	1117	164	0	0
T16	1219	290	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153314	116025	0	0
T1	1293	1123	0	0
T2	1126	1051	0	0
T3	1195	1138	0	0
T7	1199	1017	0	0
T8	1017	933	0	0
T12	1079	994	0	0
T13	1081	1028	0	0
T14	1078	991	0	0
T15	1101	1002	0	0
T16	1204	1108	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	46	0	40
T1	0	0	0	1
T7	1215	1	0	0
T8	1031	0	0	0
T11	1132	1	0	0
T13	1097	1	0	0
T14	1091	0	0	0
T15	1117	1	0	0
T16	1219	0	0	0
T17	1096	1	0	0
T18	1118	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	1151	0	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	116909	0	0
T1	1308	1138	0	0
T2	1140	1065	0	0
T3	1209	1152	0	0
T7	1215	1033	0	0
T8	1031	947	0	0
T12	1092	1007	0	0
T13	1097	1044	0	0
T14	1091	1004	0	0
T15	1117	1018	0	0
T16	1219	1123	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	116909	0	0
T1	1308	1138	0	0
T2	1140	1065	0	0
T3	1209	1152	0	0
T7	1215	1033	0	0
T8	1031	947	0	0
T12	1092	1007	0	0
T13	1097	1044	0	0
T14	1091	1004	0	0
T15	1117	1018	0	0
T16	1219	1123	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	829	0	119
T1	1308	11	0	1
T2	1140	11	0	1
T3	1209	11	0	1
T7	1215	11	0	1
T8	1031	11	0	1
T12	1092	11	0	1
T13	1097	11	0	1
T14	1091	11	0	1
T15	1117	11	0	1
T16	1219	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154198	769	0	0
T1	1308	10	0	0
T2	1140	10	0	0
T3	1209	10	0	0
T7	1215	9	0	0
T8	1031	9	0	0
T12	1092	10	0	0
T13	1097	10	0	0
T14	1091	10	0	0
T15	1117	10	0	0
T16	1219	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79936	1322	0	0
T1	1308	6	0	0
T2	1140	6	0	0
T3	1209	5	0	0
T7	1215	9	0	0
T8	1031	9	0	0
T12	1092	9	0	0
T13	1097	7	0	0
T14	1091	8	0	0
T15	1117	8	0	0
T16	1219	3	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79936	329	0	0
T1	1308	10	0	0
T2	1140	10	0	0
T3	1209	9	0	0
T7	1215	7	0	0
T8	1031	7	0	0
T12	1092	8	0	0
T13	1097	9	0	0
T14	1091	9	0	0
T15	1117	9	0	0
T16	1219	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79936	249	0	91
T1	1308	6	0	2
T2	1140	7	0	2
T3	1209	7	0	2
T7	1215	8	0	2
T8	1031	6	0	3
T12	1092	6	0	2
T13	1097	5	0	3
T14	1091	6	0	2
T15	1117	5	0	3
T16	1219	6	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74262	3129	0	0
T24	891	7	0	0
T25	1033	9	0	0
T26	986	10	0	0
T33	895	11	0	0
T34	984	10	0	0
T35	892	12	0	0
T36	916	9	0	0
T37	865	9	0	0
T38	1054	6	0	0
T39	887	8	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74262	349	0	0
T24	891	6	0	0
T25	1033	8	0	0
T26	986	8	0	0
T33	895	8	0	0
T34	984	10	0	0
T35	892	9	0	0
T36	916	10	0	0
T37	865	10	0	0
T38	1054	10	0	0
T39	887	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74262	40	0	0
T24	891	1	0	0
T25	1033	1	0	0
T26	986	1	0	0
T33	895	1	0	0
T34	984	1	0	0
T35	892	1	0	0
T36	916	1	0	0
T37	865	1	0	0
T38	1054	1	0	0
T39	887	1	0	0