Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T10,T11,T12

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T13,T8,T14	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T3,T15,T13
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T13,T8,T16
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T7,T8,T17
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T2,T18,T17

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	153264	115473	0	158
AlertKnownO_A	153961	117150	0	0
InBandInitRequest_A	153961	4266	0	0
InBandInitSequence_A	153961	413	0	0
InitReq_A	153961	770	0	0
IntegFailKnownO_A	153961	117150	0	0
NoSpuriousAlertsDuringInit_A	153961	16555	0	0
NoSpuriousPingOksDuringInit_A	153961	16173	0	0
PingDiffOk_A	153030	116219	0	0
PingOkBypassDuringInit_A	153961	56	0	40
PingOkKnownO_A	153961	117150	0	0
PingPKnownO_A	153961	117150	0	0
PingPending_A	153961	829	0	119
PingRequest0_A	153961	0	0	0
PingResponse0_A	153961	778	0	0
gen_async_assert.Alert_A	80401	1315	0	0
gen_async_assert.PingResponse1_A	80401	311	0	0
gen_async_assert.SigInt_A	80401	243	0	94
gen_sync_assert.Alert_A	73560	3158	0	0
gen_sync_assert.PingResponse1_A	73560	355	0	0
gen_sync_assert.SigInt_A	73560	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153264	115473	0	158
T1	1049	981	0	2
T2	1139	1037	0	2
T3	1155	1056	0	2
T7	1119	1054	0	2
T8	1242	1069	0	2
T9	1195	1103	0	2
T13	1130	993	0	2
T15	1024	963	0	2
T19	1025	959	0	2
T20	1115	1027	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	117150	0	0
T1	1065	999	0	0
T2	1154	1054	0	0
T3	1171	1074	0	0
T7	1134	1071	0	0
T8	1257	1088	0	0
T9	1209	1119	0	0
T13	1145	1012	0	0
T15	1040	981	0	0
T19	1040	976	0	0
T20	1131	1045	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	4266	0	0
T1	1065	51	0	0
T2	1154	67	0	0
T3	1171	83	0	0
T7	1134	54	0	0
T8	1257	62	0	0
T9	1209	77	0	0
T13	1145	75	0	0
T15	1040	41	0	0
T19	1040	35	0	0
T20	1131	53	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	413	0	0
T1	1065	2	0	0
T2	1154	1	0	0
T3	1171	3	0	0
T7	1134	2	0	0
T8	1257	2	0	0
T9	1209	3	0	0
T13	1145	3	0	0
T15	1040	2	0	0
T19	1040	2	0	0
T20	1131	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	770	0	0
T1	1065	9	0	0
T2	1154	11	0	0
T3	1171	14	0	0
T7	1134	13	0	0
T8	1257	12	0	0
T9	1209	15	0	0
T13	1145	10	0	0
T15	1040	6	0	0
T19	1040	7	0	0
T20	1131	10	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	117150	0	0
T1	1065	999	0	0
T2	1154	1054	0	0
T3	1171	1074	0	0
T7	1134	1071	0	0
T8	1257	1088	0	0
T9	1209	1119	0	0
T13	1145	1012	0	0
T15	1040	981	0	0
T19	1040	976	0	0
T20	1131	1045	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	16555	0	0
T1	1065	178	0	0
T2	1154	217	0	0
T3	1171	263	0	0
T7	1134	253	0	0
T8	1257	257	0	0
T9	1209	291	0	0
T13	1145	215	0	0
T15	1040	127	0	0
T19	1040	147	0	0
T20	1131	197	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	16173	0	0
T1	1065	160	0	0
T2	1154	213	0	0
T3	1171	245	0	0
T7	1134	250	0	0
T8	1257	253	0	0
T9	1209	275	0	0
T13	1145	207	0	0
T15	1040	123	0	0
T19	1040	142	0	0
T20	1131	195	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153030	116219	0	0
T1	1051	985	0	0
T2	1137	1037	0	0
T3	1158	1061	0	0
T7	1117	1054	0	0
T8	1242	1073	0	0
T9	1191	1101	0	0
T13	1130	997	0	0
T15	1023	964	0	0
T19	1023	959	0	0
T20	1117	1031	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	56	0	40
T1	1065	2	0	1
T2	1154	1	0	0
T3	1171	1	0	0
T7	1134	0	0	0
T8	1257	0	0	0
T9	1209	1	0	0
T11	0	0	0	1
T13	1145	2	0	0
T14	0	2	0	0
T15	1040	0	0	0
T18	0	1	0	0
T19	1040	1	0	0
T20	1131	2	0	0
T21	0	2	0	0
T22	0	0	0	1
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	117150	0	0
T1	1065	999	0	0
T2	1154	1054	0	0
T3	1171	1074	0	0
T7	1134	1071	0	0
T8	1257	1088	0	0
T9	1209	1119	0	0
T13	1145	1012	0	0
T15	1040	981	0	0
T19	1040	976	0	0
T20	1131	1045	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	117150	0	0
T1	1065	999	0	0
T2	1154	1054	0	0
T3	1171	1074	0	0
T7	1134	1071	0	0
T8	1257	1088	0	0
T9	1209	1119	0	0
T13	1145	1012	0	0
T15	1040	981	0	0
T19	1040	976	0	0
T20	1131	1045	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	829	0	119
T1	1065	11	0	1
T2	1154	11	0	1
T3	1171	11	0	1
T7	1134	11	0	1
T8	1257	11	0	1
T9	1209	11	0	1
T13	1145	11	0	1
T15	1040	11	0	1
T19	1040	11	0	1
T20	1131	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153961	778	0	0
T1	1065	10	0	0
T2	1154	8	0	0
T3	1171	10	0	0
T7	1134	9	0	0
T8	1257	9	0	0
T9	1209	10	0	0
T13	1145	10	0	0
T15	1040	10	0	0
T19	1040	10	0	0
T20	1131	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80401	1315	0	0
T1	1065	7	0	0
T2	1154	7	0	0
T3	1171	5	0	0
T7	1134	5	0	0
T8	1257	5	0	0
T9	1209	4	0	0
T13	1145	8	0	0
T15	1040	10	0	0
T19	1040	9	0	0
T20	1131	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80401	311	0	0
T1	1065	7	0	0
T2	1154	7	0	0
T3	1171	8	0	0
T7	1134	8	0	0
T8	1257	8	0	0
T9	1209	6	0	0
T13	1145	5	0	0
T15	1040	8	0	0
T19	1040	7	0	0
T20	1131	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80401	243	0	94
T1	1065	6	0	3
T2	1154	5	0	2
T3	1171	6	0	3
T7	1134	7	0	3
T8	1257	8	0	2
T9	1209	5	0	3
T13	1145	7	0	3
T15	1040	8	0	3
T19	1040	6	0	3
T20	1131	6	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73560	3158	0	0
T22	906	8	0	0
T23	1012	8	0	0
T24	892	9	0	0
T25	882	9	0	0
T26	789	10	0	0
T30	948	9	0	0
T31	880	11	0	0
T32	1018	7	0	0
T33	986	9	0	0
T34	973	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73560	355	0	0
T22	906	7	0	0
T23	1012	8	0	0
T24	892	9	0	0
T25	882	9	0	0
T26	789	9	0	0
T30	948	10	0	0
T31	880	10	0	0
T32	1018	10	0	0
T33	986	10	0	0
T34	973	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73560	40	0	0
T22	906	1	0	0
T23	1012	1	0	0
T24	892	1	0	0
T25	882	1	0	0
T26	789	1	0	0
T30	948	1	0	0
T31	880	1	0	0
T32	1018	1	0	0
T33	986	1	0	0
T34	973	1	0	0