Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_sender	95.52	100.00	100.00	100.00	100.00	95.83	77.27

---

Module Instance : prim_alert_tb.i_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	193	32	32	100.00
ALWAYS	276	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	1	1
145	1	1
146	1	1
163	1	1
167	1	1
171	1	1
172	1	1
175	1	1
177	1	1
178	1	1
182	1	1
183	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
214	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE
226	1	1
227	1	1
229	1	1
230	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
242	1	1
246	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
282	1	1
283	1	1
284	1	1
285	1	1

---

Cond Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (ack_sigint | ping_sigint)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (alert_req | alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (alert_clr ? 1'b0 : alert_req_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (alert_test_i | alert_test_set_q)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (alert_clr ? 1'b0 : alert_test_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (alert_req_trigger | alert_test_trigger)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       177
 EXPRESSION (ping_set_q | ping_event)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (ping_clr ? 1'b0 : ping_trigger)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       182
 EXPRESSION (alert_clr & alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       202
 EXPRESSION (alert_trigger || ping_trigger)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (alert_trigger ? AlertHsPhase1 : PingHsPhase1)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T11,T12	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_ack_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_alert_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertHsPhase1	203	Covered	T1,T2,T3
AlertHsPhase2	211	Covered	T1,T2,T3
Idle	246	Covered	T1,T2,T3
Pause0	220	Covered	T1,T2,T3
Pause1	242	Covered	T1,T2,T3
PingHsPhase1	203	Covered	T1,T2,T3
PingHsPhase2	227	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertHsPhase1->AlertHsPhase2	211	Covered	T1,T2,T3
AlertHsPhase1->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Pause0	220	Covered	T1,T2,T3
Idle->AlertHsPhase1	203	Covered	T1,T2,T3
Idle->PingHsPhase1	203	Covered	T1,T2,T3
Pause0->Idle	256	Covered	T38,T31,T39
Pause0->Pause1	242	Covered	T1,T2,T3
Pause1->Idle	246	Covered	T1,T2,T3
PingHsPhase1->Idle	256	Covered	T1,T2,T3
PingHsPhase1->PingHsPhase2	227	Covered	T1,T2,T3
PingHsPhase2->Idle	256	Covered	T2,T7,T13
PingHsPhase2->Pause0	237	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	172	2	2	100.00
TERNARY	178	2	2	100.00
TERNARY	167	2	2	100.00
CASE	199	14	13	92.86
IF	255	2	2	100.00
IF	276	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	(ping_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	199	case (state_q)
-2-:	202	if ((alert_trigger || ping_trigger))
-3-:	203	(alert_trigger) ? 
-4-:	210	if (ack_level)
-5-:	219	if ((!ack_level))
-6-:	226	if (ack_level)
-7-:	235	if ((!ack_level))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	1	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	0	-	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	1	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	0	-	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	1	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	0	-	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	1	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	0	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	255	if (sigint_detected)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	276	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	17	77.27
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	17	77.27

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertHs_A	157412	1128	0	0
AlertPKnownO_A	157412	119343	0	0
AlertState0_A	157412	119343	0	0
AlertTest1_A	157412	80	0	0
AlertTestHs_A	157412	80	0	0
gen_async_assert.DiffEncoding_A	83926	56995	0	0
gen_async_assert.InBandInitFsm_A	83926	117	0	160
gen_async_assert.InBandInitPing_A	83926	117	0	160
gen_async_assert.PingHs_A	83926	384	0	0
gen_async_assert.SigIntAck_A	83926	117	0	200
gen_async_assert.SigIntPing_A	83926	117	0	200
gen_fatal_assert.AlertState1_A	116245	6396	0	0
gen_fatal_assert.AlertState2_A	116245	46880	0	0
gen_fatal_assert.AlertState3_A	116245	4314	0	0
gen_recov_assert.AlertState1_A	41167	6817	0	0
gen_recov_assert.AlertState2_A	41167	0	0	0
gen_sync_assert.DiffEncoding_A	73486	51396	0	0
gen_sync_assert.InBandInitFsm_A	73486	0	0	0
gen_sync_assert.InBandInitPing_A	73486	0	0	0
gen_sync_assert.PingHs_A	73486	375	0	0
gen_sync_assert.SigIntAck_A	73486	0	0	0
gen_sync_assert.SigIntPing_A	73486	0	0	0

AlertHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157412	1128	0	0
T1	1103	16	0	0
T2	1172	14	0	0
T3	1160	17	0	0
T7	1138	14	0	0
T8	1156	19	0	0
T10	1273	17	0	0
T13	1114	15	0	0
T17	1157	16	0	0
T18	1091	16	0	0
T19	1114	16	0	0

AlertPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157412	119343	0	0
T1	1103	1018	0	0
T2	1172	1105	0	0
T3	1160	1098	0	0
T7	1138	1053	0	0
T8	1156	1092	0	0
T10	1273	1117	0	0
T13	1114	1026	0	0
T17	1157	1068	0	0
T18	1091	1004	0	0
T19	1114	1055	0	0

AlertState0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157412	119343	0	0
T1	1103	1018	0	0
T2	1172	1105	0	0
T3	1160	1098	0	0
T7	1138	1053	0	0
T8	1156	1092	0	0
T10	1273	1117	0	0
T13	1114	1026	0	0
T17	1157	1068	0	0
T18	1091	1004	0	0
T19	1114	1055	0	0

AlertTest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157412	80	0	0
T1	1103	1	0	0
T2	1172	1	0	0
T3	1160	1	0	0
T7	1138	1	0	0
T8	1156	1	0	0
T10	1273	1	0	0
T13	1114	1	0	0
T17	1157	1	0	0
T18	1091	1	0	0
T19	1114	1	0	0

AlertTestHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157412	80	0	0
T1	1103	1	0	0
T2	1172	1	0	0
T3	1160	1	0	0
T7	1138	1	0	0
T8	1156	1	0	0
T10	1273	1	0	0
T13	1114	1	0	0
T17	1157	1	0	0
T18	1091	1	0	0
T19	1114	1	0	0

gen_async_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83926	56995	0	0
T1	1103	912	0	0
T2	1172	952	0	0
T3	1160	937	0	0
T7	1138	919	0	0
T8	1156	938	0	0
T10	1273	943	0	0
T13	1114	919	0	0
T17	1157	937	0	0
T18	1091	882	0	0
T19	1114	928	0	0

gen_async_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83926	117	0	160
T1	1103	3	0	4
T2	1172	4	0	4
T3	1160	3	0	4
T7	1138	3	0	4
T8	1156	3	0	4
T10	1273	3	0	4
T13	1114	3	0	4
T17	1157	2	0	4
T18	1091	2	0	4
T19	1114	3	0	4

gen_async_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83926	117	0	160
T1	1103	3	0	4
T2	1172	4	0	4
T3	1160	3	0	4
T7	1138	3	0	4
T8	1156	3	0	4
T10	1273	3	0	4
T13	1114	3	0	4
T17	1157	2	0	4
T18	1091	2	0	4
T19	1114	3	0	4

gen_async_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83926	384	0	0
T1	1103	11	0	0
T2	1172	10	0	0
T3	1160	9	0	0
T7	1138	9	0	0
T8	1156	9	0	0
T10	1273	10	0	0
T13	1114	10	0	0
T17	1157	8	0	0
T18	1091	10	0	0
T19	1114	10	0	0

gen_async_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83926	117	0	200
T1	1103	3	0	5
T2	1172	4	0	5
T3	1160	3	0	5
T7	1138	3	0	5
T8	1156	3	0	5
T10	1273	3	0	5
T13	1114	3	0	5
T17	1157	2	0	5
T18	1091	2	0	5
T19	1114	3	0	5

gen_async_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83926	117	0	200
T1	1103	3	0	5
T2	1172	4	0	5
T3	1160	3	0	5
T7	1138	3	0	5
T8	1156	3	0	5
T10	1273	3	0	5
T13	1114	3	0	5
T17	1157	2	0	5
T18	1091	2	0	5
T19	1114	3	0	5

gen_fatal_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116245	6396	0	0
T4	3008	250	0	0
T9	2899	214	0	0
T15	3089	254	0	0
T23	2994	256	0	0
T40	3278	274	0	0
T41	3078	215	0	0
T42	2775	193	0	0
T43	3146	226	0	0
T44	3343	231	0	0
T45	3121	241	0	0

gen_fatal_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116245	46880	0	0
T4	3008	1307	0	0
T9	2899	1134	0	0
T15	3089	1178	0	0
T23	2994	1216	0	0
T40	3278	1428	0	0
T41	3078	1325	0	0
T42	2775	1003	0	0
T43	3146	1437	0	0
T44	3343	1579	0	0
T45	3121	1288	0	0

gen_fatal_assert.AlertState3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116245	4314	0	0
T4	3008	68	0	0
T9	2899	58	0	0
T15	3089	59	0	0
T23	2994	61	0	0
T40	3278	71	0	0
T41	3078	69	0	0
T42	2775	53	0	0
T43	3146	74	0	0
T44	3343	83	0	0
T45	3121	65	0	0

gen_recov_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41167	6817	0	0
T1	1103	251	0	0
T2	1172	266	0	0
T3	1160	272	0	0
T7	1138	224	0	0
T8	1156	288	0	0
T10	1273	290	0	0
T13	1114	232	0	0
T17	1157	259	0	0
T18	1091	238	0	0
T19	1114	265	0	0

gen_recov_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41167	0	0	0

gen_sync_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73486	51396	0	0
T25	884	746	0	0
T26	953	817	0	0
T27	910	742	0	0
T28	838	709	0	0
T29	821	715	0	0
T30	950	771	0	0
T34	901	750	0	0
T35	968	751	0	0
T36	914	751	0	0
T37	850	725	0	0

gen_sync_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73486	0	0	0

gen_sync_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73486	0	0	0

gen_sync_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73486	375	0	0
T25	884	9	0	0
T26	953	9	0	0
T27	910	9	0	0
T28	838	9	0	0
T29	821	8	0	0
T30	950	9	0	0
T34	901	10	0	0
T35	968	10	0	0
T36	914	10	0	0
T37	850	10	0	0

gen_sync_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73486	0	0	0

gen_sync_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73486	0	0	0