Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T7,T10
1	0	Covered	T11

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T12	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T3,T12
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T12,T10,T13
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T12,T14,T15
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T16,T7,T17

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	154964	116574	0	158
AlertKnownO_A	155648	118259	0	0
InBandInitRequest_A	155648	4244	0	0
InBandInitSequence_A	155648	431	0	0
InitReq_A	155648	772	0	0
IntegFailKnownO_A	155648	118259	0	0
NoSpuriousAlertsDuringInit_A	155648	16516	0	0
NoSpuriousPingOksDuringInit_A	155648	16165	0	0
PingDiffOk_A	154768	117379	0	0
PingOkBypassDuringInit_A	155648	38	0	40
PingOkKnownO_A	155648	118259	0	0
PingPKnownO_A	155648	118259	0	0
PingPending_A	155648	828	0	119
PingRequest0_A	155648	0	0	0
PingResponse0_A	155648	773	0	0
gen_async_assert.Alert_A	81633	1366	0	0
gen_async_assert.PingResponse1_A	81633	313	0	0
gen_async_assert.SigInt_A	81633	237	0	88
gen_sync_assert.Alert_A	74015	3213	0	0
gen_sync_assert.PingResponse1_A	74015	357	0	0
gen_sync_assert.SigInt_A	74015	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154964	116574	0	158
T1	1163	1013	0	2
T2	1125	1029	0	2
T3	1187	1034	0	2
T9	1086	1023	0	2
T12	1183	1048	0	2
T16	1069	967	0	2
T18	1062	1005	0	2
T19	1039	986	0	2
T20	1045	993	0	2
T21	1139	1068	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	118259	0	0
T1	1178	1031	0	0
T2	1140	1046	0	0
T3	1201	1052	0	0
T9	1100	1039	0	0
T12	1197	1066	0	0
T16	1083	983	0	0
T18	1075	1020	0	0
T19	1053	1002	0	0
T20	1059	1009	0	0
T21	1155	1086	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	4244	0	0
T1	1178	45	0	0
T2	1140	22	0	0
T3	1201	74	0	0
T9	1100	55	0	0
T12	1197	76	0	0
T16	1083	42	0	0
T18	1075	48	0	0
T19	1053	47	0	0
T20	1059	54	0	0
T21	1155	85	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	431	0	0
T1	1178	3	0	0
T2	1140	1	0	0
T3	1201	6	0	0
T9	1100	3	0	0
T12	1197	4	0	0
T16	1083	2	0	0
T18	1075	2	0	0
T19	1053	2	0	0
T20	1059	3	0	0
T21	1155	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	772	0	0
T1	1178	8	0	0
T2	1140	6	0	0
T3	1201	10	0	0
T9	1100	10	0	0
T12	1197	12	0	0
T16	1083	7	0	0
T18	1075	10	0	0
T19	1053	8	0	0
T20	1059	9	0	0
T21	1155	13	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	118259	0	0
T1	1178	1031	0	0
T2	1140	1046	0	0
T3	1201	1052	0	0
T9	1100	1039	0	0
T12	1197	1066	0	0
T16	1083	983	0	0
T18	1075	1020	0	0
T19	1053	1002	0	0
T20	1059	1009	0	0
T21	1155	1086	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	16516	0	0
T1	1178	161	0	0
T2	1140	131	0	0
T3	1201	210	0	0
T9	1100	196	0	0
T12	1197	247	0	0
T16	1083	145	0	0
T18	1075	194	0	0
T19	1053	159	0	0
T20	1059	180	0	0
T21	1155	254	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	16165	0	0
T1	1178	161	0	0
T2	1140	131	0	0
T3	1201	209	0	0
T9	1100	185	0	0
T12	1197	240	0	0
T16	1083	143	0	0
T18	1075	191	0	0
T19	1053	158	0	0
T20	1059	178	0	0
T21	1155	250	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154768	117379	0	0
T1	1160	1013	0	0
T2	1127	1033	0	0
T3	1188	1039	0	0
T9	1086	1025	0	0
T12	1184	1053	0	0
T16	1068	968	0	0
T18	1060	1005	0	0
T19	1041	990	0	0
T20	1046	996	0	0
T21	1139	1070	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	38	0	40
T1	0	0	0	1
T6	0	0	0	1
T7	1061	0	0	0
T8	0	1	0	0
T9	1100	0	0	0
T10	1174	1	0	0
T12	1197	1	0	0
T14	1034	1	0	0
T16	1083	0	0	0
T18	1075	1	0	0
T19	1053	1	0	0
T20	1059	2	0	0
T21	1155	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	118259	0	0
T1	1178	1031	0	0
T2	1140	1046	0	0
T3	1201	1052	0	0
T9	1100	1039	0	0
T12	1197	1066	0	0
T16	1083	983	0	0
T18	1075	1020	0	0
T19	1053	1002	0	0
T20	1059	1009	0	0
T21	1155	1086	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	118259	0	0
T1	1178	1031	0	0
T2	1140	1046	0	0
T3	1201	1052	0	0
T9	1100	1039	0	0
T12	1197	1066	0	0
T16	1083	983	0	0
T18	1075	1020	0	0
T19	1053	1002	0	0
T20	1059	1009	0	0
T21	1155	1086	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	828	0	119
T1	1178	11	0	1
T2	1140	11	0	1
T3	1201	11	0	1
T9	1100	11	0	1
T12	1197	11	0	1
T16	1083	11	0	1
T18	1075	11	0	1
T19	1053	11	0	1
T20	1059	11	0	1
T21	1155	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155648	773	0	0
T1	1178	10	0	0
T2	1140	10	0	0
T3	1201	9	0	0
T9	1100	10	0	0
T12	1197	10	0	0
T16	1083	10	0	0
T18	1075	10	0	0
T19	1053	10	0	0
T20	1059	10	0	0
T21	1155	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81633	1366	0	0
T1	1178	9	0	0
T2	1140	7	0	0
T3	1201	6	0	0
T9	1100	7	0	0
T12	1197	6	0	0
T16	1083	7	0	0
T18	1075	8	0	0
T19	1053	8	0	0
T20	1059	7	0	0
T21	1155	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81633	313	0	0
T1	1178	10	0	0
T2	1140	10	0	0
T3	1201	9	0	0
T9	1100	8	0	0
T12	1197	6	0	0
T16	1083	9	0	0
T18	1075	8	0	0
T19	1053	9	0	0
T20	1059	8	0	0
T21	1155	7	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81633	237	0	88
T1	1178	5	0	3
T2	1140	8	0	3
T3	1201	5	0	2
T9	1100	5	0	2
T12	1197	5	0	2
T16	1083	6	0	2
T18	1075	5	0	3
T19	1053	5	0	2
T20	1059	7	0	1
T21	1155	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74015	3213	0	0
T24	1061	9	0	0
T32	801	10	0	0
T33	871	11	0	0
T34	1050	6	0	0
T35	1092	9	0	0
T36	979	11	0	0
T37	874	10	0	0
T38	887	11	0	0
T39	892	9	0	0
T40	893	12	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74015	357	0	0
T24	1061	6	0	0
T32	801	9	0	0
T33	871	10	0	0
T34	1050	10	0	0
T35	1092	8	0	0
T36	979	10	0	0
T37	874	10	0	0
T38	887	10	0	0
T39	892	9	0	0
T40	893	7	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74015	40	0	0
T24	1061	1	0	0
T32	801	1	0	0
T33	871	1	0	0
T34	1050	1	0	0
T35	1092	1	0	0
T36	979	1	0	0
T37	874	1	0	0
T38	887	1	0	0
T39	892	1	0	0
T40	893	1	0	0