Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T10
1	0	Covered	T11,T12,T13

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T10,T14	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T14,T15,T16
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T14,T17,T5
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T3,T9,T18

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	151423	114711	0	156
AlertKnownO_A	152103	116363	0	0
InBandInitRequest_A	152103	3963	0	0
InBandInitSequence_A	152103	391	0	0
InitReq_A	152103	747	0	0
IntegFailKnownO_A	152103	116363	0	0
NoSpuriousAlertsDuringInit_A	152103	16000	0	0
NoSpuriousPingOksDuringInit_A	152103	15657	0	0
PingDiffOk_A	151234	115494	0	0
PingOkBypassDuringInit_A	152103	40	0	40
PingOkKnownO_A	152103	116363	0	0
PingPKnownO_A	152103	116363	0	0
PingPending_A	152103	817	0	118
PingRequest0_A	152103	0	0	0
PingResponse0_A	152103	756	0	0
gen_async_assert.Alert_A	79188	1359	0	0
gen_async_assert.PingResponse1_A	79188	311	0	0
gen_async_assert.SigInt_A	79188	231	0	90
gen_sync_assert.Alert_A	72915	3121	0	0
gen_sync_assert.PingResponse1_A	72915	360	0	0
gen_sync_assert.SigInt_A	72915	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151423	114711	0	156
T1	1122	947	0	2
T2	1091	1000	0	2
T3	1136	1076	0	2
T7	1160	1075	0	2
T8	1058	1001	0	2
T9	1160	1085	0	2
T10	1173	997	0	2
T14	1130	991	0	2
T19	1144	1046	0	2
T20	1025	957	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	116363	0	0
T1	1137	966	0	0
T2	1105	1016	0	0
T3	1151	1093	0	0
T7	1175	1092	0	0
T8	1073	1018	0	0
T9	1175	1102	0	0
T10	1186	1014	0	0
T14	1144	1009	0	0
T19	1159	1063	0	0
T20	1039	973	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	3963	0	0
T1	1137	20	0	0
T2	1105	27	0	0
T3	1151	59	0	0
T7	1175	66	0	0
T8	1073	47	0	0
T9	1175	51	0	0
T10	1186	48	0	0
T14	1144	38	0	0
T19	1159	52	0	0
T20	1039	52	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	391	0	0
T1	1137	1	0	0
T2	1105	0	0	0
T3	1151	3	0	0
T7	1175	1	0	0
T8	1073	2	0	0
T9	1175	1	0	0
T10	1186	1	0	0
T14	1144	0	0	0
T15	0	5	0	0
T19	1159	0	0	0
T20	1039	2	0	0
T21	0	2	0	0
T22	0	1	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	747	0	0
T1	1137	5	0	0
T2	1105	7	0	0
T3	1151	11	0	0
T7	1175	12	0	0
T8	1073	10	0	0
T9	1175	12	0	0
T10	1186	10	0	0
T14	1144	8	0	0
T19	1159	12	0	0
T20	1039	7	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	116363	0	0
T1	1137	966	0	0
T2	1105	1016	0	0
T3	1151	1093	0	0
T7	1175	1092	0	0
T8	1073	1018	0	0
T9	1175	1102	0	0
T10	1186	1014	0	0
T14	1144	1009	0	0
T19	1159	1063	0	0
T20	1039	973	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	16000	0	0
T1	1137	106	0	0
T2	1105	145	0	0
T3	1151	213	0	0
T7	1175	244	0	0
T8	1073	198	0	0
T9	1175	231	0	0
T10	1186	200	0	0
T14	1144	175	0	0
T19	1159	236	0	0
T20	1039	137	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	15657	0	0
T1	1137	106	0	0
T2	1105	145	0	0
T3	1151	213	0	0
T7	1175	217	0	0
T8	1073	182	0	0
T9	1175	228	0	0
T10	1186	181	0	0
T14	1144	172	0	0
T19	1159	230	0	0
T20	1039	133	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151234	115494	0	0
T1	1123	952	0	0
T2	1092	1003	0	0
T3	1133	1075	0	0
T7	1159	1076	0	0
T8	1060	1005	0	0
T9	1161	1088	0	0
T10	1169	997	0	0
T14	1139	1004	0	0
T19	1142	1046	0	0
T20	1023	957	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	40	0	40
T4	0	1	0	0
T7	1175	1	0	0
T8	1073	0	0	0
T9	1175	0	0	0
T10	1186	3	0	0
T14	1144	0	0	0
T15	1253	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	1159	1	0	0
T20	1039	0	0	0
T21	1118	2	0	0
T22	1100	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	116363	0	0
T1	1137	966	0	0
T2	1105	1016	0	0
T3	1151	1093	0	0
T7	1175	1092	0	0
T8	1073	1018	0	0
T9	1175	1102	0	0
T10	1186	1014	0	0
T14	1144	1009	0	0
T19	1159	1063	0	0
T20	1039	973	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	116363	0	0
T1	1137	966	0	0
T2	1105	1016	0	0
T3	1151	1093	0	0
T7	1175	1092	0	0
T8	1073	1018	0	0
T9	1175	1102	0	0
T10	1186	1014	0	0
T14	1144	1009	0	0
T19	1159	1063	0	0
T20	1039	973	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	817	0	118
T1	1137	11	0	1
T2	1105	11	0	1
T3	1151	11	0	1
T7	1175	11	0	1
T8	1073	11	0	1
T9	1175	11	0	1
T10	1186	11	0	1
T14	1144	10	0	1
T19	1159	11	0	1
T20	1039	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152103	756	0	0
T1	1137	10	0	0
T2	1105	10	0	0
T3	1151	10	0	0
T7	1175	9	0	0
T8	1073	9	0	0
T9	1175	9	0	0
T10	1186	10	0	0
T14	1144	9	0	0
T19	1159	9	0	0
T20	1039	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79188	1359	0	0
T1	1137	12	0	0
T2	1105	8	0	0
T3	1151	8	0	0
T7	1175	8	0	0
T8	1073	6	0	0
T9	1175	9	0	0
T10	1186	8	0	0
T14	1144	9	0	0
T19	1159	6	0	0
T20	1039	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79188	311	0	0
T1	1137	10	0	0
T2	1105	10	0	0
T3	1151	10	0	0
T7	1175	8	0	0
T8	1073	8	0	0
T9	1175	8	0	0
T10	1186	6	0	0
T14	1144	8	0	0
T19	1159	6	0	0
T20	1039	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79188	231	0	90
T1	1137	7	0	3
T2	1105	8	0	2
T3	1151	6	0	3
T7	1175	5	0	3
T8	1073	5	0	2
T9	1175	6	0	3
T10	1186	6	0	2
T14	1144	7	0	0
T15	0	0	0	3
T19	1159	6	0	3
T20	1039	7	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72915	3121	0	0
T26	811	10	0	0
T27	884	8	0	0
T36	847	11	0	0
T37	912	10	0	0
T38	1084	9	0	0
T39	898	8	0	0
T40	857	12	0	0
T41	911	11	0	0
T42	964	10	0	0
T43	912	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72915	360	0	0
T26	811	8	0	0
T27	884	8	0	0
T36	847	9	0	0
T37	912	10	0	0
T38	1084	10	0	0
T39	898	10	0	0
T40	857	10	0	0
T41	911	8	0	0
T42	964	10	0	0
T43	912	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72915	40	0	0
T26	811	1	0	0
T27	884	1	0	0
T36	847	1	0	0
T37	912	1	0	0
T38	1084	1	0	0
T39	898	1	0	0
T40	857	1	0	0
T41	911	1	0	0
T42	964	1	0	0
T43	912	1	0	0