Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T9,T10,T11

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T12,T13,T14	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T3,T12
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T13,T15,T16
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T2,T17,T18
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T8,T19,T13

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	153625	115654	0	158
AlertKnownO_A	154323	117340	0	0
InBandInitRequest_A	154323	4137	0	0
InBandInitSequence_A	154323	411	0	0
InitReq_A	154323	745	0	0
IntegFailKnownO_A	154323	117340	0	0
NoSpuriousAlertsDuringInit_A	154323	16031	0	0
NoSpuriousPingOksDuringInit_A	154323	15667	0	0
PingDiffOk_A	153468	116485	0	0
PingOkBypassDuringInit_A	154323	62	0	40
PingOkKnownO_A	154323	117340	0	0
PingPKnownO_A	154323	117340	0	0
PingPending_A	154323	827	0	119
PingRequest0_A	154323	0	0	0
PingResponse0_A	154323	769	0	0
gen_async_assert.Alert_A	81074	1387	0	0
gen_async_assert.PingResponse1_A	81074	311	0	0
gen_async_assert.SigInt_A	81074	236	0	86
gen_sync_assert.Alert_A	73249	3156	0	0
gen_sync_assert.PingResponse1_A	73249	352	0	0
gen_sync_assert.SigInt_A	73249	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153625	115654	0	158
T1	1103	1051	0	2
T2	1050	980	0	2
T3	1100	1039	0	2
T7	1111	1013	0	2
T8	1040	969	0	2
T12	1168	1020	0	2
T19	1045	963	0	2
T20	1117	1060	0	2
T21	1052	986	0	2
T22	1020	947	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	117340	0	0
T1	1119	1069	0	0
T2	1064	996	0	0
T3	1116	1057	0	0
T7	1126	1030	0	0
T8	1054	985	0	0
T12	1183	1039	0	0
T19	1059	979	0	0
T20	1131	1076	0	0
T21	1067	1003	0	0
T22	1034	963	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	4137	0	0
T1	1119	66	0	0
T2	1064	38	0	0
T3	1116	64	0	0
T7	1126	52	0	0
T8	1054	22	0	0
T12	1183	45	0	0
T19	1059	40	0	0
T20	1131	47	0	0
T21	1067	51	0	0
T22	1034	41	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	411	0	0
T1	1119	2	0	0
T2	1064	1	0	0
T3	1116	4	0	0
T7	1126	2	0	0
T8	1054	0	0	0
T12	1183	3	0	0
T13	0	3	0	0
T19	1059	0	0	0
T20	1131	1	0	0
T21	1067	1	0	0
T22	1034	0	0	0
T23	0	5	0	0
T24	0	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	745	0	0
T1	1119	12	0	0
T2	1064	7	0	0
T3	1116	10	0	0
T7	1126	9	0	0
T8	1054	7	0	0
T12	1183	8	0	0
T19	1059	8	0	0
T20	1131	10	0	0
T21	1067	8	0	0
T22	1034	6	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	117340	0	0
T1	1119	1069	0	0
T2	1064	996	0	0
T3	1116	1057	0	0
T7	1126	1030	0	0
T8	1054	985	0	0
T12	1183	1039	0	0
T19	1059	979	0	0
T20	1131	1076	0	0
T21	1067	1003	0	0
T22	1034	963	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	16031	0	0
T1	1119	235	0	0
T2	1064	150	0	0
T3	1116	200	0	0
T7	1126	187	0	0
T8	1054	146	0	0
T12	1183	160	0	0
T19	1059	156	0	0
T20	1131	200	0	0
T21	1067	166	0	0
T22	1034	127	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	15667	0	0
T1	1119	220	0	0
T2	1064	135	0	0
T3	1116	198	0	0
T7	1126	182	0	0
T8	1054	131	0	0
T12	1183	159	0	0
T19	1059	152	0	0
T20	1131	189	0	0
T21	1067	161	0	0
T22	1034	114	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153468	116485	0	0
T1	1104	1054	0	0
T2	1050	982	0	0
T3	1103	1044	0	0
T7	1109	1013	0	0
T8	1040	971	0	0
T12	1169	1025	0	0
T19	1047	967	0	0
T20	1113	1058	0	0
T21	1050	986	0	0
T22	1020	949	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	62	0	40
T2	1064	1	0	0
T3	1116	2	0	0
T7	1126	0	0	0
T8	1054	0	0	0
T12	1183	1	0	0
T13	1142	0	0	0
T15	0	0	0	1
T19	1059	1	0	0
T20	1131	0	0	0
T21	1067	1	0	0
T22	1034	1	0	0
T23	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1
T36	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	117340	0	0
T1	1119	1069	0	0
T2	1064	996	0	0
T3	1116	1057	0	0
T7	1126	1030	0	0
T8	1054	985	0	0
T12	1183	1039	0	0
T19	1059	979	0	0
T20	1131	1076	0	0
T21	1067	1003	0	0
T22	1034	963	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	117340	0	0
T1	1119	1069	0	0
T2	1064	996	0	0
T3	1116	1057	0	0
T7	1126	1030	0	0
T8	1054	985	0	0
T12	1183	1039	0	0
T19	1059	979	0	0
T20	1131	1076	0	0
T21	1067	1003	0	0
T22	1034	963	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	827	0	119
T1	1119	11	0	1
T2	1064	11	0	1
T3	1116	11	0	1
T7	1126	11	0	1
T8	1054	11	0	1
T12	1183	11	0	1
T19	1059	11	0	1
T20	1131	11	0	1
T21	1067	11	0	1
T22	1034	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154323	769	0	0
T1	1119	9	0	0
T2	1064	9	0	0
T3	1116	10	0	0
T7	1126	9	0	0
T8	1054	10	0	0
T12	1183	10	0	0
T19	1059	9	0	0
T20	1131	10	0	0
T21	1067	10	0	0
T22	1034	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81074	1387	0	0
T1	1119	6	0	0
T2	1064	10	0	0
T3	1116	8	0	0
T7	1126	7	0	0
T8	1054	9	0	0
T12	1183	8	0	0
T19	1059	8	0	0
T20	1131	7	0	0
T21	1067	8	0	0
T22	1034	10	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81074	311	0	0
T1	1119	8	0	0
T2	1064	8	0	0
T3	1116	8	0	0
T7	1126	7	0	0
T8	1054	8	0	0
T12	1183	9	0	0
T19	1059	7	0	0
T20	1131	10	0	0
T21	1067	7	0	0
T22	1034	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81074	236	0	86
T1	1119	7	0	3
T2	1064	6	0	2
T3	1116	8	0	2
T7	1126	6	0	2
T8	1054	5	0	2
T12	1183	5	0	3
T19	1059	6	0	2
T20	1131	6	0	2
T21	1067	8	0	3
T22	1034	5	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73249	3156	0	0
T28	901	10	0	0
T29	914	10	0	0
T30	913	10	0	0
T31	979	7	0	0
T37	937	9	0	0
T38	1040	7	0	0
T39	836	9	0	0
T40	906	12	0	0
T41	855	10	0	0
T42	869	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73249	352	0	0
T28	901	6	0	0
T29	914	7	0	0
T30	913	9	0	0
T31	979	8	0	0
T37	937	9	0	0
T38	1040	10	0	0
T39	836	9	0	0
T40	906	10	0	0
T41	855	9	0	0
T42	869	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73249	40	0	0
T28	901	1	0	0
T29	914	1	0	0
T30	913	1	0	0
T31	979	1	0	0
T37	937	1	0	0
T38	1040	1	0	0
T39	836	1	0	0
T40	906	1	0	0
T41	855	1	0	0
T42	869	1	0	0