Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T10
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T10,T11	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T2,T3,T10
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T11,T12,T13
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T10,T11,T14
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T15,T16,T17

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	151291	113404	0	156
AlertKnownO_A	151979	115072	0	0
InBandInitRequest_A	151979	3861	0	0
InBandInitSequence_A	151979	390	0	0
InitReq_A	151979	737	0	0
IntegFailKnownO_A	151979	115072	0	0
NoSpuriousAlertsDuringInit_A	151979	15741	0	0
NoSpuriousPingOksDuringInit_A	151979	15419	0	0
PingDiffOk_A	151105	114198	0	0
PingOkBypassDuringInit_A	151979	45	0	40
PingOkKnownO_A	151979	115072	0	0
PingPKnownO_A	151979	115072	0	0
PingPending_A	151979	818	0	118
PingRequest0_A	151979	0	0	0
PingResponse0_A	151979	755	0	0
gen_async_assert.Alert_A	78486	1311	0	0
gen_async_assert.PingResponse1_A	78486	318	0	0
gen_async_assert.SigInt_A	78486	238	0	88
gen_sync_assert.Alert_A	73493	3133	0	0
gen_sync_assert.PingResponse1_A	73493	347	0	0
gen_sync_assert.SigInt_A	73493	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151291	113404	0	156
T1	995	943	0	2
T2	1190	1038	0	2
T3	1061	991	0	2
T7	1074	997	0	2
T8	1141	1044	0	2
T10	1065	945	0	2
T11	1283	1135	0	2
T14	1062	969	0	2
T18	1102	1010	0	2
T19	1070	975	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	115072	0	0
T1	1011	961	0	0
T2	1206	1058	0	0
T3	1077	1009	0	0
T7	1088	1013	0	0
T8	1156	1061	0	0
T10	1080	964	0	0
T11	1298	1154	0	0
T14	1078	987	0	0
T18	1116	1026	0	0
T19	1084	991	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	3861	0	0
T1	1011	40	0	0
T2	1206	46	0	0
T3	1077	32	0	0
T7	1088	46	0	0
T8	1156	61	0	0
T10	1080	21	0	0
T11	1298	72	0	0
T14	1078	43	0	0
T18	1116	43	0	0
T19	1084	50	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	390	0	0
T1	1011	2	0	0
T2	1206	0	0	0
T3	1077	1	0	0
T7	1088	2	0	0
T8	1156	2	0	0
T9	0	1	0	0
T10	1080	0	0	0
T11	1298	2	0	0
T14	1078	2	0	0
T18	1116	1	0	0
T19	1084	1	0	0
T20	0	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	737	0	0
T1	1011	7	0	0
T2	1206	11	0	0
T3	1077	9	0	0
T7	1088	10	0	0
T8	1156	10	0	0
T10	1080	5	0	0
T11	1298	15	0	0
T14	1078	6	0	0
T18	1116	8	0	0
T19	1084	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	115072	0	0
T1	1011	961	0	0
T2	1206	1058	0	0
T3	1077	1009	0	0
T7	1088	1013	0	0
T8	1156	1061	0	0
T10	1080	964	0	0
T11	1298	1154	0	0
T14	1078	987	0	0
T18	1116	1026	0	0
T19	1084	991	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	15741	0	0
T1	1011	142	0	0
T2	1206	241	0	0
T3	1077	184	0	0
T7	1088	192	0	0
T8	1156	197	0	0
T10	1080	127	0	0
T11	1298	315	0	0
T14	1078	123	0	0
T18	1116	163	0	0
T19	1084	176	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	15419	0	0
T1	1011	138	0	0
T2	1206	215	0	0
T3	1077	167	0	0
T7	1088	178	0	0
T8	1156	195	0	0
T10	1080	116	0	0
T11	1298	310	0	0
T14	1078	120	0	0
T18	1116	163	0	0
T19	1084	174	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151105	114198	0	0
T1	993	943	0	0
T2	1188	1040	0	0
T3	1063	995	0	0
T7	1071	996	0	0
T8	1140	1045	0	0
T10	1064	948	0	0
T11	1281	1137	0	0
T14	1064	973	0	0
T18	1100	1010	0	0
T19	1069	976	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	45	0	40
T1	1011	2	0	0
T2	1206	1	0	0
T3	1077	1	0	0
T6	0	0	0	1
T7	1088	0	0	0
T8	1156	1	0	0
T10	1080	0	0	0
T11	1298	1	0	0
T12	0	1	0	0
T14	1078	1	0	0
T15	0	1	0	0
T18	1116	0	0	0
T19	1084	2	0	0
T21	0	1	0	0
T22	0	0	0	1
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	115072	0	0
T1	1011	961	0	0
T2	1206	1058	0	0
T3	1077	1009	0	0
T7	1088	1013	0	0
T8	1156	1061	0	0
T10	1080	964	0	0
T11	1298	1154	0	0
T14	1078	987	0	0
T18	1116	1026	0	0
T19	1084	991	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	115072	0	0
T1	1011	961	0	0
T2	1206	1058	0	0
T3	1077	1009	0	0
T7	1088	1013	0	0
T8	1156	1061	0	0
T10	1080	964	0	0
T11	1298	1154	0	0
T14	1078	987	0	0
T18	1116	1026	0	0
T19	1084	991	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	818	0	118
T1	1011	11	0	1
T2	1206	11	0	1
T3	1077	11	0	1
T7	1088	11	0	1
T8	1156	11	0	1
T10	1080	11	0	1
T11	1298	11	0	1
T14	1078	11	0	1
T18	1116	11	0	1
T19	1084	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151979	755	0	0
T1	1011	10	0	0
T2	1206	10	0	0
T3	1077	10	0	0
T7	1088	9	0	0
T8	1156	9	0	0
T10	1080	10	0	0
T11	1298	10	0	0
T14	1078	10	0	0
T18	1116	10	0	0
T19	1084	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78486	1311	0	0
T1	1011	8	0	0
T2	1206	7	0	0
T3	1077	9	0	0
T7	1088	8	0	0
T8	1156	6	0	0
T10	1080	10	0	0
T11	1298	5	0	0
T14	1078	11	0	0
T18	1116	5	0	0
T19	1084	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78486	318	0	0
T1	1011	7	0	0
T2	1206	8	0	0
T3	1077	8	0	0
T7	1088	8	0	0
T8	1156	8	0	0
T10	1080	10	0	0
T11	1298	7	0	0
T14	1078	8	0	0
T18	1116	10	0	0
T19	1084	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78486	238	0	88
T1	1011	6	0	2
T2	1206	6	0	2
T3	1077	8	0	2
T7	1088	5	0	2
T8	1156	8	0	3
T10	1080	6	0	2
T11	1298	6	0	2
T14	1078	6	0	3
T18	1116	7	0	2
T19	1084	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73493	3133	0	0
T22	809	11	0	0
T23	892	12	0	0
T24	941	11	0	0
T25	901	9	0	0
T26	830	11	0	0
T31	905	8	0	0
T32	899	11	0	0
T33	900	7	0	0
T34	843	10	0	0
T35	984	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73493	347	0	0
T22	809	8	0	0
T23	892	9	0	0
T24	941	7	0	0
T25	901	9	0	0
T26	830	9	0	0
T31	905	10	0	0
T32	899	10	0	0
T33	900	9	0	0
T34	843	7	0	0
T35	984	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73493	40	0	0
T22	809	1	0	0
T23	892	1	0	0
T24	941	1	0	0
T25	901	1	0	0
T26	830	1	0	0
T31	905	1	0	0
T32	899	1	0	0
T33	900	1	0	0
T34	843	1	0	0
T35	984	1	0	0