Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T9,T10

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T11,T12	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T1,T13,T14
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T15,T14,T16
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T3,T17,T16

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	156276	117887	0	160
AlertKnownO_A	156978	119588	0	0
InBandInitRequest_A	156978	4314	0	0
InBandInitSequence_A	156978	442	0	0
InitReq_A	156978	802	0	0
IntegFailKnownO_A	156978	119588	0	0
NoSpuriousAlertsDuringInit_A	156978	16817	0	0
NoSpuriousPingOksDuringInit_A	156978	16457	0	0
PingDiffOk_A	156077	118687	0	0
PingOkBypassDuringInit_A	156978	48	0	40
PingOkKnownO_A	156978	119588	0	0
PingPKnownO_A	156978	119588	0	0
PingPending_A	156978	839	0	120
PingRequest0_A	156978	0	0	0
PingResponse0_A	156978	780	0	0
gen_async_assert.Alert_A	83387	1409	0	0
gen_async_assert.PingResponse1_A	83387	332	0	0
gen_async_assert.SigInt_A	83387	253	0	96
gen_sync_assert.Alert_A	73591	3068	0	0
gen_sync_assert.PingResponse1_A	73591	349	0	0
gen_sync_assert.SigInt_A	73591	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156276	117887	0	160
T1	1227	1072	0	2
T2	1153	1051	0	2
T3	1110	1040	0	2
T7	1069	1003	0	2
T11	1218	1047	0	2
T12	1177	1031	0	2
T18	1144	1061	0	2
T19	1057	957	0	2
T20	1065	1012	0	2
T21	1042	968	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	119588	0	0
T1	1242	1091	0	0
T2	1167	1067	0	0
T3	1126	1058	0	0
T7	1083	1019	0	0
T11	1233	1066	0	0
T12	1192	1050	0	0
T18	1159	1078	0	0
T19	1072	974	0	0
T20	1078	1027	0	0
T21	1057	985	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	4314	0	0
T1	1242	69	0	0
T2	1167	80	0	0
T3	1126	49	0	0
T7	1083	52	0	0
T11	1233	46	0	0
T12	1192	72	0	0
T18	1159	63	0	0
T19	1072	28	0	0
T20	1078	57	0	0
T21	1057	48	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	442	0	0
T1	1242	2	0	0
T2	1167	3	0	0
T3	1126	1	0	0
T7	1083	2	0	0
T11	1233	2	0	0
T12	1192	4	0	0
T18	1159	2	0	0
T19	1072	0	0	0
T20	1078	3	0	0
T21	1057	3	0	0
T22	0	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	802	0	0
T1	1242	13	0	0
T2	1167	13	0	0
T3	1126	10	0	0
T7	1083	10	0	0
T11	1233	7	0	0
T12	1192	11	0	0
T18	1159	12	0	0
T19	1072	6	0	0
T20	1078	10	0	0
T21	1057	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	119588	0	0
T1	1242	1091	0	0
T2	1167	1067	0	0
T3	1126	1058	0	0
T7	1083	1019	0	0
T11	1233	1066	0	0
T12	1192	1050	0	0
T18	1159	1078	0	0
T19	1072	974	0	0
T20	1078	1027	0	0
T21	1057	985	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	16817	0	0
T1	1242	260	0	0
T2	1167	248	0	0
T3	1126	202	0	0
T7	1083	196	0	0
T11	1233	158	0	0
T12	1192	224	0	0
T18	1159	235	0	0
T19	1072	129	0	0
T20	1078	197	0	0
T21	1057	177	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	16457	0	0
T1	1242	256	0	0
T2	1167	233	0	0
T3	1126	200	0	0
T7	1083	175	0	0
T11	1233	156	0	0
T12	1192	220	0	0
T18	1159	231	0	0
T19	1072	128	0	0
T20	1078	195	0	0
T21	1057	173	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077	118687	0	0
T1	1225	1074	0	0
T2	1151	1051	0	0
T3	1109	1041	0	0
T7	1064	1000	0	0
T11	1218	1051	0	0
T12	1180	1038	0	0
T18	1142	1061	0	0
T19	1059	961	0	0
T20	1066	1015	0	0
T21	1038	966	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	48	0	40
T2	1167	1	0	0
T3	1126	1	0	0
T7	1083	1	0	0
T8	0	1	0	0
T9	0	0	0	1
T11	1233	0	0	0
T12	1192	2	0	0
T16	0	0	0	1
T18	1159	1	0	0
T19	1072	1	0	0
T20	1078	0	0	0
T21	1057	1	0	0
T22	1123	1	0	0
T23	0	1	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	119588	0	0
T1	1242	1091	0	0
T2	1167	1067	0	0
T3	1126	1058	0	0
T7	1083	1019	0	0
T11	1233	1066	0	0
T12	1192	1050	0	0
T18	1159	1078	0	0
T19	1072	974	0	0
T20	1078	1027	0	0
T21	1057	985	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	119588	0	0
T1	1242	1091	0	0
T2	1167	1067	0	0
T3	1126	1058	0	0
T7	1083	1019	0	0
T11	1233	1066	0	0
T12	1192	1050	0	0
T18	1159	1078	0	0
T19	1072	974	0	0
T20	1078	1027	0	0
T21	1057	985	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	839	0	120
T1	1242	11	0	1
T2	1167	11	0	1
T3	1126	11	0	1
T7	1083	11	0	1
T11	1233	11	0	1
T12	1192	11	0	1
T18	1159	11	0	1
T19	1072	11	0	1
T20	1078	11	0	1
T21	1057	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156978	780	0	0
T1	1242	9	0	0
T2	1167	9	0	0
T3	1126	9	0	0
T7	1083	10	0	0
T11	1233	10	0	0
T12	1192	10	0	0
T18	1159	9	0	0
T19	1072	10	0	0
T20	1078	9	0	0
T21	1057	9	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83387	1409	0	0
T1	1242	4	0	0
T2	1167	7	0	0
T3	1126	8	0	0
T7	1083	8	0	0
T11	1233	6	0	0
T12	1192	6	0	0
T18	1159	7	0	0
T19	1072	8	0	0
T20	1078	7	0	0
T21	1057	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83387	332	0	0
T1	1242	8	0	0
T2	1167	7	0	0
T3	1126	8	0	0
T7	1083	8	0	0
T11	1233	9	0	0
T12	1192	7	0	0
T18	1159	7	0	0
T19	1072	9	0	0
T20	1078	9	0	0
T21	1057	7	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83387	253	0	96
T1	1242	6	0	3
T2	1167	6	0	2
T3	1126	6	0	2
T7	1083	6	0	3
T11	1233	8	0	2
T12	1192	7	0	1
T18	1159	6	0	2
T19	1072	6	0	2
T20	1078	5	0	2
T21	1057	5	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73591	3068	0	0
T9	925	9	0	0
T16	1017	11	0	0
T24	873	10	0	0
T25	1023	8	0	0
T32	1052	10	0	0
T33	907	10	0	0
T34	1026	12	0	0
T35	929	9	0	0
T36	958	8	0	0
T37	955	8	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73591	349	0	0
T9	925	7	0	0
T16	1017	9	0	0
T24	873	9	0	0
T25	1023	9	0	0
T32	1052	9	0	0
T33	907	9	0	0
T34	1026	8	0	0
T35	929	9	0	0
T36	958	10	0	0
T37	955	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73591	40	0	0
T9	925	1	0	0
T16	1017	1	0	0
T24	873	1	0	0
T25	1023	1	0	0
T32	1052	1	0	0
T33	907	1	0	0
T34	1026	1	0	0
T35	929	1	0	0
T36	958	1	0	0
T37	955	1	0	0